107 lines
4.2 KiB
VHDL
107 lines
4.2 KiB
VHDL
-- file: clk_wiz_0.vhd
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--
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-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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------------------------------------------------------------------------------
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-- User entered comments
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------------------------------------------------------------------------------
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-- None
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--
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------------------------------------------------------------------------------
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-- Output Output Phase Duty Cycle Pk-to-Pk Phase
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-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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------------------------------------------------------------------------------
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-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
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--
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------------------------------------------------------------------------------
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-- Input Clock Freq (MHz) Input Jitter (UI)
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------------------------------------------------------------------------------
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-- __primary_________100.000____________0.010
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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entity clk_wiz_0 is
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end clk_wiz_0;
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architecture xilinx of clk_wiz_0 is
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attribute CORE_GENERATION_INFO : string;
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attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
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component clk_wiz_0_clk_wiz
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end component;
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begin
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U0: clk_wiz_0_clk_wiz
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port map (
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-- Clock in ports
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clk_in1 => clk_in1,
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-- Clock out ports
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clk_out1 => clk_out1
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);
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end xilinx;
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