54 lines
1.1 KiB
VHDL
54 lines
1.1 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 05.07.2021 15:20:28
|
|
-- Design Name:
|
|
-- Module Name: Compteur_Y - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
use work.ScreenProperties.all;
|
|
|
|
entity Compteur_Y is
|
|
Port ( CLK : in STD_LOGIC;
|
|
RST : in STD_LOGIC;
|
|
Value : out Y_T);
|
|
end Compteur_Y;
|
|
|
|
architecture Behavioral of Compteur_Y is
|
|
|
|
signal current : Y_T := 0;
|
|
|
|
begin
|
|
|
|
process
|
|
begin
|
|
wait until CLK'event and CLK = '1';
|
|
if (RST = '0') then
|
|
current <= 0;
|
|
else
|
|
current <= current + 1;
|
|
if (current = screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1) then
|
|
current <= 0;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
Value <= current;
|
|
|
|
end Behavioral;
|