118 lines
4.1 KiB
VHDL
118 lines
4.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18.04.2021 22:28:40
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-- Design Name:
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-- Module Name: Test_Etape1_LectureInstruction - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Etape1_LectureInstruction is
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-- Port ( );
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end Test_Etape1_LectureInstruction;
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architecture Behavioral of Test_Etape1_LectureInstruction is
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component Etage1_LectureInstruction is
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Generic (Instruction_size_in_memory : Natural;
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Addr_size_mem_instruction : Natural;
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Mem_instruction_size : Natural;
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Nb_bits : Natural;
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Instruction_bus_size : Natural;
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Nb_registres : Natural;
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Mem_adresse_retour_size : Natural;
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Adresse_size_mem_adresse_retour : Natural;
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Instructions_critiques_lecture : STD_LOGIC_VECTOR;
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Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
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Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
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Code_Instruction_JMP : STD_LOGIC_VECTOR;
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Code_Instruction_JMZ : STD_LOGIC_VECTOR;
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Code_Instruction_CALL : STD_LOGIC_VECTOR;
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Code_Instruction_RET : STD_LOGIC_VECTOR);
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Z : in STD_LOGIC;
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A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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end component;
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signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_CLK : STD_LOGIC := '0';
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signal my_RST : STD_LOGIC := '1';
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signal my_Z : STD_LOGIC := '1';
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constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
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constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
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constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
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constant CLK_period : time := 10 ns;
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begin
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instance : Etage1_LectureInstruction
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generic map (Instruction_size_in_memory => 28,
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Addr_size_mem_instruction => 4,
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Mem_instruction_size => 16,
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Nb_bits => 8,
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Instruction_bus_size => 4,
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Nb_registres => 16,
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Mem_adresse_retour_size => 4,
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Adresse_size_mem_adresse_retour => 2,
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Instructions_critiques_lecture => Instructions_critiques_lecture,
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Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
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Instructions_critiques_ecriture => Instructions_critiques_ecriture,
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Code_Instruction_JMP => "1100",
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Code_Instruction_JMZ => "1101",
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Code_Instruction_CALL => "1110",
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Code_Instruction_RET => "1111"
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)
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port map (
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CLK => my_CLK,
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RST => my_RST,
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z => my_Z,
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A => my_A,
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B => my_B,
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C => my_C,
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Instruction => my_Instruction
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);
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CLK_process :process
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begin
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my_CLK <= '0';
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wait for CLK_period/2;
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my_CLK <= '1';
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wait for CLK_period/2;
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end process;
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process
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begin
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wait;
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end process;
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end Behavioral;
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