84 lines
2.3 KiB
VHDL
84 lines
2.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.04.2021 21:25:53
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-- Design Name:
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-- Module Name: TestALU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity TestALU is
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-- Port ( );
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end TestALU;
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architecture Behavioral of TestALU is
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component ALU is
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Generic (Nb_bits : Natural);
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Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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OP : in STD_LOGIC_VECTOR (1 downto 0);
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S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end component;
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signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
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signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
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signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
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signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
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signal my_N : STD_LOGIC := '0';
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signal my_O : STD_LOGIC := '0';
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signal my_Z : STD_LOGIC := '0';
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signal my_C : STD_LOGIC := '0';
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begin
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instance : ALU
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generic map (Nb_bits => 16)
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port map (
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A => my_A,
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B => my_B,
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OP => my_OP,
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S => my_S,
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N => my_N,
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O => my_O,
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Z => my_Z,
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C => my_C
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);
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process
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begin
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my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
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my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
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my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
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wait;
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end process;
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end Behavioral;
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