Processeur/Processeur.srcs/sources_1/new/MUX.vhd

48 lines
1.3 KiB
VHDL

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-- Company:
-- Engineer:
--
-- Create Date: 17.04.2021 21:49:57
-- Design Name:
-- Module Name: MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end MUX;
architecture Behavioral of MUX is
begin
OUTPUT <= IN1 when (Bits_Controle(to_integer(unsigned(Instruction))) = '1') else
IN2;
end Behavioral;