57 lines
1.3 KiB
VHDL
57 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 08.05.2021 21:00:25
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-- Design Name:
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-- Module Name: Clock_Divider - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Clock_Divider is
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Port ( CLK_IN : in STD_LOGIC;
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CLK_OUT : out STD_LOGIC);
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end Clock_Divider;
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architecture Behavioral of Clock_Divider is
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signal N : Integer := 0;
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signal CLK : STD_LOGIC := '1';
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begin
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process
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begin
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wait until CLK_IN'event and CLK_IN = '1';
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N <= N + 1;
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if (N = 1000) then
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N <= 0;
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if (CLK = '1') then
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CLK <= '0';
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else
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CLK <= '1';
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end if;
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end if;
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end process;
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CLK_OUT <= CLK;
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end Behavioral;
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