Processeur/Processeur.srcs/sources_1/new/Clock_Divider.vhd

57 lines
1.3 KiB
VHDL

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08.05.2021 21:00:25
-- Design Name:
-- Module Name: Clock_Divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Clock_Divider is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end Clock_Divider;
architecture Behavioral of Clock_Divider is
signal N : Integer := 0;
signal CLK : STD_LOGIC := '1';
begin
process
begin
wait until CLK_IN'event and CLK_IN = '1';
N <= N + 1;
if (N = 1000) then
N <= 0;
if (CLK = '1') then
CLK <= '0';
else
CLK <= '1';
end if;
end if;
end process;
CLK_OUT <= CLK;
end Behavioral;