71 lines
2.4 KiB
VHDL
71 lines
2.4 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15.04.2021 08:23:48
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-- Design Name:
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-- Module Name: BancRegistres - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity BancRegistres is
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Generic (Nb_bits : Natural;
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Addr_size : Natural;
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Nb_regs : Natural);
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Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
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AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
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AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
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AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
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W : in STD_LOGIC;
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DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
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end BancRegistres;
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-- ASK MEILLEURE IDEE UN TABLEAU
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architecture Behavioral of BancRegistres is
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signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0');
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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REGISTRES <= (others => '0');
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else
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if (W = '1') then
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REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA;
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end if;
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end if;
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end process;
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QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
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QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
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QC <= REGISTRES (((to_integer(unsigned(AddrC)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrC)));
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end Behavioral;
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