85 lines
2.5 KiB
VHDL
85 lines
2.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13.04.2021 10:07:41
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-- Design Name:
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-- Module Name: ALU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALU is
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Generic (Nb_bits : Natural);
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Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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OP : in STD_LOGIC_VECTOR (2 downto 0);
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S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end ALU;
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architecture Behavioral of ALU is
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signal A9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
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signal B9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
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signal ADD : STD_LOGIC_VECTOR (Nb_bits downto 0);
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signal SUB : STD_LOGIC_VECTOR (Nb_bits downto 0);
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signal MUL : STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
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signal intern_N : STD_LOGIC;
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signal intern_Z : STD_LOGIC;
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constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
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constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
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begin
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A9 <= '0' & A;
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B9 <= '0' & B;
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ADD <= A9 + B9;
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SUB <= A9 - B9;
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MUL <= A * B;
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S <= ADD (Nb_bits-1 downto 0) when OP = "001" else
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SUB (Nb_bits-1 downto 0) when OP = "010" else
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MUL (Nb_bits-1 downto 0) when OP = "011" else
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-- Add division
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(0 => intern_N, others => '0') when OP = "101" else
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(0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
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(0 => intern_Z, others => '0') when OP = "111" else
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(others => '0');
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intern_N <= SUB (Nb_bits);
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intern_Z <= '1' when (SUB = ZERO_N1) else
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'0';
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N <= intern_N;
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O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
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'1';
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Z <= intern_Z;
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C <= ADD (Nb_bits);
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end Behavioral;
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