66 righe
No EOL
1,9 KiB
VHDL
66 righe
No EOL
1,9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17.04.2021 22:43:43
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-- Design Name:
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-- Module Name: Test_LC - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_LC is
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-- Port ( );
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end Test_LC;
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architecture Behavioral of Test_LC is
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component LC is
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Generic (Instruction_Vector_Size : Natural;
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Command_size : Natural;
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Bits_Controle : STD_LOGIC_VECTOR);
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Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
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Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
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end component;
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signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
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signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
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constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
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begin
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instance : LC
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generic map (Instruction_Vector_Size => 3,
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Command_size => 2,
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Bits_Controle => Bits_Controle)
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port map (
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Instruction => my_Instruction,
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Commande => my_Commande
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);
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process
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begin
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my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
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wait;
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end process;
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end Behavioral; |