62 lines
No EOL
1.8 KiB
VHDL
62 lines
No EOL
1.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.04.2021 14:35:04
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-- Design Name:
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-- Module Name: MemoireDonnees - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity MemoireDonnees is
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Generic (Nb_bits : Natural;
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Addr_size : Natural;
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Mem_size : Natural);
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Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
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RW : in STD_LOGIC;
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D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
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end MemoireDonnees;
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architecture Behavioral of MemoireDonnees is
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signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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MEMORY <= (others => '0');
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else
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if (RW = '0') then
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MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
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end if;
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end if;
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end process;
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D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
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end Behavioral; |