45 lines
1.3 KiB
VHDL
45 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17.04.2021 21:49:57
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-- Design Name:
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-- Module Name: LC - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LC is
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Generic (Instruction_Vector_Size : Natural;
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Command_size : Natural;
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Bits_Controle : STD_LOGIC_VECTOR);
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Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
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Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
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end LC;
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architecture Behavioral of LC is
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begin
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Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
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end Behavioral;
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