99 lines
2.7 KiB
VHDL
99 lines
2.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.04.2021 12:58:02
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-- Design Name:
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-- Module Name: TestMemoireAdressesRetour - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity TestMemoireAdressesRetour is
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-- Port ( );
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end TestMemoireAdressesRetour;
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architecture Behavioral of TestMemoireAdressesRetour is
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component MemoireAdressesRetour is
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Generic (Nb_bits : Natural;
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Addr_size : Natural;
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Mem_size : Natural);
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Port ( R : in STD_LOGIC;
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W : in STD_LOGIC;
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D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
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E : out STD_LOGIC;
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F : out STD_LOGIC);
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end component;
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signal my_R : STD_LOGIC := '0';
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signal my_W : STD_LOGIC := '0';
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signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_RST : STD_LOGIC := '0';
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signal my_CLK : STD_LOGIC := '0';
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signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
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signal my_E : STD_LOGIC;
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signal my_F : STD_LOGIC;
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constant CLK_period : time := 10 ns;
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begin
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instance : MemoireAdressesRetour
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generic map (Nb_bits => 8,
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Addr_size => 2,
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Mem_size => 4
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)
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port map (
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R => my_R,
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W => my_W,
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D_IN => my_D_IN,
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RST => my_RST,
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CLK => my_CLK,
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D_OUT => my_D_OUT,
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E => my_E,
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F => my_F
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);
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CLK_process :process
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begin
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my_CLK <= '0';
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wait for CLK_period/2;
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my_CLK <= '1';
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wait for CLK_period/2;
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end process;
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process
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begin
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my_RST <= '1' after 0 ns, '0' after 100 ns;
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my_R <= '1' after 20 ns, '0' after 30 ns;
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my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
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my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
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wait;
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end process;
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end Behavioral;
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