95 lines
2.2 KiB
VHDL
95 lines
2.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 01.07.2021 13:37:43
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-- Design Name:
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-- Module Name: SystemKeyboard - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SystemKeyboard is
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Port (CLK : in STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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led : out STD_LOGIC_VECTOR (0 to 10);
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btnC : in STD_LOGIC);
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end SystemKeyboard;
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architecture Behavioral of SystemKeyboard is
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component Keyboard
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Port (CLK : in STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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Data_read : in STD_LOGIC;
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Data_av : out STD_LOGIC;
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Data : out STD_LOGIC_VECTOR (0 to 6);
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alert : out STD_LOGIC);
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end component;
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signal intern_Data_read : STD_LOGIC := '0';
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signal intern_Data_av : STD_LOGIC := '0';
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signal Data_Read : STD_LOGIC_VECTOR (0 to 6);
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begin
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instance_Keyboard : Keyboard
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port map (CLK => CLK,
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PS2Clk => PS2Clk,
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PS2Data => PS2Data,
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Data_read => intern_Data_read,
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Data_av => intern_Data_av,
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Data => Data_Read,
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alert => led(10));
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led(7) <= '0';
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led(8) <= intern_Data_av;
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led(9) <= intern_Data_read;
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process
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begin
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wait until CLK'event and CLK = '1';
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if (intern_Data_av = '1' and btnC = '1') then
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led(0 to 6) <= Data_read;
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intern_Data_read <= '1';
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else
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intern_Data_read <= '0';
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end if;
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end process;
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end Behavioral;
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