60 lines
No EOL
1.3 KiB
VHDL
60 lines
No EOL
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 05.07.2021 15:20:28
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-- Design Name:
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-- Module Name: Compteur_X - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.ScreenProperties.all;
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entity Compteur_X is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Value : out X_T;
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Carry : out STD_LOGIC);
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end Compteur_X;
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architecture Behavioral of Compteur_X is
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signal current : X_T := 0;
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signal intern_Carry : STD_LOGIC := '0';
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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current <= 0;
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else
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current <= current + 1;
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if (current = screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1) then
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intern_Carry <= '1';
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current <= 0;
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else
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intern_Carry <= '0';
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end if;
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end if;
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end process;
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Value <= current;
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Carry <= intern_Carry;
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end Behavioral; |