66 lines
1.8 KiB
VHDL
66 lines
1.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.04.2021 22:03:10
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-- Design Name:
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-- Module Name: System - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity System is
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Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
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btnL : in STD_LOGIC;
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btnC : in STD_LOGIC;
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btnR : in STD_LOGIC;
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btnD : in STD_LOGIC;
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LED : out STD_LOGIC_VECTOR (0 to 7);
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CLK : in STD_LOGIC);
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end System;
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architecture Structural of System is
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component ClockDivider1000
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Port ( clk_in : in STD_LOGIC;
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clk_out : out STD_LOGIC);
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end component;
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component Compteur
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Port ( CK : in STD_LOGIC;
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RST : in STD_LOGIC;
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SENS : in STD_LOGIC;
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LOAD : in STD_LOGIC;
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EN : in STD_LOGIC;
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Din : in STD_LOGIC_VECTOR (7 downto 0);
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Dout : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
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begin
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DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
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DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
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CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
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end Structural;
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