50 lines
1.3 KiB
VHDL
50 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.04.2021 21:44:36
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-- Design Name:
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-- Module Name: ClockDivider1000 - Structural
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ClockDivider1000 is
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Port ( clk_in : in STD_LOGIC;
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clk_out : out STD_LOGIC);
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end ClockDivider1000;
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architecture Structural of ClockDivider1000 is
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component ClockDivider10
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Port ( clk_in : in STD_LOGIC;
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clk_out : out STD_LOGIC);
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end component;
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signal aux1, aux2 : STD_LOGIC;
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begin
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U1: ClockDivider10 port map(clk_in, aux1);
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U2: ClockDivider10 port map(aux1, aux2);
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U3: ClockDivider10 port map(aux2, clk_out);
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end Structural;
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