74 lines
No EOL
2.1 KiB
VHDL
74 lines
No EOL
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17.04.2021 22:43:43
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-- Design Name:
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-- Module Name: Test_MUX - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_MUX is
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-- Port ( );
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end Test_MUX;
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architecture Behavioral of Test_MUX is
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component MUX is
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Generic (Nb_bits : Natural;
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Instruction_Vector_Size : Natural;
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Bits_Controle : STD_LOGIC_VECTOR);
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Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
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IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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end component;
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signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
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signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
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signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
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begin
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instance : MUX
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generic map (Nb_bits => 16,
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Instruction_Vector_Size => 4,
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Bits_Controle => x"aaaa")
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port map (
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Instruction => my_Instruction,
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IN1 => my_IN1,
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IN2 => my_IN2,
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OUTPUT => my_OUTPUT
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);
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process
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begin
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my_IN1 <= x"abcd";
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my_IN2 <= x"1234";
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my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
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wait;
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end process;
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end Behavioral; |