Processeur/Processeur.srcs/sources_1/new/SystemKeyboardScreen.vhd

231 lines
6.3 KiB
VHDL

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 10:04:44
-- Design Name:
-- Module Name: SystemKeyboardScreen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SystemKeyboardScreen is
Port ( CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC);
end SystemKeyboardScreen;
architecture Behavioral of SystemKeyboardScreen is
component Keyboard
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end component;
component VGAControler is
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
component Ecran is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in X_T;
Y : in Y_T;
OUT_ON : out STD_LOGIC);
end component;
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal Keyboard_Data_read : STD_LOGIC := '0';
signal Keyboard_Data_av : STD_LOGIC := '0';
signal Keyboard_Data : STD_LOGIC_VECTOR (0 to 6);
signal Screen_Data_av : STD_LOGIC := '0';
signal alert : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC := '1';
begin
instanceVGA : VGAControler
port map( VGA_RED => vgaRed,
VGA_BLUE => vgaBlue,
VGA_GREEN => vgaGreen,
VGA_HS => Hsync,
VGA_VS => Vsync,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => RST);
clk_wiz_0_inst : clk_wiz_0
port map (
clk_in1 => CLK,
clk_out1 => my_CLK
);
instance_Ecran : Ecran
port map ( CLK => CLK,
RST => RST,
Data_Av => Screen_Data_av,
Data_IN => Keyboard_Data,
X => my_X,
Y => my_Y,
OUT_ON => my_PIXEL_ON);
instance_Keyboard : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => Keyboard_Data_av,
Data_av => Keyboard_Data_av,
Data => Keyboard_Data,
alert => alert);
process
begin
wait until CLK'event and CLK = '1';
if (Keyboard_Data_av = '1') then
Screen_Data_av <= '1';
else
Screen_Data_av <= '0';
end if;
end process;
end Behavioral;
--entity SystemKeyboardScreen is
-- Port ( CLK : in STD_LOGIC;
-- led : out STD_LOGIC_VECTOR (0 to 0);
-- btnC : in STD_LOGIC;
-- sw : in STD_LOGIC_VECTOR (0 to 6));
--end SystemKeyboardScreen;
--architecture Behavioral of SystemKeyboardScreen is
-- component Ecran is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Data_Av : in STD_LOGIC;
-- Data_IN : in STD_LOGIC_VECTOR (0 to 6);
-- X : in X_T;
-- Y : in Y_T;
-- OUT_ON : out STD_LOGIC);
-- end component;
-- component Compteur_X is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Value : out X_T;
-- Carry : out STD_LOGIC);
-- end component;
-- component Compteur_Y is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Value : out Y_T);
-- end component;
-- signal my_X : X_T := 0;
-- signal my_Y : Y_T := 0;
-- signal Y_CLK : STD_LOGIC := '0';
-- signal RST : STD_LOGIC := '1';
--begin
-- X_Compteur : Compteur_X
-- port map (CLK => CLK,
-- RST => RST,
-- Value => my_X,
-- Carry => Y_CLK);
-- Y_Compteur : Compteur_Y
-- port map (CLK => Y_CLK,
-- RST => RST,
-- Value => my_Y);
-- instance_Ecran : Ecran
-- port map ( CLK => CLK,
-- RST => RST,
-- Data_Av => btnC,
-- Data_IN => sw,
-- X => my_X,
-- Y => my_Y,
-- OUT_ON => led(0));
--end Behavioral;