129 lines
3.5 KiB
VHDL
129 lines
3.5 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 28.06.2021 17:27:26
|
|
-- Design Name:
|
|
-- Module Name: ScreenSystem - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
use work.ScreenProperties.all;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity ScreenSystem is
|
|
Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
|
|
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
|
|
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
|
|
Hsync : out STD_LOGIC;
|
|
Vsync : out STD_LOGIC;
|
|
|
|
|
|
btnC : in STD_LOGIC;
|
|
CLK : in STD_LOGIC
|
|
);
|
|
end ScreenSystem;
|
|
|
|
architecture Behavioral of ScreenSystem is
|
|
|
|
component VGAControler is
|
|
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
|
|
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
|
|
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
|
|
VGA_HS : out STD_LOGIC;
|
|
VGA_VS : out STD_LOGIC;
|
|
|
|
X : out X_T;
|
|
Y : out Y_T;
|
|
PIXEL_ON : in STD_LOGIC;
|
|
|
|
CLK : in STD_LOGIC;
|
|
RST : in STD_LOGIC);
|
|
end component;
|
|
|
|
component clk_wiz_0
|
|
port
|
|
(-- Clock in ports
|
|
clk_in1 : in std_logic;
|
|
-- Clock out ports
|
|
clk_out1 : out std_logic
|
|
);
|
|
end component;
|
|
|
|
component Ecran is
|
|
Port ( CLK : in STD_LOGIC;
|
|
RST : in STD_LOGIC;
|
|
Data_Av : in STD_LOGIC;
|
|
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
|
|
X : in X_T;
|
|
Y : in Y_T;
|
|
OUT_ON : out STD_LOGIC);
|
|
end component;
|
|
|
|
signal my_X : X_T := 0;
|
|
signal my_Y : Y_T := 0;
|
|
signal my_PIXEL_ON : STD_LOGIC := '0';
|
|
|
|
signal my_CLK : STD_LOGIC := '0';
|
|
signal RST : STD_LOGIC;
|
|
|
|
begin
|
|
|
|
instanceVGA : VGAControler
|
|
port map( VGA_RED => vgaRed,
|
|
VGA_BLUE => vgaBlue,
|
|
VGA_GREEN => vgaGreen,
|
|
VGA_HS => Hsync,
|
|
VGA_VS => Vsync,
|
|
|
|
X => my_X,
|
|
Y => my_Y,
|
|
PIXEL_ON => my_PIXEL_ON,
|
|
|
|
CLK => my_CLK,
|
|
RST => RST);
|
|
|
|
|
|
clk_wiz_0_inst : clk_wiz_0
|
|
port map (
|
|
clk_in1 => CLK,
|
|
clk_out1 => my_CLK
|
|
);
|
|
|
|
|
|
instance_Ecran : Ecran
|
|
port map ( CLK => CLK,
|
|
RST => RST,
|
|
Data_Av => '0',
|
|
Data_IN => "0000000",
|
|
X => my_X,
|
|
Y => my_Y,
|
|
OUT_ON => my_PIXEL_ON);
|
|
|
|
-- Gestion du RST (inversion d'état)
|
|
RST <= '1' when btnC = '0' else
|
|
'0';
|
|
|
|
end Behavioral;
|