126 lines
3.5 KiB
VHDL
126 lines
3.5 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 01.07.2021 09:09:30
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-- Design Name:
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-- Module Name: KeyboardControler - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity KeyboardControler is
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Port (CLK : in STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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Data_av : out STD_LOGIC;
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Data : out STD_LOGIC_VECTOR (0 to 7);
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alert : out STD_LOGIC);
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end KeyboardControler;
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architecture Behavioral of KeyboardControler is
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subtype compteur_T is Natural range 0 to 10;
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signal compteur : compteur_T := 0;
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signal current_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
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signal previous_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
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signal parity : STD_LOGIC := '0';
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signal intern_alert : STD_LOGIC := '0';
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signal intern_Data_av : STD_LOGIC := '0';
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signal dejaSignale : boolean := false;
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begin
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process
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begin
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wait until PS2Clk'event and PS2Clk = '1';
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case compteur is
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when 0 =>
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parity <= '1';
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intern_alert <= '0';
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intern_Data_av <= '0';
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when 1 =>
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current_data(7) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 2 =>
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current_data(6) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 3 =>
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current_data(5) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 4 =>
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current_data(4) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 5 =>
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current_data(3) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 6 =>
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current_data(2) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 7 =>
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current_data(1) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 8 =>
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current_data(0) <= PS2Data;
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parity <= parity XOR PS2Data;
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when 9 =>
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if (parity = PS2Data) then
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intern_alert <= '0';
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else
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intern_alert <= '1';
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end if;
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when 10 =>
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if (intern_alert = '0') then
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previous_data <= current_data;
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if (not (previous_data = "11110000" or current_data = "11110000" or previous_data = "11100000")) then
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Data <= current_data;
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intern_Data_av <= '1';
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end if;
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end if;
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end case;
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compteur <= (compteur + 1) mod 11;
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end process;
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process
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begin
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wait until CLK'event and CLK = '1';
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if (intern_Data_av = '1' and not dejaSignale) then
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Data_av <= '1';
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dejaSignale <= true;
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else
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Data_av <= '0';
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end if;
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if (intern_Data_av = '0') then
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dejaSignale <= false;
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end if;
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end process;
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alert <= intern_alert;
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end Behavioral;
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