112 lines
3.8 KiB
VHDL
112 lines
3.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 13.04.2021 10:19:15
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-- Module Name: System - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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-- Description: Environnement du processeur, mapping entre le processeur et la carte
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--
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-- Dependencies:
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-- - Clock_Divider
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-- - Pipeline
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Lien avec le fichier de contraintes
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-- Récupération des leds pour STD_OUT
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-- Récupération des switchs pour STD_IN
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-- Récupération d'un bouton pour RST
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-- Récupération de la clock
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entity System is
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Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
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sw : in STD_LOGIC_VECTOR (7 downto 0);
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btnC : in STD_LOGIC;
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CLK : STD_LOGIC);
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end System;
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architecture Structural of System is
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component Pipeline is
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Generic (Nb_bits : Natural := 8;
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Instruction_En_Memoire_Size : Natural := 29;
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Addr_Memoire_Instruction_Size : Natural := 3;
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Memoire_Instruction_Size : Natural := 8;
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Instruction_Bus_Size : Natural := 5;
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Nb_Instructions : Natural := 32;
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Nb_Registres : Natural := 16;
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Addr_registres_size : Natural := 4;
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Memoire_Size : Natural := 32;
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Adresse_mem_size : Natural := 5;
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Memoire_Adresses_Retour_Size : Natural := 16;
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Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
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Port (CLK : STD_LOGIC;
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RST : STD_LOGIC;
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STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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end component;
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component Pipeline_NS is
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Generic (Nb_bits : Natural := 8;
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Instruction_En_Memoire_Size : Natural := 29;
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Addr_Memoire_Instruction_Size : Natural := 3;
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Memoire_Instruction_Size : Natural := 8;
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Instruction_Bus_Size : Natural := 5;
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Nb_Instructions : Natural := 32;
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Nb_Registres : Natural := 16;
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Memoire_Size : Natural := 32);
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Port (CLK : STD_LOGIC;
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RST : STD_LOGIC;
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STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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end component;
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component Clock_Divider is
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Port ( CLK_IN : in STD_LOGIC;
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CLK_OUT : out STD_LOGIC);
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end component;
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-- signaux auxiliaires
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signal my_RST : STD_LOGIC;
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signal my_CLK : STD_LOGIC;
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constant SECURISED : boolean := true;
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begin
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-- Diviseur de clock
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clk_div : Clock_Divider
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port map (CLK_IN => CLK,
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CLK_OUT => my_CLK);
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-- Generation du processeur en fonction de la condition sécurisé ou non
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instance: if (SECURISED) generate
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instance_securisee : entity work.Pipeline
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generic map (Addr_Memoire_Instruction_Size => 8,
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Memoire_Instruction_Size => 256)
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port map (CLK => my_CLK,
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RST => my_RST,
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STD_IN => sw,
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STD_OUT => led);
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else generate
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instance_non_securisee : entity work.Pipeline_NS
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generic map (Addr_Memoire_Instruction_Size => 8,
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Memoire_Instruction_Size => 256)
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port map (CLK => my_CLK,
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RST => my_RST,
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STD_IN => sw,
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STD_OUT => led);
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end generate;
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-- Gestion du RST (inversion d'état)
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my_RST <= '1' when btnC = '0' else
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'0';
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end Structural;
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