---------------------------------------------------------------------------------- -- Company: INSA-Toulouse -- Engineer: Paul Faure -- -- Create Date: 13.04.2021 10:19:15 -- Module Name: System - Behavioral -- Project Name: Processeur sécurisé -- Target Devices: Basys 3 ARTIX7 -- Tool Versions: Vivado 2016.4 -- Description: Environnement du processeur, mapping entre le processeur et la carte -- -- Dependencies: -- - Clock_Divider -- - Pipeline ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Lien avec le fichier de contraintes -- Récupération des leds pour STD_OUT -- Récupération des switchs pour STD_IN -- Récupération d'un bouton pour RST -- Récupération de la clock entity System is Port ( led : out STD_LOGIC_VECTOR (7 downto 0); sw : in STD_LOGIC_VECTOR (7 downto 0); btnC : in STD_LOGIC; CLK : STD_LOGIC); end System; architecture Structural of System is component Pipeline is Generic (Nb_bits : Natural := 8; Instruction_En_Memoire_Size : Natural := 29; Addr_Memoire_Instruction_Size : Natural := 3; Memoire_Instruction_Size : Natural := 8; Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; Addr_registres_size : Natural := 4; Memoire_Size : Natural := 32; Adresse_mem_size : Natural := 5; Memoire_Adresses_Retour_Size : Natural := 16; Adresse_Memoire_Adresses_Retour_Size : Natural := 4); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; component Pipeline_NS is Generic (Nb_bits : Natural := 8; Instruction_En_Memoire_Size : Natural := 29; Addr_Memoire_Instruction_Size : Natural := 3; Memoire_Instruction_Size : Natural := 8; Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; Memoire_Size : Natural := 32); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; component Clock_Divider is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end component; -- signaux auxiliaires signal my_RST : STD_LOGIC; signal my_CLK : STD_LOGIC; constant SECURISED : boolean := true; begin -- Diviseur de clock clk_div : Clock_Divider port map (CLK_IN => CLK, CLK_OUT => my_CLK); -- Generation du processeur en fonction de la condition sécurisé ou non instance: if (SECURISED) generate instance_securisee : entity work.Pipeline generic map (Addr_Memoire_Instruction_Size => 8, Memoire_Instruction_Size => 256) port map (CLK => my_CLK, RST => my_RST, STD_IN => sw, STD_OUT => led); else generate instance_non_securisee : entity work.Pipeline_NS generic map (Addr_Memoire_Instruction_Size => 8, Memoire_Instruction_Size => 256) port map (CLK => my_CLK, RST => my_RST, STD_IN => sw, STD_OUT => led); end generate; -- Gestion du RST (inversion d'état) my_RST <= '1' when btnC = '0' else '0'; end Structural;