61 lines
1.3 KiB
VHDL
61 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 28.06.2021 14:59:39
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-- Design Name:
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-- Module Name: Compteur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Compteur is
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Generic (Min : Natural;
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Max : Natural
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);
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Port (CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Value : out Natural;
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Carry : out STD_LOGIC);
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end Compteur;
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architecture Behavioral of Compteur is
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signal current : Natural := Min;
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signal InternCarry : STD_LOGIC := '0';
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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current <= Min;
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else
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current <= current + 1;
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if (current = Max) then
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InternCarry <= '1';
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current <= Min;
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else
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InternCarry <= '0';
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end if;
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end if;
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end process;
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Value <= current;
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Carry <= InternCarry;
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end Behavioral;
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