108 行
3.1 KiB
VHDL
108 行
3.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 28.06.2021 15:55:57
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-- Design Name:
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-- Module Name: Test_VGAControler - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Test_VGAControler is
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-- Port ( );
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end Test_VGAControler;
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architecture Behavioral of Test_VGAControler is
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component VGAControler is
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Generic ( HEIGHT : Natural;
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WIDTH : Natural;
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X_PulseWidth : Natural;
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X_FrontPorch : Natural;
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X_BackPorch : Natural;
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Y_PulseWidth : Natural;
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Y_FrontPorch : Natural;
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Y_BackPorch : Natural
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);
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Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_HS : out STD_LOGIC;
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VGA_VS : out STD_LOGIC;
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X : out Natural;
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Y : out Natural;
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PIXEL_ON : in STD_LOGIC;
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC);
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end component;
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signal my_VGA_RED : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_VGA_BLUE : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_VGA_GREEN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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signal my_VGA_HS : STD_LOGIC := '0';
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signal my_VGA_VS : STD_LOGIC := '0';
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signal my_X : Natural := 0;
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signal my_Y : Natural := 0;
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signal my_PIXEL_ON : STD_LOGIC := '0';
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signal my_CLK : STD_LOGIC := '0';
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signal my_RST : STD_LOGIC := '1';
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constant CLK_period : time := 10 ns;
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begin
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instance : VGAControler
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generic map( HEIGHT => 4,
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WIDTH =>10,
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X_PulseWidth => 2,
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X_FrontPorch => 1,
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X_BackPorch => 3,
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Y_PulseWidth => 1,
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Y_FrontPorch => 1,
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Y_BackPorch => 1)
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port map( VGA_RED => my_VGA_RED,
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VGA_BLUE => my_VGA_BLUE,
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VGA_GREEN => my_VGA_GREEN,
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VGA_HS => my_VGA_HS,
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VGA_VS => my_VGA_VS,
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X => my_X,
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Y => my_Y,
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PIXEL_ON => my_PIXEL_ON,
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CLK => my_CLK,
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RST => my_RST);
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CLK_process : process
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begin
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my_CLK <= '0';
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wait for CLK_period/2;
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my_CLK <= '1';
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wait for CLK_period/2;
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end process;
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process
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begin
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my_PIXEL_ON <= '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns;
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wait;
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end process;
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end Behavioral;
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