63 lines
No EOL
1.4 KiB
VHDL
63 lines
No EOL
1.4 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 29.06.2021 16:16:32
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-- Design Name:
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-- Module Name: TestTableASCII - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.font.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity TestTableASCII is
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-- Port ( );
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end TestTableASCII;
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architecture Behavioral of TestTableASCII is
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component TableASCII is
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port ( CodeASCII : in Natural;
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Font : out font_T);
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end component;
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signal my_CodeASCII : Natural := 0;
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signal my_Font : font_T := (others => (others => '0'));
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begin
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instance : TableASCII
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port map( CodeASCII => my_CodeASCII,
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Font => my_Font
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);
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process
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begin
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my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
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wait;
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end process;
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end Behavioral; |