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Implémentation demo

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Paul Faure 2021-05-27 12:24:35 +02:00
parent 805b597ab6
commit df3b1ecdac
2 changed files with 4 additions and 5 deletions
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3
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
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4
Processeur.srcs/sources_1/new/System.vhd
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@ -75,8 +75,8 @@ begin
CLK_OUT => my_CLK); CLK_OUT => my_CLK);
instance : Pipeline instance : Pipeline
generic map (Addr_Memoire_Instruction_Size => 7, generic map (Addr_Memoire_Instruction_Size => 8,
Memoire_Instruction_Size => 128) Memoire_Instruction_Size => 256)
port map (CLK => my_CLK, port map (CLK => my_CLK,
RST => my_RST, RST => my_RST,
STD_IN => sw, STD_IN => sw,