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Preparation merge

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This commit is contained in:
Paul Faure 2021-06-24 13:18:28 +02:00
parent f25ee2735a
commit cd30c90fc7
6 changed files with 35 additions and 34 deletions
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8
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd → Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd
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@ -3,7 +3,7 @@
-- Engineer: Paul Faure -- Engineer: Paul Faure
-- --
-- Create Date: 18.04.2021 21:19:41 -- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage1_LectureInstruction - Behavioral -- Module Name: Etage1_LectureInstruction_NS - Behavioral
-- Project Name: Processeur sécurisé -- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7 -- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4 -- Tool Versions: Vivado 2016.4
@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
entity Etage1_LectureInstruction is entity Etage1_LectureInstruction_NS is
Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire) Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées) Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
@ -61,11 +61,11 @@ entity Etage1_LectureInstruction is
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
end Etage1_LectureInstruction; end Etage1_LectureInstruction_NS;
architecture Behavioral of Etage1_LectureInstruction is architecture Behavioral of Etage1_LectureInstruction_NS is
component MemoireInstructions is component MemoireInstructions is
Generic (Nb_bits : Natural; Generic (Nb_bits : Natural;
Addr_size : Natural; Addr_size : Natural;

10
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd → Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd
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@ -3,7 +3,7 @@
-- Engineer: Paul Faure -- Engineer: Paul Faure
-- --
-- Create Date: 18.04.2021 21:19:41 -- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage4_Memoire - Structural -- Module Name: Etage4_Memoire_NS - Structural
-- Project Name: Processeur sécurisé -- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7 -- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4 -- Tool Versions: Vivado 2016.4
@ -24,7 +24,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Etage4_Memoire is entity Etage4_Memoire_NS is
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables) Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
@ -44,9 +44,9 @@ entity Etage4_Memoire is
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1 OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
end Etage4_Memoire; end Etage4_Memoire_NS;
architecture Structural of Etage4_Memoire is architecture Structural of Etage4_Memoire_NS is
component MemoireDonnees is component MemoireDonnees is
Generic (Nb_bits : Natural; Generic (Nb_bits : Natural;
Addr_size : Natural; Addr_size : Natural;
@ -186,4 +186,4 @@ begin
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP; Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
end Structural; end Structural;

2
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
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File diff suppressed because one or more lines are too long

17
Processeur.srcs/sources_1/new/Pipeline.vhd → Processeur.srcs/sources_1/new/Pipeline_NS.vhd
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@ -4,7 +4,7 @@
-- --
-- Create Date: 19.04.2021 16:57:41 -- Create Date: 19.04.2021 16:57:41
-- Design Name: -- Design Name:
-- Module Name: Pipeline - Behavioral -- Module Name: Pipeline_NS - Behavioral
-- Project Name: -- Project Name:
-- Target Devices: -- Target Devices:
-- Tool Versions: -- Tool Versions:
@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity Pipeline is entity Pipeline_NS is
Generic (Nb_bits : Natural := 8; Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29; Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3; Addr_Memoire_Instruction_Size : Natural := 3;
@ -46,11 +46,11 @@ entity Pipeline is
RST : STD_LOGIC; RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end Pipeline; end Pipeline_NS;
architecture Behavioral of Pipeline is architecture Behavioral of Pipeline_NS is
component Etage1_LectureInstruction is component Etage1_LectureInstruction_NS is
Generic (Instruction_size_in_memory : Natural; Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural; Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural; Mem_instruction_size : Natural;
@ -122,7 +122,7 @@ architecture Behavioral of Pipeline is
C : out STD_LOGIC); C : out STD_LOGIC);
end component; end component;
component Etage4_Memoire is component Etage4_Memoire_NS is
Generic ( Nb_bits : Natural; Generic ( Nb_bits : Natural;
Mem_size : Natural; Mem_size : Natural;
Adresse_mem_size : Natural; Adresse_mem_size : Natural;
@ -200,7 +200,7 @@ architecture Behavioral of Pipeline is
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110"; constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
begin begin
instance_Etage1 : Etage1_LectureInstruction instance_Etage1 : Etage1_LectureInstruction_NS
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size, generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
Addr_size_mem_instruction => Addr_Memoire_Instruction_Size, Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
Mem_instruction_size => Memoire_Instruction_Size, Mem_instruction_size => Memoire_Instruction_Size,
@ -276,7 +276,7 @@ begin
C => C C => C
); );
instance_Etage4 : Etage4_Memoire instance_Etage4 : Etage4_Memoire_NS
generic map( Nb_bits => Nb_bits, generic map( Nb_bits => Nb_bits,
Mem_size => Memoire_Size, Mem_size => Memoire_Size,
Adresse_mem_size => Adresse_mem_size, Adresse_mem_size => Adresse_mem_size,
@ -321,3 +321,4 @@ begin
Instruction_to_5 <= Instruction_from_4; Instruction_to_5 <= Instruction_from_4;
end process; end process;
end Behavioral; end Behavioral;

4
Processeur.srcs/sources_1/new/System.vhd
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@ -31,7 +31,7 @@ entity System is
end System; end System;
architecture Structural of System is architecture Structural of System is
component Pipeline is component Pipeline_NS is
Generic (Nb_bits : Natural := 8; Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29; Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3; Addr_Memoire_Instruction_Size : Natural := 3;
@ -62,7 +62,7 @@ begin
CLK_OUT => my_CLK); CLK_OUT => my_CLK);
-- Le processeur, augmentation de la taille de la mémoire d'instruction -- Le processeur, augmentation de la taille de la mémoire d'instruction
instance : Pipeline instance : Pipeline_NS
generic map (Addr_Memoire_Instruction_Size => 8, generic map (Addr_Memoire_Instruction_Size => 8,
Memoire_Instruction_Size => 256) Memoire_Instruction_Size => 256)
port map (CLK => my_CLK, port map (CLK => my_CLK,

28
Processeur.xpr
View file

@ -103,37 +103,37 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd"> <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>