Ajout module ecran et clavier au processeur (TAF : version non sécu, Tester)

Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc

@@ -108,8 +108,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
 
 
 ##Buttons
-#set_property PACKAGE_PIN U18 [get_ports btnC]
-#	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+set_property PACKAGE_PIN U18 [get_ports btnC]
+	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
 ##set_property PACKAGE_PIN T18 [get_ports btnU]
 #	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
 #set_property PACKAGE_PIN W19 [get_ports btnL]

Processeur.srcs/sim_1/new/TestScreenDriver.vhd

@@ -0,0 +1,87 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.07.2021 11:39:21
+-- Design Name: 
+-- Module Name: TestScreenDriver - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TestScreenDriver is
+--  Port ( );
+end TestScreenDriver;
+
+architecture Behavioral of TestScreenDriver is 
+
+    component ScreenDriver
+    Generic ( Nb_bits : Natural
+            );
+    Port ( CLK       : in STD_LOGIC;
+           Value     : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           ValueAv   : in STD_LOGIC;
+           IsInt     : in STD_LOGIC;
+           OutData   : out STD_LOGIC_VECTOR (0 to 6);
+           OutDataAv : out STD_LOGIC);
+    end component;
+    
+   signal CLK       : STD_LOGIC := '0';
+   signal Value     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
+   signal ValueAv   : STD_LOGIC := '0';
+   signal IsInt     : STD_LOGIC := '0';
+   signal OutData   : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
+   signal OutDataAv : STD_LOGIC := '0';
+   
+   constant CLK_period : time := 10 ns;
+
+begin
+
+    instance : ScreenDriver
+    Generic map ( Nb_bits => 16)
+    Port map ( CLK       => CLK       ,
+               Value     => Value     ,
+               ValueAv   => ValueAv   ,
+               IsInt     => IsInt     ,
+               OutData   => OutData   ,
+               OutDataAv => OutDataAv );
+    
+    CLK_process : process
+    begin
+        CLK <= '1';
+        wait for CLK_period/2;
+        CLK <= '0';
+        wait for CLK_period/2;
+    end process;
+    
+    process
+    begin
+        Value   <= "0000000001010101" after 10 ns, "11111111111111111" after 80 ns;
+        ValueAv <= '1' after 10 ns, '0' after 30 ns,                  '1' after 80 ns, '0' after 90 ns;
+        IsInt   <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
+        wait;
+    end process;
+
+end Behavioral;

Processeur.srcs/sim_1/new/TestSystem.vhd

@@ -0,0 +1,90 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 12.07.2021 08:34:17
+-- Design Name: 
+-- Module Name: TestSystem - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TestSystem is
+--  Port ( );
+end TestSystem;
+
+architecture Behavioral of TestSystem is
+
+    component System is
+    Port ( vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
+           btnC : in STD_LOGIC;
+           CLK : STD_LOGIC);
+    end component;
+    
+    signal CLK : STD_LOGIC := '0';
+    signal btnC : STD_LOGIC := '0';
+    signal PS2Clk : STD_LOGIC := '0';
+    signal PS2Data : STD_LOGIC := '0';
+    signal vgaRed   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
+    signal vgaBlue  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
+    signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
+    signal Hsync    : STD_LOGIC := '0';
+    signal Vsync    : STD_LOGIC := '0';
+    
+    constant CLK_period : time := 10 ns;
+    
+begin
+    instance : System
+    port map (vgaRed   => vgaRed,
+              vgaBlue  => vgaBlue,
+              vgaGreen => vgaGreen,
+              Hsync    => Hsync,
+              Vsync    => Vsync,
+              PS2Clk => PS2Clk,
+              PS2Data => PS2Data,
+              btnC => btnC,
+              CLK  => CLK);
+              
+    CLK_process :process
+    begin
+        CLK <= '1';
+        wait for CLK_period/2;
+        CLK <= '0';
+        wait for CLK_period/2;
+    end process;
+    
+    process 
+    begin
+        PS2Clk <= '1' after 3200 us, '0' after 3250 us, '1' after 3300 us, '0' after 3350 us, '1' after 3400 us, '0' after 3450 us, '1' after 3500 us, '0' after 3550 us, '1' after 3600 us, '0' after 3650 us, '1' after 3700 us, '0' after 3750 us, '1' after 3800 us, '0' after 3850 us, '1' after 3900 us, '0' after 3950 us, '1' after 4000 us, '0' after 4050 us, '1' after 4100 us, '0' after 4150 us, '1' after 4200 us, '0' after 4250 us, '1' after 5000 us, '0' after 5050 us, '1' after 5100 us, '0' after 5150 us, '1' after 5200 us, '0' after 5250 us, '1' after 5300 us, '0' after 5350 us, '1' after 5400 us, '0' after 5450 us, '1' after 5500 us, '0' after 5550 us, '1' after 5600 us, '0' after 5650 us, '1' after 5700 us, '0' after 5750 us, '1' after 5800 us, '0' after 5850 us, '1' after 5900 us, '0' after 5950 us, '1' after 6000 us, '0' after 6050 us;
+        PS2Data <= '0' after 3200 us, '1' after 3300 us, '0' after 3400 us, '1' after 3500 us, '0' after 3600 us, '1' after 3700 us, '1' after 3800 us, '1' after 3900 us, '0' after 4000 us, '0' after 4100 us, '1' after 4200 us, '0' after 4300 us, '0' after 5000 us, '0' after 5100 us, '1' after 5200 us, '0' after 5300 us, '1' after 5400 us, '1' after 5500 us, '0' after 5600 us, '1' after 5700 us, '0' after 5800 us, '1' after 5900 us, '1' after 6000 us, '0' after 6100 us;
+        wait;
+    end process;
+end Behavioral;

Processeur.srcs/sources_1/new/Ecran.vhd

@@ -46,7 +46,7 @@ architecture Behavioral of Ecran is
     end component;
 
     constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000";
-    constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001101";
+    constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001010";
     constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111";
     
     signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); --(0 => '1', 1 => '0', 2 => '0', 3 => '1', 4 => '0', 5 => '0', 6 => '0', others => '0');
@@ -125,7 +125,7 @@ begin
     point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht)));
     point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)));
     
-    CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y/Display_CaracterHeight < L_Blocks and X/Display_CaracterWidht < C_Blocks and RST='1') else
+    CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y < screen_height and X < screen_width and RST='1') else
                         "0000000";
 
     OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width));

Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd

@@ -50,14 +50,17 @@
                  --                Instructions_critiques_lecture_C(5) = '0'  --> AFC ne lit pas dans le registre de l'opérande C
                  --                Instructions_critiques_ecriture(5) = '1'  --> AFC ecrit dans le registre de l'opérande A
                  
-                 Code_Instruction_JMP : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMP
-                 Code_Instruction_JMZ : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMZ
-                 Code_Instruction_CALL : STD_LOGIC_VECTOR;  -- Numéro de l'instruction CALL
-                 Code_Instruction_RET : STD_LOGIC_VECTOR;   -- Numéro de l'instruction RET
-                 Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP
+                 Code_Instruction_JMP  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMP
+                 Code_Instruction_JMZ  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMZ
+                 Code_Instruction_PRI  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction PRI
+                 Code_Instruction_PRIC : STD_LOGIC_VECTOR;   -- Numéro de l'instruction PRIC
+                 Code_Instruction_CALL : STD_LOGIC_VECTOR;   -- Numéro de l'instruction CALL
+                 Code_Instruction_RET  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction RET
+                 Code_Instruction_STOP : STD_LOGIC_VECTOR);  -- Numéro de l'instruction STOP
         Port ( CLK : in STD_LOGIC; -- Clock
                RST : in STD_LOGIC; -- Reset
                Z : in STD_LOGIC;   -- Flag Zero de l'ALU (utile pour le JMZ)
+               STD_IN_Request : in STD_LOGIC;
                A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
                B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
                C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
@@ -117,6 +120,9 @@
         -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k
         signal compteur : integer := 0;
         
+        -- Compteur de protection des collisions entre les prints
+        signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0;
+        
         -- Signal d'arret (STOP 0)
         signal locked : boolean := false;
         
@@ -153,16 +159,20 @@
                 Tableau <= (others => -1);
                 Pointeur_Instruction <= (others => '0');
                 compteur <= 0;
+                Compteur_PRI <= 0;
                 locked <= false;
                 C <= Argument_nul;
                 B <= Argument_nul;
                 A <= Argument_nul;
                 Instruction <= Instruction_nulle;
-            else
+            elsif (STD_IN_Request = '0') then
                 -- Avancement des instructions en écritures dans le pipeline
                 Tableau(3) <= Tableau(2);
                 Tableau(2) <= Tableau(1);
                 Tableau(1) <= -1;
+                if (Compteur_PRI > 0) then
+                    Compteur_PRI <= Compteur_PRI - 1;
+                end if;
                 if (not bulles) then
                     -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
                     if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
@@ -212,6 +222,14 @@
                         B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
                         A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
                         Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
+                    elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then
+                        -- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions
+                        Compteur_PRI <= Nb_bits/4 + 1;
+                        C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
+                        B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
+                        A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
+                        Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
+                        Pointeur_Instruction <= Pointeur_Instruction + 1;
                     else
                         -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau
                         C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
@@ -276,12 +294,24 @@
                 or 
                 (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
             )
+        )
+        or
+        (
+            (
+                (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI)
+                or
+                (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC)
+            )
+            and
+            (
+                not (Compteur_PRI = 0)
+            )
         );
         
         -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
-        R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
+        R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET and STD_IN_Request = '0' else
                  '0';
-        W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
+        W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL and STD_IN_Request = '0' else
                  '0';
                  
                  

Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd

@@ -29,12 +29,17 @@ entity Etage2_5_Registres is
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
               Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
               Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
-              Code_Instruction_PRI : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
-              Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
+              Code_Instruction_PRI  : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
+              Code_Instruction_PRIC : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRIC
+              Code_Instruction_GET  : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
     Port ( CLK : in STD_LOGIC; -- Clock
            RST : in STD_LOGIC; -- Reset
            STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
+           STD_IN_Av : in STD_LOGIC;
+           STD_IN_Request : out STD_LOGIC;
            STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
+           STD_OUT_Av : out STD_LOGIC;
+           STD_OUT_Int : out STD_LOGIC;
            IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
            IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
            IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
@@ -95,7 +100,7 @@ architecture Behavioral of Etage2_5_Registres is
     signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
     signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
     signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
-    signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
+    
     
 begin
     instance_LC : LC
@@ -147,22 +152,19 @@ begin
                intern_OUT_2_C;
     OUT_2_Instruction <= (others => '0') when RST = '0' else
                          IN_2_Instruction;    
-     
-    -- Gestion de STD_OU (peut être améliorée) 
-    process 
-    begin
-        -- Synchronisation sur la clock
-        wait until CLK'event and CLK = '1';
-        if (RST = '0') then
-            intern_STD_OUT <= (others => '0');
-        else
-            if (IN_2_Instruction = Code_Instruction_PRI) then
-                intern_STD_OUT <= intern_OUT_2_A;
-            end if;
-        end if;
-    end process;
-    STD_OUT <= intern_STD_OUT when RST = '1' else
-               (others => '0');
+    
+    STD_OUT     <= (others => '0') when RST = '0' else
+                   intern_OUT_2_A;
+    STD_OUT_Av  <= '0' when RST = '0' else
+                   '1' when IN_2_Instruction = Code_Instruction_PRI or IN_2_Instruction = Code_Instruction_PRIC else
+                   '0';
+    STD_OUT_Int <= '0' when RST = '0' else
+                   '1' when IN_2_Instruction = Code_Instruction_PRI else
+                   '0';
+                   
+    STD_IN_Request <= '0' when RST = '0' else
+                      '1' when IN_5_Instruction = Code_Instruction_GET and STD_IN_Av = '0' else
+                      '0';
     
     
     

Processeur.srcs/sources_1/new/Etage4_Memoire.vhd

@@ -49,15 +49,21 @@
 
     architecture Structural of Etage4_Memoire is
         component MemoireDonnees is
-        Generic (Nb_bits : Natural;
-                 Addr_size : Natural;
-                 Mem_size : Natural);
-        Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
-               RW : in STD_LOGIC;
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
-               RST : in STD_LOGIC;
-               CLK : in STD_LOGIC;
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
+        Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire 
+                 Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire
+                 Mem_size : Natural); -- Nombre de mot stockables
+        Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
+               RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
+               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
+               CALL : in STD_LOGIC; -- '1' -> CALL en cours
+               IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
+               IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
+               RET : in STD_LOGIC; -- '1' -> RET en cours
+               OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
+               OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
+               RST : in STD_LOGIC; -- Reset
+               CLK : in STD_LOGIC; -- Clock
+               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire 
         end component;
         
         component MemoireAdressesRetour is
@@ -112,6 +118,10 @@
         signal E : STD_LOGIC;
         signal F : STD_LOGIC;
         
+        -- Signaux inutiles
+        signal OUT_EBP : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
+        signal OUT_AddrRet : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
+        
         
     begin
         instance_LC : LC -- Link controleur sur la mémoire de donnees
@@ -155,6 +165,12 @@
         port map ( Addr => Addr_MemoireDonnees,
                    RW => Commande_MemoireDonnees(0),
                    D_IN => IN_B,
+                   CALL => '0',
+                   IN_EBP => (others => '0'),
+                   IN_AddrRet => (others => '0'),
+                   RET => '0',
+                   OUT_EBP => OUT_EBP,
+                   OUT_AddrRet => OUT_AddrRet,
                    RST => RST,
                    CLK => CLK,
                    D_OUT => Sortie_MemoireDonnees);

Processeur.srcs/sources_1/new/KeyboardDriver.vhd

@@ -0,0 +1,86 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 13.07.2021 09:30:08
+-- Design Name: 
+-- Module Name: KeyboardDriver - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity KeyboardDriver is
+    Generic (Nb_Bits : Natural);
+    Port (CLK : in STD_LOGIC;
+          Data_read : out STD_LOGIC;
+          Data_av : in STD_LOGIC;
+          Data : in STD_LOGIC_VECTOR (0 to 6);
+          STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+          STD_IN_Av : out STD_LOGIC;
+          STD_IN_Request : in STD_LOGIC;
+          STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+          STD_OUT_Av : out STD_LOGIC);
+end KeyboardDriver;
+
+architecture Behavioral of KeyboardDriver is
+
+    signal intern_value : Natural := 0;
+    signal work_in_progress : BOOLEAN := false;
+    signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0');
+    
+
+begin
+
+    process
+    begin
+        wait until CLK'event and CLK = '1';
+        STD_IN_Av <= '0';        
+        STD_OUT_Av <= '0';
+        if not(work_in_progress) then
+            intern_value <= 0;
+        end if;
+        if STD_IN_Request = '1' then  
+            work_in_progress <= true;
+            if Data_av = '1' then
+                STD_OUT <= Zeros & Data;
+                STD_OUT_Av <= '1';
+                if (Data = "1111111") then
+                    intern_value <= intern_value / 10;
+                elsif (Data = "0001101") then
+                    STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits));
+                    STD_IN_Av <= '1';
+                    work_in_progress <= false;
+                elsif (Data >= "0110000" and Data <= "0111001") then
+                    intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6)));
+                end if;
+            end if;
+        end if; 
+    end process;
+    
+    Data_read <= '0' when STD_IN_Request = '0' else Data_av;
+
+end Behavioral;

Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd

@@ -0,0 +1,107 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 13.07.2021 09:30:08
+-- Design Name: 
+-- Module Name: PeripheriqueClavier - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PeripheriqueClavier is
+    Generic (Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
+           STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_IN_Av : out STD_LOGIC;
+           STD_IN_Request : in STD_LOGIC;
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : out STD_LOGIC);
+end PeripheriqueClavier;
+
+architecture Behavioral of PeripheriqueClavier is
+
+    component KeyboardDriver
+        Generic (Nb_Bits : Natural);
+        Port (CLK : in STD_LOGIC;
+              Data_read : out STD_LOGIC;
+              Data_av : in STD_LOGIC;
+              Data : in STD_LOGIC_VECTOR (0 to 6);
+              STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+              STD_IN_Av : out STD_LOGIC;
+              STD_IN_Request : in STD_LOGIC;
+              STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+              STD_OUT_Av : out STD_LOGIC);
+    end component;
+    
+    component Keyboard 
+        Port (CLK : in STD_LOGIC;
+      
+              PS2Clk : in STD_LOGIC;
+              PS2Data : in STD_LOGIC;
+            
+              Data_read : in STD_LOGIC;
+              Data_av : out STD_LOGIC;
+              Data : out STD_LOGIC_VECTOR (0 to 6);
+            
+              alert : out STD_LOGIC);
+    end component;
+    
+    signal Data_read : STD_LOGIC := '0';
+    signal Data_av : STD_LOGIC := '0';
+    signal Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
+    
+    signal nothing : STD_LOGIC := '0';
+
+begin
+    
+    instance_Keyboard : Keyboard 
+    port map (CLK => CLK,
+  
+              PS2Clk => PS2Clk,
+              PS2Data => PS2Data,
+            
+              Data_read => Data_read,
+              Data_av => Data_av,
+              Data => Data,
+            
+              alert => nothing);
+              
+    instance_KeyboardDriver : KeyboardDriver
+    generic map (Nb_Bits => Nb_Bits)
+    port map (CLK => CLK,
+              Data_read => Data_read,
+              Data_av => Data_av,
+              Data => Data,
+              STD_IN => STD_IN,
+              STD_IN_Av => STD_IN_Av,
+              STD_IN_Request => STD_IN_Request,
+              STD_OUT => STD_OUT,
+              STD_OUT_Av => STD_OUT_Av);
+
+end Behavioral;

Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd

@@ -0,0 +1,150 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.07.2021 15:25:56
+-- Design Name: 
+-- Module Name: PeripheriqueEcran - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ScreenProperties.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PeripheriqueEcran is
+    Generic ( Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           CLK_VGA : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           
+           vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+                     
+           STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : in STD_LOGIC;
+           STD_OUT_Int : in STD_LOGIC);
+end PeripheriqueEcran;
+
+architecture Behavioral of PeripheriqueEcran is
+
+component VGAControler is
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
+               VGA_HS    : out STD_LOGIC;
+               VGA_VS    : out STD_LOGIC;
+               
+               X         : out X_T;
+               Y         : out Y_T;
+               PIXEL_ON  : in STD_LOGIC;
+               
+               CLK       : in STD_LOGIC;
+               RST       : in STD_LOGIC);
+    end component; 
+    
+    component clk_wiz_0
+    port
+     (-- Clock in ports
+      clk_in1           : in     std_logic;
+      -- Clock out ports
+      clk_out1          : out    std_logic
+     );
+    end component;
+    
+    component Ecran is
+        Port (     CLK            : in STD_LOGIC;
+                   RST            : in STD_LOGIC;
+                   Data_Av        : in STD_LOGIC;
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
+                   X              : in X_T;
+                   Y              : in Y_T;
+                   OUT_ON         : out STD_LOGIC);
+    end component;
+    
+    component ScreenDriver 
+        Generic ( Nb_bits : Natural
+                );
+        Port ( CLK : in STD_LOGIC;
+               Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+               ValueAv : in STD_LOGIC;
+               IsInt : in STD_LOGIC;
+               OutData : out STD_LOGIC_VECTOR (0 to 6);
+               OutDataAv : out STD_LOGIC);
+    end component;
+    
+    signal my_X : X_T := 0;
+    signal my_Y : Y_T := 0;
+    signal my_PIXEL_ON : STD_LOGIC := '0';
+    signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
+    signal OutDataAv : STD_LOGIC := '0';    
+    signal my_CLK : STD_LOGIC := '0';
+
+begin
+
+    instanceVGA : VGAControler 
+    port map(  VGA_RED   => vgaRed,
+               VGA_BLUE  => vgaBlue,
+               VGA_GREEN => vgaGreen,
+               VGA_HS    => Hsync,
+               VGA_VS    => Vsync,
+                 
+               X         => my_X,
+               Y         => my_Y,
+               PIXEL_ON  => my_PIXEL_ON,
+                 
+               CLK       => my_CLK,
+               RST       => RST);
+               
+    
+    clk_wiz_0_inst : clk_wiz_0
+    port map (
+              clk_in1 => CLK_VGA,
+              clk_out1 => my_CLK
+             );
+    
+    
+    instance_Ecran : Ecran
+    port map (     CLK     => CLK,
+                   RST     => RST,
+                   Data_Av => OutDataAv,
+                   Data_IN => OutData,
+                   X => my_X,
+                   Y => my_Y,
+                   OUT_ON => my_PIXEL_ON);
+                   
+    instance_ScreenDriver : ScreenDriver 
+    Generic map ( Nb_bits => Nb_Bits
+                )
+    Port map ( CLK => CLK,
+               Value => STD_OUT,
+               ValueAv => STD_OUT_Av,
+               IsInt => STD_OUT_Int,
+               OutData => OutData,
+               OutDataAv => OutDataAv);
+
+end Behavioral;

Processeur.srcs/sources_1/new/Pipeline.vhd

@@ -44,10 +44,14 @@ entity Pipeline is
              Adresse_mem_size : Natural := 5;
              Memoire_Adresses_Retour_Size : Natural := 16;
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
-    Port (CLK : STD_LOGIC;
-          RST : STD_LOGIC;
-          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
+    Port (CLK : in STD_LOGIC;
+          RST : in STD_LOGIC;
+          STD_IN      : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_IN_Av   : in STD_LOGIC;
+          STD_IN_Request  : out STD_LOGIC;
+          STD_OUT     : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_OUT_Av  : out STD_LOGIC;
+          STD_OUT_Int : out STD_LOGIC);
 end Pipeline;
 
 architecture Behavioral of Pipeline is
@@ -67,12 +71,15 @@ architecture Behavioral of Pipeline is
              Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
              Code_Instruction_JMP : STD_LOGIC_VECTOR;
              Code_Instruction_JMZ : STD_LOGIC_VECTOR;
+             Code_Instruction_PRI  : STD_LOGIC_VECTOR;   
+             Code_Instruction_PRIC : STD_LOGIC_VECTOR;   
              Code_Instruction_CALL : STD_LOGIC_VECTOR;
              Code_Instruction_RET : STD_LOGIC_VECTOR;
              Code_Instruction_STOP : STD_LOGIC_VECTOR);
     Port ( CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            Z : in STD_LOGIC;
+           STD_IN_Request : in STD_LOGIC;
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -80,30 +87,35 @@ architecture Behavioral of Pipeline is
     end component;
     
     component Etage2_5_Registres is
-    Generic ( Nb_bits : Natural;
-              Nb_registres : Natural;
-              Addr_registres_size : Natural;
-              Instruction_bus_size : Natural;
-              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
-              Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
-              Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
-              Code_Instruction_PRI : STD_LOGIC_VECTOR;
-              Code_Instruction_GET : STD_LOGIC_VECTOR);
-    Port ( CLK : in STD_LOGIC;
-           RST : in STD_LOGIC;
-           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
-           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
-           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
+        Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
+                  Nb_registres : Natural; -- Nombre de registres du processeurs
+                  Addr_registres_size : Natural; -- Nombre de bits pour adresser les registres
+                  Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
+                  Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
+                  Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
+                  Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
+                  Code_Instruction_PRI  : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
+                  Code_Instruction_PRIC : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRIC
+                  Code_Instruction_GET  : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
+        Port ( CLK : in STD_LOGIC; -- Clock
+               RST : in STD_LOGIC; -- Reset
+               STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
+               STD_IN_Av : in STD_LOGIC;
+               STD_IN_Request : out STD_LOGIC;
+               STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
+               STD_OUT_Av : out STD_LOGIC;
+               STD_OUT_Int : out STD_LOGIC;
+               IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
+               IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
+               IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
+               IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction de l'étage 2
+               OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A de l'étage 2
+               OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B de l'étage 2
+               OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C de l'étage 2
+               OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction de l'étage 2
+               IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 5
+               IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 5
+               IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Entrée de l'instruction de l'étage 5
     end component;
     
     component Etage3_Calcul is
@@ -181,27 +193,31 @@ architecture Behavioral of Pipeline is
     signal O : STD_LOGIC := '0';
     signal C : STD_LOGIC := '0';
     
-    constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
-    constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
+    signal intern_STD_IN_Request : STD_LOGIC := '0';
+    
+    
+    constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111";
+    constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001";
     constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
-    constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
-    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
-    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
-    constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
-    constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
+    constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001";
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111";
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111";
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111011001111111111";
+    constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000";
+    constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
     constant Code_Instruction_JMZ  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
     constant Code_Instruction_PRI  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
-    constant Code_Instruction_GET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
-    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
-    constant Code_Instruction_RET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
-    constant Code_Instruction_STOP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
+    constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; -------- TO BE DONE 
+    constant Code_Instruction_GET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
+    constant Code_Instruction_RET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
+    constant Code_Instruction_STOP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110";
     
-    constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
-    constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
-    constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
-    constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
+    constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000";
+    constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110";
+    constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110";
+    constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
 begin
     instance_Etage1 : Etage1_LectureInstruction
     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
@@ -218,6 +234,8 @@ begin
                  Instructions_critiques_ecriture => Instructions_critiques_ecriture,
                  Code_Instruction_JMP => Code_Instruction_JMP,
                  Code_Instruction_JMZ => Code_Instruction_JMZ,
+                 Code_Instruction_PRI  => Code_Instruction_PRI, 
+                 Code_Instruction_PRIC => Code_Instruction_PRIC,   
                  Code_Instruction_CALL => Code_Instruction_CALL,
                  Code_Instruction_RET => Code_Instruction_RET,
                  Code_Instruction_STOP => Code_Instruction_STOP
@@ -226,6 +244,7 @@ begin
         CLK => CLK,
         RST => RST,
         Z => Z,
+        STD_IN_Request => intern_STD_IN_Request,
         A => A_from_1,
         B => B_from_1,
         C => C_from_1,
@@ -241,12 +260,17 @@ begin
                  Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
                  Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
                  Code_Instruction_PRI => Code_Instruction_PRI,
+                 Code_Instruction_PRIC =>  Code_Instruction_PRIC,
                  Code_Instruction_GET => Code_Instruction_GET
     )
     port map(    CLK => CLK,
                  RST => RST,
-                 STD_IN => STD_IN,
-                 STD_OUT => STD_OUT,
+                 STD_IN      => STD_IN,
+                 STD_IN_Av   => STD_IN_Av,
+                 STD_IN_Request  => intern_STD_IN_Request,
+                 STD_OUT     => STD_OUT,
+                 STD_OUT_Av  => STD_OUT_Av,
+                 STD_OUT_Int => STD_OUT_Int,
                  IN_2_A => A_to_2,
                  IN_2_B => B_to_2,
                  IN_2_C => C_to_2,
@@ -303,26 +327,30 @@ begin
                  OUT_B => B_from_4,
                  OUT_Instruction => Instruction_from_4
     );
+    
+    STD_IN_Request <= intern_STD_IN_Request;
 
     process
     begin
         wait until CLK'event and CLK = '1';
-        A_to_2 <= A_from_1;
-        B_to_2 <= B_from_1;
-        C_to_2 <= C_from_1;
-        Instruction_to_2 <= Instruction_from_1;
-        
-        A_to_3 <= A_from_2;
-        B_to_3 <= B_from_2;
-        C_to_3 <= C_from_2;
-        Instruction_to_3 <= Instruction_from_2;
-
-        A_to_4 <= A_from_3;
-        B_to_4 <= B_from_3;
-        Instruction_to_4 <= Instruction_from_3;
-
-        A_to_5 <= A_from_4;
-        B_to_5 <= B_from_4;
-        Instruction_to_5 <= Instruction_from_4;
+        if (intern_STD_IN_Request = '0') then
+            A_to_2 <= A_from_1;
+            B_to_2 <= B_from_1;
+            C_to_2 <= C_from_1;
+            Instruction_to_2 <= Instruction_from_1;
+            
+            A_to_3 <= A_from_2;
+            B_to_3 <= B_from_2;
+            C_to_3 <= C_from_2;
+            Instruction_to_3 <= Instruction_from_2;
+    
+            A_to_4 <= A_from_3;
+            B_to_4 <= B_from_3;
+            Instruction_to_4 <= Instruction_from_3;
+    
+            A_to_5 <= A_from_4;
+            B_to_5 <= B_from_4;
+            Instruction_to_5 <= Instruction_from_4;
+        end if;
     end process;        
 end Behavioral;

Processeur.srcs/sources_1/new/ScreenDriver.vhd

@@ -0,0 +1,142 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.07.2021 09:54:12
+-- Design Name: 
+-- Module Name: ScreenDriver - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ScreenDriver is
+    Generic ( Nb_bits : Natural
+            );
+    Port ( CLK : in STD_LOGIC;
+           Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           ValueAv : in STD_LOGIC;
+           IsInt : in STD_LOGIC;
+           OutData : out STD_LOGIC_VECTOR (0 to 6);
+           OutDataAv : out STD_LOGIC);
+end ScreenDriver;
+
+architecture Behavioral of ScreenDriver is
+
+    signal intern_value : STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0) := (others => '0');
+    signal current_hexa : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
+    subtype compteur_T is Natural range 0 to Nb_bits/4 - 1;
+    signal compteur : compteur_T := 0; 
+    signal work_in_progess : BOOLEAN := false;    
+    signal x_to_send : BOOLEAN := false;    
+    signal first_detected : BOOLEAN := false;
+    
+
+begin
+
+    current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4);
+
+    process
+    begin
+        wait until CLK'event and CLK = '1';
+        if ValueAv = '1' then  
+            if IsInt = '0' then
+                OutData <= Value (6 downto 0);
+            else 
+                intern_value <= Value;
+                OutData <= "0110000";
+                x_to_send <= true;
+            end if;
+            OutDataAv <= '1';
+        elsif x_to_send then
+            OutData <= "1111000";
+            OutDataAv <= '1';
+            x_to_send <= false;
+            work_in_progess <= true;
+            first_detected <= false;
+        elsif work_in_progess then
+            case current_hexa is
+            when "0000" =>
+                if first_detected or compteur = Nb_bits/4 - 1 then
+                    OutData <= "0110000";
+                end if;
+            when "0001" =>
+                OutData <= "0110001";
+            when "0010" =>
+                OutData <= "0110010";
+            when "0011" =>
+                OutData <= "0110011";
+            when "0100" =>
+                OutData <= "0110100";
+            when "0101" =>
+                OutData <= "0110101";
+            when "0110" =>
+                OutData <= "0110110";
+            when "0111" =>
+                OutData <= "0110111";
+            when "1000" =>
+                OutData <= "0111000";
+            when "1001" =>
+                OutData <= "0111001";
+            when "1010" =>
+                OutData <= "1000001";
+            when "1011" =>
+                OutData <= "1000010";
+            when "1100" =>
+                OutData <= "1000011";
+            when "1101" =>
+                OutData <= "1000100";
+            when "1110" =>
+                OutData <= "1000101";
+            when "1111" =>
+                OutData <= "1000110";
+            when others => 
+                OutData <= "0000001";
+            end case;
+            
+            
+            if first_detected or not (current_hexa = "0000") or compteur = Nb_bits/4 - 1 then
+                OutDataAv <= '1';
+                first_detected <= true;
+            else 
+                OutDataAv <= '0';
+                first_detected <= false;
+            end if;
+            
+            if (compteur = Nb_bits/4 - 1) then
+                compteur <= 0;
+                work_in_progess <= false;    
+                x_to_send       <= false;    
+                first_detected  <= false;
+            else 
+                compteur <= compteur + 1;
+            end if;
+        else 
+            OutDataAv <= '0';
+        end if;
+    end process;
+
+end Behavioral;

Processeur.srcs/sources_1/new/System.vhd

@@ -24,8 +24,13 @@ use IEEE.STD_LOGIC_1164.ALL;
 --   Récupération d'un bouton pour RST
 --   Récupération de la clock
 entity System is
-    Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
-           sw : in STD_LOGIC_VECTOR (7 downto 0);
+    Port ( vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
            btnC : in STD_LOGIC;
            CLK : STD_LOGIC);
 end System;
@@ -45,10 +50,14 @@ architecture Structural of System is
              Adresse_mem_size : Natural := 5;
              Memoire_Adresses_Retour_Size : Natural := 16;
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
-    Port (CLK : STD_LOGIC;
-          RST : STD_LOGIC;
-          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
+    Port (CLK : in STD_LOGIC;
+          RST : in STD_LOGIC;
+          STD_IN          : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_IN_Av       : in STD_LOGIC;
+          STD_IN_Request  : out STD_LOGIC;
+          STD_OUT         : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_OUT_Av      : out STD_LOGIC;
+          STD_OUT_Int     : out STD_LOGIC);
     end component;
 
     component Pipeline_NS is
@@ -66,6 +75,36 @@ architecture Structural of System is
           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
     end component;
     
+    component PeripheriqueEcran 
+    Generic ( Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           CLK_VGA : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           
+           vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+                     
+           STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : in STD_LOGIC;
+           STD_OUT_Int : in STD_LOGIC);
+    end component;
+    
+    component PeripheriqueClavier 
+    Generic (Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
+           STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_IN_Av : out STD_LOGIC;
+           STD_IN_Request : in STD_LOGIC;
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : out STD_LOGIC);
+    end component;
+    
     component Clock_Divider is
         Port ( CLK_IN : in STD_LOGIC;
                CLK_OUT : out STD_LOGIC);
@@ -74,10 +113,22 @@ architecture Structural of System is
     -- signaux auxiliaires
     signal my_RST : STD_LOGIC;
     signal my_CLK : STD_LOGIC;
+    signal STD_IN      : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
+    signal STD_IN_Av   : STD_LOGIC := '0';
+    signal STD_IN_Request  : STD_LOGIC := '0';
+    signal intern_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
+    signal intern_STD_OUT_Av  : STD_LOGIC := '0';
+    signal intern_STD_OUT_Int : STD_LOGIC := '0';
+    signal pipeline_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
+    signal pipeline_STD_OUT_Av  : STD_LOGIC := '0';
+    signal pipeline_STD_OUT_Int : STD_LOGIC := '0';
+    signal clavier_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
+    signal clavier_STD_OUT_Av  : STD_LOGIC := '0';
+    signal clavier_STD_OUT_Int : STD_LOGIC := '0';
     
     constant SECURISED : boolean := true;
         
-begin     
+begin    
            
     -- Diviseur de clock
     clk_div : Clock_Divider
@@ -88,25 +139,73 @@ begin
     -- Generation du processeur en fonction de la condition sécurisé ou non       
     instance: if (SECURISED) generate
         instance_securisee : entity work.Pipeline
-            generic map (Addr_Memoire_Instruction_Size => 8,
-                         Memoire_Instruction_Size => 256)
+            generic map (Nb_bits => 16,
+                         Instruction_En_Memoire_Size => 53,
+                         Addr_Memoire_Instruction_Size => 9,
+                         Memoire_Instruction_Size => 512,
+                         Instruction_Bus_Size => 5,
+                         Nb_Instructions => 32,
+                         Nb_Registres => 16,
+                         Addr_registres_size => 4,
+                         Memoire_Size => 32,
+                         Adresse_mem_size => 5,
+                         Memoire_Adresses_Retour_Size => 4,
+                         Adresse_Memoire_Adresses_Retour_Size => 2)
             port map (CLK => my_CLK,
                       RST => my_RST,
-                      STD_IN => sw,
-                      STD_OUT => led);
+                      STD_IN      => STD_IN,
+                      STD_IN_Av   => STD_IN_Av,
+                      STD_IN_Request => STD_IN_Request,
+                      STD_OUT     => pipeline_STD_OUT,
+                      STD_OUT_Av  => pipeline_STD_OUT_Av,
+                      STD_OUT_Int => pipeline_STD_OUT_Int);
     else generate
         instance_non_securisee : entity work.Pipeline_NS
-            generic map (Addr_Memoire_Instruction_Size => 8,
-                         Memoire_Instruction_Size => 256)
+            generic map (Addr_Memoire_Instruction_Size => 9,
+                         Memoire_Instruction_Size => 512)
             port map (CLK => my_CLK,
                       RST => my_RST,
-                      STD_IN => sw,
-                      STD_OUT => led);
+                      STD_IN => STD_IN,
+                      STD_OUT => pipeline_STD_OUT);
     end generate;  
+    
+    instance_perif_ecran : PeripheriqueEcran 
+    generic map ( Nb_Bits => 16)
+    port map ( CLK => my_CLK,
+               CLK_VGA => CLK,
+               RST => my_RST,
+               
+               vgaRed   => vgaRed,
+               vgaBlue  => vgaBlue,
+               vgaGreen => vgaGreen,
+               Hsync    => Hsync,
+               Vsync    => Vsync,
+                         
+               STD_OUT =>     intern_STD_OUT,
+               STD_OUT_Av =>  intern_STD_OUT_Av,
+               STD_OUT_Int => intern_STD_OUT_Int);
+               
+    instance_perif_clavier : PeripheriqueClavier 
+    generic map (Nb_Bits => 16)
+    port map ( CLK => my_CLK,
+               RST => my_RST,
+               PS2Clk => PS2Clk,
+               PS2Data => PS2Data,
+               STD_IN => STD_IN,
+               STD_IN_Av => STD_IN_Av,
+               STD_IN_Request => STD_IN_Request,
+               STD_OUT =>    clavier_STD_OUT,
+               STD_OUT_Av => clavier_STD_OUT_Av);
           
               
     -- Gestion du RST (inversion d'état)
     my_RST <= '1' when btnC = '0' else
               '0';
+              
+    
+    intern_STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
+    intern_STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
+    intern_STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
+    
 end Structural;
 

Processeur.xpr

@@ -35,7 +35,7 @@
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="DSANumComputeUnits" Val="16"/>
-    <Option Name="WTXSimLaunchSim" Val="473"/>
+    <Option Name="WTXSimLaunchSim" Val="543"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -251,9 +251,39 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/IntToASCII.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ScreenDriver.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/PeripheriqueEcran.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/PeripheriqueClavier.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/KeyboardDriver.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="SystemKeyboardScreen"/>
+        <Option Name="TopModule" Val="System"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@@ -397,9 +427,26 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sim_1/new/TestScreenDriver.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/TestSystem.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="Test_SystemKeyboardScreen"/>
+        <Option Name="TopModule" Val="TestSystem"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -408,6 +455,7 @@
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg"/>
       </Config>
     </FileSet>
   </FileSets>

SimulationsConfig/TestSystem_behav.wcfg

@@ -0,0 +1,581 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="TestSystem_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="TestSystem" />
+            <top_module name="font" />
+            <top_module name="screenproperties" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="2944585505728fs"></ZoomStartTime>
+      <ZoomEndTime time="3965757255329fs"></ZoomEndTime>
+      <Cursor1Time time="7176632820000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="251"></NameColumnWidth>
+      <ValueColumnWidth column_width="185"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="7" />
+   <wvobject type="logic" fp_name="/TestSystem/CLK">
+      <obj_property name="ElementShortName">CLK</obj_property>
+      <obj_property name="ObjectShortName">CLK</obj_property>
+   </wvobject>
+   <wvobject type="group" fp_name="group135">
+      <obj_property name="label">Pipeline</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/CLK">
+         <obj_property name="ElementShortName">CLK</obj_property>
+         <obj_property name="ObjectShortName">CLK</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN">
+         <obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
+         <obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN_Av">
+         <obj_property name="ElementShortName">STD_IN_Av</obj_property>
+         <obj_property name="ObjectShortName">STD_IN_Av</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN_Request">
+         <obj_property name="ElementShortName">STD_IN_Request</obj_property>
+         <obj_property name="ObjectShortName">STD_IN_Request</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT">
+         <obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
+         <obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT_Av">
+         <obj_property name="ElementShortName">STD_OUT_Av</obj_property>
+         <obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT_Int">
+         <obj_property name="ElementShortName">STD_OUT_Int</obj_property>
+         <obj_property name="ObjectShortName">STD_OUT_Int</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_1">
+         <obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_1">
+         <obj_property name="ElementShortName">A_from_1[15:0]</obj_property>
+         <obj_property name="ObjectShortName">A_from_1[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_1">
+         <obj_property name="ElementShortName">B_from_1[15:0]</obj_property>
+         <obj_property name="ObjectShortName">B_from_1[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/C_from_1">
+         <obj_property name="ElementShortName">C_from_1[15:0]</obj_property>
+         <obj_property name="ObjectShortName">C_from_1[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_2">
+         <obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_2">
+         <obj_property name="ElementShortName">A_from_2[15:0]</obj_property>
+         <obj_property name="ObjectShortName">A_from_2[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_2">
+         <obj_property name="ElementShortName">B_from_2[15:0]</obj_property>
+         <obj_property name="ObjectShortName">B_from_2[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/C_from_2">
+         <obj_property name="ElementShortName">C_from_2[15:0]</obj_property>
+         <obj_property name="ObjectShortName">C_from_2[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_3">
+         <obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_3">
+         <obj_property name="ElementShortName">A_from_3[15:0]</obj_property>
+         <obj_property name="ObjectShortName">A_from_3[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_3">
+         <obj_property name="ElementShortName">B_from_3[15:0]</obj_property>
+         <obj_property name="ObjectShortName">B_from_3[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_4">
+         <obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_4">
+         <obj_property name="ElementShortName">A_from_4[15:0]</obj_property>
+         <obj_property name="ObjectShortName">A_from_4[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_4">
+         <obj_property name="ElementShortName">B_from_4[15:0]</obj_property>
+         <obj_property name="ObjectShortName">B_from_4[15:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group133">
+      <obj_property name="label">Gestion Instructions</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/CLK">
+         <obj_property name="ElementShortName">CLK</obj_property>
+         <obj_property name="ObjectShortName">CLK</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Z">
+         <obj_property name="ElementShortName">Z</obj_property>
+         <obj_property name="ObjectShortName">Z</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/A">
+         <obj_property name="ElementShortName">A[15:0]</obj_property>
+         <obj_property name="ObjectShortName">A[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/B">
+         <obj_property name="ElementShortName">B[15:0]</obj_property>
+         <obj_property name="ObjectShortName">B[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/C">
+         <obj_property name="ElementShortName">C[15:0]</obj_property>
+         <obj_property name="ObjectShortName">C[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Instruction">
+         <obj_property name="ElementShortName">Instruction[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Pointeur_instruction">
+         <obj_property name="ElementShortName">Pointeur_instruction[8:0]</obj_property>
+         <obj_property name="ObjectShortName">Pointeur_instruction[8:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Tableau">
+         <obj_property name="ElementShortName">Tableau[1:3]</obj_property>
+         <obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Adresse_Retour">
+         <obj_property name="ElementShortName">Adresse_Retour[8:0]</obj_property>
+         <obj_property name="ObjectShortName">Adresse_Retour[8:0]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Compteur_PRI">
+         <obj_property name="ElementShortName">Compteur_PRI</obj_property>
+         <obj_property name="ObjectShortName">Compteur_PRI</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/locked">
+         <obj_property name="ElementShortName">locked</obj_property>
+         <obj_property name="ObjectShortName">locked</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/compteur">
+         <obj_property name="ElementShortName">compteur</obj_property>
+         <obj_property name="ObjectShortName">compteur</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/bulles">
+         <obj_property name="ElementShortName">bulles</obj_property>
+         <obj_property name="ObjectShortName">bulles</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group132">
+      <obj_property name="label">Registres</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/CLK">
+         <obj_property name="ElementShortName">CLK</obj_property>
+         <obj_property name="ObjectShortName">CLK</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/W">
+         <obj_property name="ElementShortName">W</obj_property>
+         <obj_property name="ObjectShortName">W</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrA">
+         <obj_property name="ElementShortName">AddrA[3:0]</obj_property>
+         <obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrB">
+         <obj_property name="ElementShortName">AddrB[3:0]</obj_property>
+         <obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrC">
+         <obj_property name="ElementShortName">AddrC[3:0]</obj_property>
+         <obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrW">
+         <obj_property name="ElementShortName">AddrW[3:0]</obj_property>
+         <obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/DATA">
+         <obj_property name="ElementShortName">DATA[15:0]</obj_property>
+         <obj_property name="ObjectShortName">DATA[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QA">
+         <obj_property name="ElementShortName">QA[15:0]</obj_property>
+         <obj_property name="ObjectShortName">QA[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QB">
+         <obj_property name="ElementShortName">QB[15:0]</obj_property>
+         <obj_property name="ObjectShortName">QB[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QC">
+         <obj_property name="ElementShortName">QC[15:0]</obj_property>
+         <obj_property name="ObjectShortName">QC[15:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/REGISTRES">
+         <obj_property name="ElementShortName">REGISTRES[255:0]</obj_property>
+         <obj_property name="ObjectShortName">REGISTRES[255:0]</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group134">
+      <obj_property name="label">Memoire</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/EBP">
+         <obj_property name="ElementShortName">EBP[4:0]</obj_property>
+         <obj_property name="ObjectShortName">EBP[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/New_EBP">
+         <obj_property name="ElementShortName">New_EBP[4:0]</obj_property>
+         <obj_property name="ObjectShortName">New_EBP[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/Addr_MemoireDonnees">
+         <obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/IN_Addr_MemoireDonnees">
+         <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
+         <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/Addr_MemoireDonnees_EBP">
+         <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="group" fp_name="group197">
+         <obj_property name="label">MemoireDonnees</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/MEMORY">
+            <obj_property name="ElementShortName">MEMORY[511:0]</obj_property>
+            <obj_property name="ObjectShortName">MEMORY[511:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/D_OUT">
+            <obj_property name="ElementShortName">D_OUT[15:0]</obj_property>
+            <obj_property name="ObjectShortName">D_OUT[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/Addr">
+            <obj_property name="ElementShortName">Addr[4:0]</obj_property>
+            <obj_property name="ObjectShortName">Addr[4:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/RW">
+            <obj_property name="ElementShortName">RW</obj_property>
+            <obj_property name="ObjectShortName">RW</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/D_IN">
+            <obj_property name="ElementShortName">D_IN[15:0]</obj_property>
+            <obj_property name="ObjectShortName">D_IN[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/CALL">
+            <obj_property name="ElementShortName">CALL</obj_property>
+            <obj_property name="ObjectShortName">CALL</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/IN_EBP">
+            <obj_property name="ElementShortName">IN_EBP[15:0]</obj_property>
+            <obj_property name="ObjectShortName">IN_EBP[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
+            <obj_property name="ElementShortName">IN_AddrRet[15:0]</obj_property>
+            <obj_property name="ObjectShortName">IN_AddrRet[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/RET">
+            <obj_property name="ElementShortName">RET</obj_property>
+            <obj_property name="ObjectShortName">RET</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
+            <obj_property name="ElementShortName">OUT_EBP[15:0]</obj_property>
+            <obj_property name="ObjectShortName">OUT_EBP[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
+            <obj_property name="ElementShortName">OUT_AddrRet[15:0]</obj_property>
+            <obj_property name="ObjectShortName">OUT_AddrRet[15:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="group" fp_name="group198">
+         <obj_property name="label">MemoireAdressesRetour</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/R">
+            <obj_property name="ElementShortName">R</obj_property>
+            <obj_property name="ObjectShortName">R</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/W">
+            <obj_property name="ElementShortName">W</obj_property>
+            <obj_property name="ObjectShortName">W</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/D_IN">
+            <obj_property name="ElementShortName">D_IN[4:0]</obj_property>
+            <obj_property name="ObjectShortName">D_IN[4:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/D_OUT">
+            <obj_property name="ElementShortName">D_OUT[4:0]</obj_property>
+            <obj_property name="ObjectShortName">D_OUT[4:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/MEMORY">
+            <obj_property name="ElementShortName">MEMORY[19:0]</obj_property>
+            <obj_property name="ObjectShortName">MEMORY[19:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/Addr">
+            <obj_property name="ElementShortName">Addr[2:0]</obj_property>
+            <obj_property name="ObjectShortName">Addr[2:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group136">
+      <obj_property name="label">PeripheriqueEcran</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="group" fp_name="group216">
+         <obj_property name="label">VGAControleur</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_RED">
+            <obj_property name="ElementShortName">VGA_RED[3:0]</obj_property>
+            <obj_property name="ObjectShortName">VGA_RED[3:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_BLUE">
+            <obj_property name="ElementShortName">VGA_BLUE[3:0]</obj_property>
+            <obj_property name="ObjectShortName">VGA_BLUE[3:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_GREEN">
+            <obj_property name="ElementShortName">VGA_GREEN[3:0]</obj_property>
+            <obj_property name="ObjectShortName">VGA_GREEN[3:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_HS">
+            <obj_property name="ElementShortName">VGA_HS</obj_property>
+            <obj_property name="ObjectShortName">VGA_HS</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_VS">
+            <obj_property name="ElementShortName">VGA_VS</obj_property>
+            <obj_property name="ObjectShortName">VGA_VS</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/X">
+            <obj_property name="ElementShortName">X</obj_property>
+            <obj_property name="ObjectShortName">X</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/Y">
+            <obj_property name="ElementShortName">Y</obj_property>
+            <obj_property name="ObjectShortName">Y</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/PIXEL_ON">
+            <obj_property name="ElementShortName">PIXEL_ON</obj_property>
+            <obj_property name="ObjectShortName">PIXEL_ON</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/CLK">
+            <obj_property name="ElementShortName">CLK</obj_property>
+            <obj_property name="ObjectShortName">CLK</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/active">
+            <obj_property name="ElementShortName">active</obj_property>
+            <obj_property name="ObjectShortName">active</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="group" fp_name="group217">
+         <obj_property name="label">Ecran</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CLK">
+            <obj_property name="ElementShortName">CLK</obj_property>
+            <obj_property name="ObjectShortName">CLK</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_Av">
+            <obj_property name="ElementShortName">Data_Av</obj_property>
+            <obj_property name="ObjectShortName">Data_Av</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_IN">
+            <obj_property name="ElementShortName">Data_IN[0:6]</obj_property>
+            <obj_property name="ObjectShortName">Data_IN[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/X">
+            <obj_property name="ElementShortName">X</obj_property>
+            <obj_property name="ObjectShortName">X</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Y">
+            <obj_property name="ElementShortName">Y</obj_property>
+            <obj_property name="ObjectShortName">Y</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/OUT_ON">
+            <obj_property name="ElementShortName">OUT_ON</obj_property>
+            <obj_property name="ObjectShortName">OUT_ON</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Ecran">
+            <obj_property name="ElementShortName">Ecran[0:2239]</obj_property>
+            <obj_property name="ObjectShortName">Ecran[0:2239]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/L">
+            <obj_property name="ElementShortName">L[0:6]</obj_property>
+            <obj_property name="ObjectShortName">L[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/C">
+            <obj_property name="ElementShortName">C[0:6]</obj_property>
+            <obj_property name="ObjectShortName">C[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/InitialL">
+            <obj_property name="ElementShortName">InitialL[0:6]</obj_property>
+            <obj_property name="ObjectShortName">InitialL[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Full">
+            <obj_property name="ElementShortName">Full</obj_property>
+            <obj_property name="ObjectShortName">Full</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement">
+            <obj_property name="ElementShortName">point_dereferencement</obj_property>
+            <obj_property name="ObjectShortName">point_dereferencement</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement_ecriture">
+            <obj_property name="ElementShortName">point_dereferencement_ecriture</obj_property>
+            <obj_property name="ObjectShortName">point_dereferencement_ecriture</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentCodeASCII">
+            <obj_property name="ElementShortName">CurrentCodeASCII[0:6]</obj_property>
+            <obj_property name="ObjectShortName">CurrentCodeASCII[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentFont">
+            <obj_property name="ElementShortName">CurrentFont[0:63]</obj_property>
+            <obj_property name="ObjectShortName">CurrentFont[0:63]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="group" fp_name="group218">
+         <obj_property name="label">ScreenDriver</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/CLK">
+            <obj_property name="ElementShortName">CLK</obj_property>
+            <obj_property name="ObjectShortName">CLK</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/Value">
+            <obj_property name="ElementShortName">Value[15:0]</obj_property>
+            <obj_property name="ObjectShortName">Value[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/ValueAv">
+            <obj_property name="ElementShortName">ValueAv</obj_property>
+            <obj_property name="ObjectShortName">ValueAv</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/IsInt">
+            <obj_property name="ElementShortName">IsInt</obj_property>
+            <obj_property name="ObjectShortName">IsInt</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutData">
+            <obj_property name="ElementShortName">OutData[0:6]</obj_property>
+            <obj_property name="ObjectShortName">OutData[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutDataAv">
+            <obj_property name="ElementShortName">OutDataAv</obj_property>
+            <obj_property name="ObjectShortName">OutDataAv</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/intern_value">
+            <obj_property name="ElementShortName">intern_value[15:0]</obj_property>
+            <obj_property name="ObjectShortName">intern_value[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/current_hexa">
+            <obj_property name="ElementShortName">current_hexa[3:0]</obj_property>
+            <obj_property name="ObjectShortName">current_hexa[3:0]</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/compteur">
+            <obj_property name="ElementShortName">compteur</obj_property>
+            <obj_property name="ObjectShortName">compteur</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/work_in_progess">
+            <obj_property name="ElementShortName">work_in_progess</obj_property>
+            <obj_property name="ObjectShortName">work_in_progess</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/x_to_send">
+            <obj_property name="ElementShortName">x_to_send</obj_property>
+            <obj_property name="ObjectShortName">x_to_send</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/first_detected">
+            <obj_property name="ElementShortName">first_detected</obj_property>
+            <obj_property name="ObjectShortName">first_detected</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group159">
+      <obj_property name="label">Peripherique Clavier</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="group" fp_name="group160">
+         <obj_property name="label">Keyboard</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/CLK">
+            <obj_property name="ElementShortName">CLK</obj_property>
+            <obj_property name="ObjectShortName">CLK</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Clk">
+            <obj_property name="ElementShortName">PS2Clk</obj_property>
+            <obj_property name="ObjectShortName">PS2Clk</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Data">
+            <obj_property name="ElementShortName">PS2Data</obj_property>
+            <obj_property name="ObjectShortName">PS2Data</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_read">
+            <obj_property name="ElementShortName">Data_read</obj_property>
+            <obj_property name="ObjectShortName">Data_read</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_av">
+            <obj_property name="ElementShortName">Data_av</obj_property>
+            <obj_property name="ObjectShortName">Data_av</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data">
+            <obj_property name="ElementShortName">Data[0:6]</obj_property>
+            <obj_property name="ObjectShortName">Data[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/alert">
+            <obj_property name="ElementShortName">alert</obj_property>
+            <obj_property name="ObjectShortName">alert</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject type="group" fp_name="group161">
+         <obj_property name="label">KeyboardDriver</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/CLK">
+            <obj_property name="ElementShortName">CLK</obj_property>
+            <obj_property name="ObjectShortName">CLK</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_read">
+            <obj_property name="ElementShortName">Data_read</obj_property>
+            <obj_property name="ObjectShortName">Data_read</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_av">
+            <obj_property name="ElementShortName">Data_av</obj_property>
+            <obj_property name="ObjectShortName">Data_av</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data">
+            <obj_property name="ElementShortName">Data[0:6]</obj_property>
+            <obj_property name="ObjectShortName">Data[0:6]</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN">
+            <obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
+            <obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Av">
+            <obj_property name="ElementShortName">STD_IN_Av</obj_property>
+            <obj_property name="ObjectShortName">STD_IN_Av</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Request">
+            <obj_property name="ElementShortName">STD_IN_Request</obj_property>
+            <obj_property name="ObjectShortName">STD_IN_Request</obj_property>
+         </wvobject>
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT">
+            <obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
+            <obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
+            <obj_property name="Radix">HEXRADIX</obj_property>
+         </wvobject>
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT_Av">
+            <obj_property name="ElementShortName">STD_OUT_Av</obj_property>
+            <obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
+         </wvobject>
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/intern_value">
+            <obj_property name="ElementShortName">intern_value</obj_property>
+            <obj_property name="ObjectShortName">intern_value</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+</wave_config>