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Ajout module ecran et clavier au processeur (TAF : version non sécu, Tester)

Faure Paul 2 months ago
parent
commit
8b1dc18f3a

+ 2
- 2
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -108,8 +108,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
108 108
 
109 109
 
110 110
 ##Buttons
111
-#set_property PACKAGE_PIN U18 [get_ports btnC]
112
-#	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
111
+set_property PACKAGE_PIN U18 [get_ports btnC]
112
+	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113 113
 ##set_property PACKAGE_PIN T18 [get_ports btnU]
114 114
 #	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115 115
 #set_property PACKAGE_PIN W19 [get_ports btnL]

+ 87
- 0
Processeur.srcs/sim_1/new/TestScreenDriver.vhd View File

@@ -0,0 +1,87 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.07.2021 11:39:21
6
+-- Design Name: 
7
+-- Module Name: TestScreenDriver - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
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+-- 
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+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
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+-- Additional Comments:
18
+-- 
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+----------------------------------------------------------------------------------
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+
21
+
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+library IEEE;
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+use IEEE.STD_LOGIC_1164.ALL;
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+
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+-- Uncomment the following library declaration if using
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+-- arithmetic functions with Signed or Unsigned values
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+--use IEEE.NUMERIC_STD.ALL;
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+
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+-- Uncomment the following library declaration if instantiating
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+-- any Xilinx leaf cells in this code.
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+--library UNISIM;
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+--use UNISIM.VComponents.all;
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+
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+entity TestScreenDriver is
35
+--  Port ( );
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+end TestScreenDriver;
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+
38
+architecture Behavioral of TestScreenDriver is 
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+
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+    component ScreenDriver
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+    Generic ( Nb_bits : Natural
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+            );
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+    Port ( CLK       : in STD_LOGIC;
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+           Value     : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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+           ValueAv   : in STD_LOGIC;
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+           IsInt     : in STD_LOGIC;
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+           OutData   : out STD_LOGIC_VECTOR (0 to 6);
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+           OutDataAv : out STD_LOGIC);
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+    end component;
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+    
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+   signal CLK       : STD_LOGIC := '0';
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+   signal Value     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
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+   signal ValueAv   : STD_LOGIC := '0';
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+   signal IsInt     : STD_LOGIC := '0';
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+   signal OutData   : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
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+   signal OutDataAv : STD_LOGIC := '0';
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+   
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+   constant CLK_period : time := 10 ns;
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+
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+begin
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+
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+    instance : ScreenDriver
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+    Generic map ( Nb_bits => 16)
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+    Port map ( CLK       => CLK       ,
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+               Value     => Value     ,
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+               ValueAv   => ValueAv   ,
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+               IsInt     => IsInt     ,
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+               OutData   => OutData   ,
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+               OutDataAv => OutDataAv );
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+    
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+    CLK_process : process
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+    begin
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+        CLK <= '1';
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+        wait for CLK_period/2;
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+        CLK <= '0';
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+        wait for CLK_period/2;
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+    end process;
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+    
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+    process
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+    begin
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+        Value   <= "0000000001010101" after 10 ns, "11111111111111111" after 80 ns;
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+        ValueAv <= '1' after 10 ns, '0' after 30 ns,                  '1' after 80 ns, '0' after 90 ns;
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+        IsInt   <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
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+        wait;
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+    end process;
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+
87
+end Behavioral;

+ 90
- 0
Processeur.srcs/sim_1/new/TestSystem.vhd View File

@@ -0,0 +1,90 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 12.07.2021 08:34:17
6
+-- Design Name: 
7
+-- Module Name: TestSystem - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
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+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
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+
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+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
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+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
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+
34
+entity TestSystem is
35
+--  Port ( );
36
+end TestSystem;
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+
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+architecture Behavioral of TestSystem is
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+
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+    component System is
41
+    Port ( vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
42
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
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+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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+           Hsync    : out STD_LOGIC;
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+           Vsync    : out STD_LOGIC;
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+           PS2Clk : in STD_LOGIC;
47
+           PS2Data : in STD_LOGIC;
48
+           btnC : in STD_LOGIC;
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+           CLK : STD_LOGIC);
50
+    end component;
51
+    
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+    signal CLK : STD_LOGIC := '0';
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+    signal btnC : STD_LOGIC := '0';
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+    signal PS2Clk : STD_LOGIC := '0';
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+    signal PS2Data : STD_LOGIC := '0';
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+    signal vgaRed   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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+    signal vgaBlue  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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+    signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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+    signal Hsync    : STD_LOGIC := '0';
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+    signal Vsync    : STD_LOGIC := '0';
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+    
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+    constant CLK_period : time := 10 ns;
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+    
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+begin
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+    instance : System
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+    port map (vgaRed   => vgaRed,
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+              vgaBlue  => vgaBlue,
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+              vgaGreen => vgaGreen,
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+              Hsync    => Hsync,
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+              Vsync    => Vsync,
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+              PS2Clk => PS2Clk,
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+              PS2Data => PS2Data,
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+              btnC => btnC,
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+              CLK  => CLK);
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+              
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+    CLK_process :process
77
+    begin
78
+        CLK <= '1';
79
+        wait for CLK_period/2;
80
+        CLK <= '0';
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+        wait for CLK_period/2;
82
+    end process;
83
+    
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+    process 
85
+    begin
86
+        PS2Clk <= '1' after 3200 us, '0' after 3250 us, '1' after 3300 us, '0' after 3350 us, '1' after 3400 us, '0' after 3450 us, '1' after 3500 us, '0' after 3550 us, '1' after 3600 us, '0' after 3650 us, '1' after 3700 us, '0' after 3750 us, '1' after 3800 us, '0' after 3850 us, '1' after 3900 us, '0' after 3950 us, '1' after 4000 us, '0' after 4050 us, '1' after 4100 us, '0' after 4150 us, '1' after 4200 us, '0' after 4250 us, '1' after 5000 us, '0' after 5050 us, '1' after 5100 us, '0' after 5150 us, '1' after 5200 us, '0' after 5250 us, '1' after 5300 us, '0' after 5350 us, '1' after 5400 us, '0' after 5450 us, '1' after 5500 us, '0' after 5550 us, '1' after 5600 us, '0' after 5650 us, '1' after 5700 us, '0' after 5750 us, '1' after 5800 us, '0' after 5850 us, '1' after 5900 us, '0' after 5950 us, '1' after 6000 us, '0' after 6050 us;
87
+        PS2Data <= '0' after 3200 us, '1' after 3300 us, '0' after 3400 us, '1' after 3500 us, '0' after 3600 us, '1' after 3700 us, '1' after 3800 us, '1' after 3900 us, '0' after 4000 us, '0' after 4100 us, '1' after 4200 us, '0' after 4300 us, '0' after 5000 us, '0' after 5100 us, '1' after 5200 us, '0' after 5300 us, '1' after 5400 us, '1' after 5500 us, '0' after 5600 us, '1' after 5700 us, '0' after 5800 us, '1' after 5900 us, '1' after 6000 us, '0' after 6100 us;
88
+        wait;
89
+    end process;
90
+end Behavioral;

+ 2
- 2
Processeur.srcs/sources_1/new/Ecran.vhd View File

@@ -46,7 +46,7 @@ architecture Behavioral of Ecran is
46 46
     end component;
47 47
 
48 48
     constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000";
49
-    constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001101";
49
+    constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001010";
50 50
     constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111";
51 51
     
52 52
     signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); --(0 => '1', 1 => '0', 2 => '0', 3 => '1', 4 => '0', 5 => '0', 6 => '0', others => '0');
@@ -125,7 +125,7 @@ begin
125 125
     point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht)));
126 126
     point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)));
127 127
     
128
-    CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y/Display_CaracterHeight < L_Blocks and X/Display_CaracterWidht < C_Blocks and RST='1') else
128
+    CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y < screen_height and X < screen_width and RST='1') else
129 129
                         "0000000";
130 130
 
131 131
     OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width));

+ 38
- 8
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd View File

@@ -50,14 +50,17 @@
50 50
                  --                Instructions_critiques_lecture_C(5) = '0'  --> AFC ne lit pas dans le registre de l'opérande C
51 51
                  --                Instructions_critiques_ecriture(5) = '1'  --> AFC ecrit dans le registre de l'opérande A
52 52
                  
53
-                 Code_Instruction_JMP : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMP
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-                 Code_Instruction_JMZ : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMZ
55
-                 Code_Instruction_CALL : STD_LOGIC_VECTOR;  -- Numéro de l'instruction CALL
56
-                 Code_Instruction_RET : STD_LOGIC_VECTOR;   -- Numéro de l'instruction RET
57
-                 Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP
53
+                 Code_Instruction_JMP  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMP
54
+                 Code_Instruction_JMZ  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction JMZ
55
+                 Code_Instruction_PRI  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction PRI
56
+                 Code_Instruction_PRIC : STD_LOGIC_VECTOR;   -- Numéro de l'instruction PRIC
57
+                 Code_Instruction_CALL : STD_LOGIC_VECTOR;   -- Numéro de l'instruction CALL
58
+                 Code_Instruction_RET  : STD_LOGIC_VECTOR;   -- Numéro de l'instruction RET
59
+                 Code_Instruction_STOP : STD_LOGIC_VECTOR);  -- Numéro de l'instruction STOP
58 60
         Port ( CLK : in STD_LOGIC; -- Clock
59 61
                RST : in STD_LOGIC; -- Reset
60 62
                Z : in STD_LOGIC;   -- Flag Zero de l'ALU (utile pour le JMZ)
63
+               STD_IN_Request : in STD_LOGIC;
61 64
                A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
62 65
                B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
63 66
                C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
@@ -117,6 +120,9 @@
117 120
         -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k
118 121
         signal compteur : integer := 0;
119 122
         
123
+        -- Compteur de protection des collisions entre les prints
124
+        signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0;
125
+        
120 126
         -- Signal d'arret (STOP 0)
121 127
         signal locked : boolean := false;
122 128
         
@@ -153,16 +159,20 @@
153 159
                 Tableau <= (others => -1);
154 160
                 Pointeur_Instruction <= (others => '0');
155 161
                 compteur <= 0;
162
+                Compteur_PRI <= 0;
156 163
                 locked <= false;
157 164
                 C <= Argument_nul;
158 165
                 B <= Argument_nul;
159 166
                 A <= Argument_nul;
160 167
                 Instruction <= Instruction_nulle;
161
-            else
168
+            elsif (STD_IN_Request = '0') then
162 169
                 -- Avancement des instructions en écritures dans le pipeline
163 170
                 Tableau(3) <= Tableau(2);
164 171
                 Tableau(2) <= Tableau(1);
165 172
                 Tableau(1) <= -1;
173
+                if (Compteur_PRI > 0) then
174
+                    Compteur_PRI <= Compteur_PRI - 1;
175
+                end if;
166 176
                 if (not bulles) then
167 177
                     -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
168 178
                     if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
@@ -212,6 +222,14 @@
212 222
                         B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
213 223
                         A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
214 224
                         Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
225
+                    elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then
226
+                        -- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions
227
+                        Compteur_PRI <= Nb_bits/4 + 1;
228
+                        C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
229
+                        B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
230
+                        A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
231
+                        Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
232
+                        Pointeur_Instruction <= Pointeur_Instruction + 1;
215 233
                     else
216 234
                         -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau
217 235
                         C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
@@ -276,12 +294,24 @@
276 294
                 or 
277 295
                 (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
278 296
             )
297
+        )
298
+        or
299
+        (
300
+            (
301
+                (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI)
302
+                or
303
+                (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC)
304
+            )
305
+            and
306
+            (
307
+                not (Compteur_PRI = 0)
308
+            )
279 309
         );
280 310
         
281 311
         -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
282
-        R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
312
+        R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET and STD_IN_Request = '0' else
283 313
                  '0';
284
-        W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
314
+        W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL and STD_IN_Request = '0' else
285 315
                  '0';
286 316
                  
287 317
                  

+ 21
- 19
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -29,12 +29,17 @@ entity Etage2_5_Registres is
29 29
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
30 30
               Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
31 31
               Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
32
-              Code_Instruction_PRI : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
33
-              Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
32
+              Code_Instruction_PRI  : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
33
+              Code_Instruction_PRIC : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRIC
34
+              Code_Instruction_GET  : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
34 35
     Port ( CLK : in STD_LOGIC; -- Clock
35 36
            RST : in STD_LOGIC; -- Reset
36 37
            STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
38
+           STD_IN_Av : in STD_LOGIC;
39
+           STD_IN_Request : out STD_LOGIC;
37 40
            STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
41
+           STD_OUT_Av : out STD_LOGIC;
42
+           STD_OUT_Int : out STD_LOGIC;
38 43
            IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
39 44
            IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
40 45
            IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
@@ -95,7 +100,7 @@ architecture Behavioral of Etage2_5_Registres is
95 100
     signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
96 101
     signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
97 102
     signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
98
-    signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
103
+    
99 104
     
100 105
 begin
101 106
     instance_LC : LC
@@ -147,22 +152,19 @@ begin
147 152
                intern_OUT_2_C;
148 153
     OUT_2_Instruction <= (others => '0') when RST = '0' else
149 154
                          IN_2_Instruction;    
150
-     
151
-    -- Gestion de STD_OU (peut être améliorée) 
152
-    process 
153
-    begin
154
-        -- Synchronisation sur la clock
155
-        wait until CLK'event and CLK = '1';
156
-        if (RST = '0') then
157
-            intern_STD_OUT <= (others => '0');
158
-        else
159
-            if (IN_2_Instruction = Code_Instruction_PRI) then
160
-                intern_STD_OUT <= intern_OUT_2_A;
161
-            end if;
162
-        end if;
163
-    end process;
164
-    STD_OUT <= intern_STD_OUT when RST = '1' else
165
-               (others => '0');
155
+    
156
+    STD_OUT     <= (others => '0') when RST = '0' else
157
+                   intern_OUT_2_A;
158
+    STD_OUT_Av  <= '0' when RST = '0' else
159
+                   '1' when IN_2_Instruction = Code_Instruction_PRI or IN_2_Instruction = Code_Instruction_PRIC else
160
+                   '0';
161
+    STD_OUT_Int <= '0' when RST = '0' else
162
+                   '1' when IN_2_Instruction = Code_Instruction_PRI else
163
+                   '0';
164
+                   
165
+    STD_IN_Request <= '0' when RST = '0' else
166
+                      '1' when IN_5_Instruction = Code_Instruction_GET and STD_IN_Av = '0' else
167
+                      '0';
166 168
     
167 169
     
168 170
     

+ 25
- 9
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -49,15 +49,21 @@
49 49
 
50 50
     architecture Structural of Etage4_Memoire is
51 51
         component MemoireDonnees is
52
-        Generic (Nb_bits : Natural;
53
-                 Addr_size : Natural;
54
-                 Mem_size : Natural);
55
-        Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
56
-               RW : in STD_LOGIC;
57
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
58
-               RST : in STD_LOGIC;
59
-               CLK : in STD_LOGIC;
60
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
52
+        Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire 
53
+                 Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire
54
+                 Mem_size : Natural); -- Nombre de mot stockables
55
+        Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
56
+               RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
57
+               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
58
+               CALL : in STD_LOGIC; -- '1' -> CALL en cours
59
+               IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
60
+               IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
61
+               RET : in STD_LOGIC; -- '1' -> RET en cours
62
+               OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
63
+               OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
64
+               RST : in STD_LOGIC; -- Reset
65
+               CLK : in STD_LOGIC; -- Clock
66
+               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire 
61 67
         end component;
62 68
         
63 69
         component MemoireAdressesRetour is
@@ -112,6 +118,10 @@
112 118
         signal E : STD_LOGIC;
113 119
         signal F : STD_LOGIC;
114 120
         
121
+        -- Signaux inutiles
122
+        signal OUT_EBP : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
123
+        signal OUT_AddrRet : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
124
+        
115 125
         
116 126
     begin
117 127
         instance_LC : LC -- Link controleur sur la mémoire de donnees
@@ -155,6 +165,12 @@
155 165
         port map ( Addr => Addr_MemoireDonnees,
156 166
                    RW => Commande_MemoireDonnees(0),
157 167
                    D_IN => IN_B,
168
+                   CALL => '0',
169
+                   IN_EBP => (others => '0'),
170
+                   IN_AddrRet => (others => '0'),
171
+                   RET => '0',
172
+                   OUT_EBP => OUT_EBP,
173
+                   OUT_AddrRet => OUT_AddrRet,
158 174
                    RST => RST,
159 175
                    CLK => CLK,
160 176
                    D_OUT => Sortie_MemoireDonnees);

+ 0
- 0
Processeur.srcs/sources_1/new/IntToASCII.vhd View File


+ 86
- 0
Processeur.srcs/sources_1/new/KeyboardDriver.vhd View File

@@ -0,0 +1,86 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 13.07.2021 09:30:08
6
+-- Design Name: 
7
+-- Module Name: KeyboardDriver - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+use IEEE.NUMERIC_STD.ALL;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+--use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity KeyboardDriver is
37
+    Generic (Nb_Bits : Natural);
38
+    Port (CLK : in STD_LOGIC;
39
+          Data_read : out STD_LOGIC;
40
+          Data_av : in STD_LOGIC;
41
+          Data : in STD_LOGIC_VECTOR (0 to 6);
42
+          STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
43
+          STD_IN_Av : out STD_LOGIC;
44
+          STD_IN_Request : in STD_LOGIC;
45
+          STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
46
+          STD_OUT_Av : out STD_LOGIC);
47
+end KeyboardDriver;
48
+
49
+architecture Behavioral of KeyboardDriver is
50
+
51
+    signal intern_value : Natural := 0;
52
+    signal work_in_progress : BOOLEAN := false;
53
+    signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0');
54
+    
55
+
56
+begin
57
+
58
+    process
59
+    begin
60
+        wait until CLK'event and CLK = '1';
61
+        STD_IN_Av <= '0';        
62
+        STD_OUT_Av <= '0';
63
+        if not(work_in_progress) then
64
+            intern_value <= 0;
65
+        end if;
66
+        if STD_IN_Request = '1' then  
67
+            work_in_progress <= true;
68
+            if Data_av = '1' then
69
+                STD_OUT <= Zeros & Data;
70
+                STD_OUT_Av <= '1';
71
+                if (Data = "1111111") then
72
+                    intern_value <= intern_value / 10;
73
+                elsif (Data = "0001101") then
74
+                    STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits));
75
+                    STD_IN_Av <= '1';
76
+                    work_in_progress <= false;
77
+                elsif (Data >= "0110000" and Data <= "0111001") then
78
+                    intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6)));
79
+                end if;
80
+            end if;
81
+        end if; 
82
+    end process;
83
+    
84
+    Data_read <= '0' when STD_IN_Request = '0' else Data_av;
85
+
86
+end Behavioral;

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


+ 107
- 0
Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd View File

@@ -0,0 +1,107 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 13.07.2021 09:30:08
6
+-- Design Name: 
7
+-- Module Name: PeripheriqueClavier - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity PeripheriqueClavier is
35
+    Generic (Nb_Bits : Natural);
36
+    Port ( CLK : in STD_LOGIC;
37
+           RST : in STD_LOGIC;
38
+           PS2Clk : in STD_LOGIC;
39
+           PS2Data : in STD_LOGIC;
40
+           STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
41
+           STD_IN_Av : out STD_LOGIC;
42
+           STD_IN_Request : in STD_LOGIC;
43
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
44
+           STD_OUT_Av : out STD_LOGIC);
45
+end PeripheriqueClavier;
46
+
47
+architecture Behavioral of PeripheriqueClavier is
48
+
49
+    component KeyboardDriver
50
+        Generic (Nb_Bits : Natural);
51
+        Port (CLK : in STD_LOGIC;
52
+              Data_read : out STD_LOGIC;
53
+              Data_av : in STD_LOGIC;
54
+              Data : in STD_LOGIC_VECTOR (0 to 6);
55
+              STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
56
+              STD_IN_Av : out STD_LOGIC;
57
+              STD_IN_Request : in STD_LOGIC;
58
+              STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
59
+              STD_OUT_Av : out STD_LOGIC);
60
+    end component;
61
+    
62
+    component Keyboard 
63
+        Port (CLK : in STD_LOGIC;
64
+      
65
+              PS2Clk : in STD_LOGIC;
66
+              PS2Data : in STD_LOGIC;
67
+            
68
+              Data_read : in STD_LOGIC;
69
+              Data_av : out STD_LOGIC;
70
+              Data : out STD_LOGIC_VECTOR (0 to 6);
71
+            
72
+              alert : out STD_LOGIC);
73
+    end component;
74
+    
75
+    signal Data_read : STD_LOGIC := '0';
76
+    signal Data_av : STD_LOGIC := '0';
77
+    signal Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
78
+    
79
+    signal nothing : STD_LOGIC := '0';
80
+
81
+begin
82
+    
83
+    instance_Keyboard : Keyboard 
84
+    port map (CLK => CLK,
85
+  
86
+              PS2Clk => PS2Clk,
87
+              PS2Data => PS2Data,
88
+            
89
+              Data_read => Data_read,
90
+              Data_av => Data_av,
91
+              Data => Data,
92
+            
93
+              alert => nothing);
94
+              
95
+    instance_KeyboardDriver : KeyboardDriver
96
+    generic map (Nb_Bits => Nb_Bits)
97
+    port map (CLK => CLK,
98
+              Data_read => Data_read,
99
+              Data_av => Data_av,
100
+              Data => Data,
101
+              STD_IN => STD_IN,
102
+              STD_IN_Av => STD_IN_Av,
103
+              STD_IN_Request => STD_IN_Request,
104
+              STD_OUT => STD_OUT,
105
+              STD_OUT_Av => STD_OUT_Av);
106
+
107
+end Behavioral;

+ 150
- 0
Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd View File

@@ -0,0 +1,150 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.07.2021 15:25:56
6
+-- Design Name: 
7
+-- Module Name: PeripheriqueEcran - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+use work.ScreenProperties.all;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+--use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity PeripheriqueEcran is
37
+    Generic ( Nb_Bits : Natural);
38
+    Port ( CLK : in STD_LOGIC;
39
+           CLK_VGA : in STD_LOGIC;
40
+           RST : in STD_LOGIC;
41
+           
42
+           vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
43
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
44
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
45
+           Hsync    : out STD_LOGIC;
46
+           Vsync    : out STD_LOGIC;
47
+                     
48
+           STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
49
+           STD_OUT_Av : in STD_LOGIC;
50
+           STD_OUT_Int : in STD_LOGIC);
51
+end PeripheriqueEcran;
52
+
53
+architecture Behavioral of PeripheriqueEcran is
54
+
55
+component VGAControler is
56
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
57
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
58
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
59
+               VGA_HS    : out STD_LOGIC;
60
+               VGA_VS    : out STD_LOGIC;
61
+               
62
+               X         : out X_T;
63
+               Y         : out Y_T;
64
+               PIXEL_ON  : in STD_LOGIC;
65
+               
66
+               CLK       : in STD_LOGIC;
67
+               RST       : in STD_LOGIC);
68
+    end component; 
69
+    
70
+    component clk_wiz_0
71
+    port
72
+     (-- Clock in ports
73
+      clk_in1           : in     std_logic;
74
+      -- Clock out ports
75
+      clk_out1          : out    std_logic
76
+     );
77
+    end component;
78
+    
79
+    component Ecran is
80
+        Port (     CLK            : in STD_LOGIC;
81
+                   RST            : in STD_LOGIC;
82
+                   Data_Av        : in STD_LOGIC;
83
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
84
+                   X              : in X_T;
85
+                   Y              : in Y_T;
86
+                   OUT_ON         : out STD_LOGIC);
87
+    end component;
88
+    
89
+    component ScreenDriver 
90
+        Generic ( Nb_bits : Natural
91
+                );
92
+        Port ( CLK : in STD_LOGIC;
93
+               Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
94
+               ValueAv : in STD_LOGIC;
95
+               IsInt : in STD_LOGIC;
96
+               OutData : out STD_LOGIC_VECTOR (0 to 6);
97
+               OutDataAv : out STD_LOGIC);
98
+    end component;
99
+    
100
+    signal my_X : X_T := 0;
101
+    signal my_Y : Y_T := 0;
102
+    signal my_PIXEL_ON : STD_LOGIC := '0';
103
+    signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
104
+    signal OutDataAv : STD_LOGIC := '0';    
105
+    signal my_CLK : STD_LOGIC := '0';
106
+
107
+begin
108
+
109
+    instanceVGA : VGAControler 
110
+    port map(  VGA_RED   => vgaRed,
111
+               VGA_BLUE  => vgaBlue,
112
+               VGA_GREEN => vgaGreen,
113
+               VGA_HS    => Hsync,
114
+               VGA_VS    => Vsync,
115
+                 
116
+               X         => my_X,
117
+               Y         => my_Y,
118
+               PIXEL_ON  => my_PIXEL_ON,
119
+                 
120
+               CLK       => my_CLK,
121
+               RST       => RST);
122
+               
123
+    
124
+    clk_wiz_0_inst : clk_wiz_0
125
+    port map (
126
+              clk_in1 => CLK_VGA,
127
+              clk_out1 => my_CLK
128
+             );
129
+    
130
+    
131
+    instance_Ecran : Ecran
132
+    port map (     CLK     => CLK,
133
+                   RST     => RST,
134
+                   Data_Av => OutDataAv,
135
+                   Data_IN => OutData,
136
+                   X => my_X,
137
+                   Y => my_Y,
138
+                   OUT_ON => my_PIXEL_ON);
139
+                   
140
+    instance_ScreenDriver : ScreenDriver 
141
+    Generic map ( Nb_bits => Nb_Bits
142
+                )
143
+    Port map ( CLK => CLK,
144
+               Value => STD_OUT,
145
+               ValueAv => STD_OUT_Av,
146
+               IsInt => STD_OUT_Int,
147
+               OutData => OutData,
148
+               OutDataAv => OutDataAv);
149
+
150
+end Behavioral;

+ 91
- 63
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -44,10 +44,14 @@ entity Pipeline is
44 44
              Adresse_mem_size : Natural := 5;
45 45
              Memoire_Adresses_Retour_Size : Natural := 16;
46 46
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
47
-    Port (CLK : STD_LOGIC;
48
-          RST : STD_LOGIC;
49
-          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50
-          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
47
+    Port (CLK : in STD_LOGIC;
48
+          RST : in STD_LOGIC;
49
+          STD_IN      : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
50
+          STD_IN_Av   : in STD_LOGIC;
51
+          STD_IN_Request  : out STD_LOGIC;
52
+          STD_OUT     : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
53
+          STD_OUT_Av  : out STD_LOGIC;
54
+          STD_OUT_Int : out STD_LOGIC);
51 55
 end Pipeline;
52 56
 
53 57
 architecture Behavioral of Pipeline is
@@ -67,12 +71,15 @@ architecture Behavioral of Pipeline is
67 71
              Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
68 72
              Code_Instruction_JMP : STD_LOGIC_VECTOR;
69 73
              Code_Instruction_JMZ : STD_LOGIC_VECTOR;
74
+             Code_Instruction_PRI  : STD_LOGIC_VECTOR;   
75
+             Code_Instruction_PRIC : STD_LOGIC_VECTOR;   
70 76
              Code_Instruction_CALL : STD_LOGIC_VECTOR;
71 77
              Code_Instruction_RET : STD_LOGIC_VECTOR;
72 78
              Code_Instruction_STOP : STD_LOGIC_VECTOR);
73 79
     Port ( CLK : in STD_LOGIC;
74 80
            RST : in STD_LOGIC;
75 81
            Z : in STD_LOGIC;
82
+           STD_IN_Request : in STD_LOGIC;
76 83
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
77 84
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
78 85
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -80,30 +87,35 @@ architecture Behavioral of Pipeline is
80 87
     end component;
81 88
     
82 89
     component Etage2_5_Registres is
83
-    Generic ( Nb_bits : Natural;
84
-              Nb_registres : Natural;
85
-              Addr_registres_size : Natural;
86
-              Instruction_bus_size : Natural;
87
-              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
88
-              Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
89
-              Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
90
-              Code_Instruction_PRI : STD_LOGIC_VECTOR;
91
-              Code_Instruction_GET : STD_LOGIC_VECTOR);
92
-    Port ( CLK : in STD_LOGIC;
93
-           RST : in STD_LOGIC;
94
-           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
95
-           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
96
-           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
97
-           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
98
-           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
99
-           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
100
-           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
101
-           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
102
-           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
103
-           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
104
-           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
105
-           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
106
-           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
90
+        Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
91
+                  Nb_registres : Natural; -- Nombre de registres du processeurs
92
+                  Addr_registres_size : Natural; -- Nombre de bits pour adresser les registres
93
+                  Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
94
+                  Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
95
+                  Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
96
+                  Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
97
+                  Code_Instruction_PRI  : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRI
98
+                  Code_Instruction_PRIC : STD_LOGIC_VECTOR;  -- Numéro de l'instruction PRIC
99
+                  Code_Instruction_GET  : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
100
+        Port ( CLK : in STD_LOGIC; -- Clock
101
+               RST : in STD_LOGIC; -- Reset
102
+               STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
103
+               STD_IN_Av : in STD_LOGIC;
104
+               STD_IN_Request : out STD_LOGIC;
105
+               STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
106
+               STD_OUT_Av : out STD_LOGIC;
107
+               STD_OUT_Int : out STD_LOGIC;
108
+               IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
109
+               IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
110
+               IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
111
+               IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction de l'étage 2
112
+               OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A de l'étage 2
113
+               OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B de l'étage 2
114
+               OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C de l'étage 2
115
+               OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction de l'étage 2
116
+               IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 5
117
+               IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 5
118
+               IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Entrée de l'instruction de l'étage 5
107 119
     end component;
108 120
     
109 121
     component Etage3_Calcul is
@@ -181,27 +193,31 @@ architecture Behavioral of Pipeline is
181 193
     signal O : STD_LOGIC := '0';
182 194
     signal C : STD_LOGIC := '0';
183 195
     
184
-    constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
185
-    constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
196
+    signal intern_STD_IN_Request : STD_LOGIC := '0';
197
+    
198
+    
199
+    constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111";
200
+    constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001";
186 201
     constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
187
-    constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
188
-    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
189
-    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
190
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
191
-    constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
192
-    constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
202
+    constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001";
203
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111";
204
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111";
205
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111011001111111111";
206
+    constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000";
207
+    constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
193 208
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
194 209
     constant Code_Instruction_JMZ  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
195 210
     constant Code_Instruction_PRI  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
196
-    constant Code_Instruction_GET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
197
-    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
198
-    constant Code_Instruction_RET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
199
-    constant Code_Instruction_STOP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
211
+    constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; -------- TO BE DONE 
212
+    constant Code_Instruction_GET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
213
+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
214
+    constant Code_Instruction_RET  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
215
+    constant Code_Instruction_STOP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110";
200 216
     
201
-    constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
202
-    constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
203
-    constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
204
-    constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
217
+    constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000";
218
+    constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110";
219
+    constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110";
220
+    constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
205 221
 begin
206 222
     instance_Etage1 : Etage1_LectureInstruction
207 223
     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
@@ -218,6 +234,8 @@ begin
218 234
                  Instructions_critiques_ecriture => Instructions_critiques_ecriture,
219 235
                  Code_Instruction_JMP => Code_Instruction_JMP,
220 236
                  Code_Instruction_JMZ => Code_Instruction_JMZ,
237
+                 Code_Instruction_PRI  => Code_Instruction_PRI, 
238
+                 Code_Instruction_PRIC => Code_Instruction_PRIC,   
221 239
                  Code_Instruction_CALL => Code_Instruction_CALL,
222 240
                  Code_Instruction_RET => Code_Instruction_RET,
223 241
                  Code_Instruction_STOP => Code_Instruction_STOP
@@ -226,6 +244,7 @@ begin
226 244
         CLK => CLK,
227 245
         RST => RST,
228 246
         Z => Z,
247
+        STD_IN_Request => intern_STD_IN_Request,
229 248
         A => A_from_1,
230 249
         B => B_from_1,
231 250
         C => C_from_1,
@@ -241,12 +260,17 @@ begin
241 260
                  Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
242 261
                  Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
243 262
                  Code_Instruction_PRI => Code_Instruction_PRI,
263
+                 Code_Instruction_PRIC =>  Code_Instruction_PRIC,
244 264
                  Code_Instruction_GET => Code_Instruction_GET
245 265
     )
246 266
     port map(    CLK => CLK,
247 267
                  RST => RST,
248
-                 STD_IN => STD_IN,
249
-                 STD_OUT => STD_OUT,
268
+                 STD_IN      => STD_IN,
269
+                 STD_IN_Av   => STD_IN_Av,
270
+                 STD_IN_Request  => intern_STD_IN_Request,
271
+                 STD_OUT     => STD_OUT,
272
+                 STD_OUT_Av  => STD_OUT_Av,
273
+                 STD_OUT_Int => STD_OUT_Int,
250 274
                  IN_2_A => A_to_2,
251 275
                  IN_2_B => B_to_2,
252 276
                  IN_2_C => C_to_2,
@@ -303,26 +327,30 @@ begin
303 327
                  OUT_B => B_from_4,
304 328
                  OUT_Instruction => Instruction_from_4
305 329
     );
330
+    
331
+    STD_IN_Request <= intern_STD_IN_Request;
306 332
 
307 333
     process
308 334
     begin
309 335
         wait until CLK'event and CLK = '1';
310
-        A_to_2 <= A_from_1;
311
-        B_to_2 <= B_from_1;
312
-        C_to_2 <= C_from_1;
313
-        Instruction_to_2 <= Instruction_from_1;
314
-        
315
-        A_to_3 <= A_from_2;
316
-        B_to_3 <= B_from_2;
317
-        C_to_3 <= C_from_2;
318
-        Instruction_to_3 <= Instruction_from_2;
319
-
320
-        A_to_4 <= A_from_3;
321
-        B_to_4 <= B_from_3;
322
-        Instruction_to_4 <= Instruction_from_3;
323
-
324
-        A_to_5 <= A_from_4;
325
-        B_to_5 <= B_from_4;
326
-        Instruction_to_5 <= Instruction_from_4;
336
+        if (intern_STD_IN_Request = '0') then
337
+            A_to_2 <= A_from_1;
338
+            B_to_2 <= B_from_1;
339
+            C_to_2 <= C_from_1;
340
+            Instruction_to_2 <= Instruction_from_1;
341
+            
342
+            A_to_3 <= A_from_2;
343
+            B_to_3 <= B_from_2;
344
+            C_to_3 <= C_from_2;
345
+            Instruction_to_3 <= Instruction_from_2;
346
+    
347
+            A_to_4 <= A_from_3;
348
+            B_to_4 <= B_from_3;
349
+            Instruction_to_4 <= Instruction_from_3;
350
+    
351
+            A_to_5 <= A_from_4;
352
+            B_to_5 <= B_from_4;
353
+            Instruction_to_5 <= Instruction_from_4;
354
+        end if;
327 355
     end process;        
328 356
 end Behavioral;

+ 142
- 0
Processeur.srcs/sources_1/new/ScreenDriver.vhd View File

@@ -0,0 +1,142 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.07.2021 09:54:12
6
+-- Design Name: 
7
+-- Module Name: ScreenDriver - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+use IEEE.NUMERIC_STD.ALL;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+--use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity ScreenDriver is
37
+    Generic ( Nb_bits : Natural
38
+            );
39
+    Port ( CLK : in STD_LOGIC;
40
+           Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
41
+           ValueAv : in STD_LOGIC;
42
+           IsInt : in STD_LOGIC;
43
+           OutData : out STD_LOGIC_VECTOR (0 to 6);
44
+           OutDataAv : out STD_LOGIC);
45
+end ScreenDriver;
46
+
47
+architecture Behavioral of ScreenDriver is
48
+
49
+    signal intern_value : STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0) := (others => '0');
50
+    signal current_hexa : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
51
+    subtype compteur_T is Natural range 0 to Nb_bits/4 - 1;
52
+    signal compteur : compteur_T := 0; 
53
+    signal work_in_progess : BOOLEAN := false;    
54
+    signal x_to_send : BOOLEAN := false;    
55
+    signal first_detected : BOOLEAN := false;
56
+    
57
+
58
+begin
59
+
60
+    current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4);
61
+
62
+    process
63
+    begin
64
+        wait until CLK'event and CLK = '1';
65
+        if ValueAv = '1' then  
66
+            if IsInt = '0' then
67
+                OutData <= Value (6 downto 0);
68
+            else 
69
+                intern_value <= Value;
70
+                OutData <= "0110000";
71
+                x_to_send <= true;
72
+            end if;
73
+            OutDataAv <= '1';
74
+        elsif x_to_send then
75
+            OutData <= "1111000";
76
+            OutDataAv <= '1';
77
+            x_to_send <= false;
78
+            work_in_progess <= true;
79
+            first_detected <= false;
80
+        elsif work_in_progess then
81
+            case current_hexa is
82
+            when "0000" =>
83
+                if first_detected or compteur = Nb_bits/4 - 1 then
84
+                    OutData <= "0110000";
85
+                end if;
86
+            when "0001" =>
87
+                OutData <= "0110001";
88
+            when "0010" =>
89
+                OutData <= "0110010";
90
+            when "0011" =>
91
+                OutData <= "0110011";
92
+            when "0100" =>
93
+                OutData <= "0110100";
94
+            when "0101" =>
95
+                OutData <= "0110101";
96
+            when "0110" =>
97
+                OutData <= "0110110";
98
+            when "0111" =>
99
+                OutData <= "0110111";
100
+            when "1000" =>
101
+                OutData <= "0111000";
102
+            when "1001" =>
103
+                OutData <= "0111001";
104
+            when "1010" =>
105
+                OutData <= "1000001";
106
+            when "1011" =>
107
+                OutData <= "1000010";
108
+            when "1100" =>
109
+                OutData <= "1000011";
110
+            when "1101" =>
111
+                OutData <= "1000100";
112
+            when "1110" =>
113
+                OutData <= "1000101";
114
+            when "1111" =>
115
+                OutData <= "1000110";
116
+            when others => 
117
+                OutData <= "0000001";
118
+            end case;
119
+            
120
+            
121
+            if first_detected or not (current_hexa = "0000") or compteur = Nb_bits/4 - 1 then
122
+                OutDataAv <= '1';
123
+                first_detected <= true;
124
+            else 
125
+                OutDataAv <= '0';
126
+                first_detected <= false;
127
+            end if;
128
+            
129
+            if (compteur = Nb_bits/4 - 1) then
130
+                compteur <= 0;
131
+                work_in_progess <= false;    
132
+                x_to_send       <= false;    
133
+                first_detected  <= false;
134
+            else 
135
+                compteur <= compteur + 1;
136
+            end if;
137
+        else 
138
+            OutDataAv <= '0';
139
+        end if;
140
+    end process;
141
+
142
+end Behavioral;

+ 114
- 15
Processeur.srcs/sources_1/new/System.vhd View File

@@ -24,8 +24,13 @@ use IEEE.STD_LOGIC_1164.ALL;
24 24
 --   Récupération d'un bouton pour RST
25 25
 --   Récupération de la clock
26 26
 entity System is
27
-    Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
28
-           sw : in STD_LOGIC_VECTOR (7 downto 0);
27
+    Port ( vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
28
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
29
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
30
+           Hsync    : out STD_LOGIC;
31
+           Vsync    : out STD_LOGIC;
32
+           PS2Clk : in STD_LOGIC;
33
+           PS2Data : in STD_LOGIC;
29 34
            btnC : in STD_LOGIC;
30 35
            CLK : STD_LOGIC);
31 36
 end System;
@@ -45,10 +50,14 @@ architecture Structural of System is
45 50
              Adresse_mem_size : Natural := 5;
46 51
              Memoire_Adresses_Retour_Size : Natural := 16;
47 52
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
48
-    Port (CLK : STD_LOGIC;
49
-          RST : STD_LOGIC;
50
-          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
51
-          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
53
+    Port (CLK : in STD_LOGIC;
54
+          RST : in STD_LOGIC;
55
+          STD_IN          : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
56
+          STD_IN_Av       : in STD_LOGIC;
57
+          STD_IN_Request  : out STD_LOGIC;
58
+          STD_OUT         : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
59
+          STD_OUT_Av      : out STD_LOGIC;
60
+          STD_OUT_Int     : out STD_LOGIC);
52 61
     end component;
53 62
 
54 63
     component Pipeline_NS is
@@ -66,6 +75,36 @@ architecture Structural of System is
66 75
           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
67 76
     end component;
68 77
     
78
+    component PeripheriqueEcran 
79
+    Generic ( Nb_Bits : Natural);
80
+    Port ( CLK : in STD_LOGIC;
81
+           CLK_VGA : in STD_LOGIC;
82
+           RST : in STD_LOGIC;
83
+           
84
+           vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
85
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
86
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
87
+           Hsync    : out STD_LOGIC;
88
+           Vsync    : out STD_LOGIC;
89
+                     
90
+           STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
91
+           STD_OUT_Av : in STD_LOGIC;
92
+           STD_OUT_Int : in STD_LOGIC);
93
+    end component;
94
+    
95
+    component PeripheriqueClavier 
96
+    Generic (Nb_Bits : Natural);
97
+    Port ( CLK : in STD_LOGIC;
98
+           RST : in STD_LOGIC;
99
+           PS2Clk : in STD_LOGIC;
100
+           PS2Data : in STD_LOGIC;
101
+           STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
102
+           STD_IN_Av : out STD_LOGIC;
103
+           STD_IN_Request : in STD_LOGIC;
104
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
105
+           STD_OUT_Av : out STD_LOGIC);
106
+    end component;
107
+    
69 108
     component Clock_Divider is
70 109
         Port ( CLK_IN : in STD_LOGIC;
71 110
                CLK_OUT : out STD_LOGIC);
@@ -74,10 +113,22 @@ architecture Structural of System is
74 113
     -- signaux auxiliaires
75 114
     signal my_RST : STD_LOGIC;
76 115
     signal my_CLK : STD_LOGIC;
116
+    signal STD_IN      : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
117
+    signal STD_IN_Av   : STD_LOGIC := '0';
118
+    signal STD_IN_Request  : STD_LOGIC := '0';
119
+    signal intern_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
120
+    signal intern_STD_OUT_Av  : STD_LOGIC := '0';
121
+    signal intern_STD_OUT_Int : STD_LOGIC := '0';
122
+    signal pipeline_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
123
+    signal pipeline_STD_OUT_Av  : STD_LOGIC := '0';
124
+    signal pipeline_STD_OUT_Int : STD_LOGIC := '0';
125
+    signal clavier_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 
126
+    signal clavier_STD_OUT_Av  : STD_LOGIC := '0';
127
+    signal clavier_STD_OUT_Int : STD_LOGIC := '0';
77 128
     
78 129
     constant SECURISED : boolean := true;
79 130
         
80
-begin     
131
+begin    
81 132
            
82 133
     -- Diviseur de clock
83 134
     clk_div : Clock_Divider
@@ -88,25 +139,73 @@ begin
88 139
     -- Generation du processeur en fonction de la condition sécurisé ou non       
89 140
     instance: if (SECURISED) generate
90 141
         instance_securisee : entity work.Pipeline
91
-            generic map (Addr_Memoire_Instruction_Size => 8,
92
-                         Memoire_Instruction_Size => 256)
142
+            generic map (Nb_bits => 16,
143
+                         Instruction_En_Memoire_Size => 53,
144
+                         Addr_Memoire_Instruction_Size => 9,
145
+                         Memoire_Instruction_Size => 512,
146
+                         Instruction_Bus_Size => 5,
147
+                         Nb_Instructions => 32,
148
+                         Nb_Registres => 16,
149
+                         Addr_registres_size => 4,
150
+                         Memoire_Size => 32,
151
+                         Adresse_mem_size => 5,
152
+                         Memoire_Adresses_Retour_Size => 4,
153
+                         Adresse_Memoire_Adresses_Retour_Size => 2)
93 154
             port map (CLK => my_CLK,
94 155
                       RST => my_RST,
95
-                      STD_IN => sw,
96
-                      STD_OUT => led);
156
+                      STD_IN      => STD_IN,
157
+                      STD_IN_Av   => STD_IN_Av,
158
+                      STD_IN_Request => STD_IN_Request,
159
+                      STD_OUT     => pipeline_STD_OUT,
160
+                      STD_OUT_Av  => pipeline_STD_OUT_Av,
161
+                      STD_OUT_Int => pipeline_STD_OUT_Int);
97 162
     else generate
98 163
         instance_non_securisee : entity work.Pipeline_NS
99
-            generic map (Addr_Memoire_Instruction_Size => 8,
100
-                         Memoire_Instruction_Size => 256)
164
+            generic map (Addr_Memoire_Instruction_Size => 9,
165
+                         Memoire_Instruction_Size => 512)
101 166
             port map (CLK => my_CLK,
102 167
                       RST => my_RST,
103
-                      STD_IN => sw,
104
-                      STD_OUT => led);
168
+                      STD_IN => STD_IN,
169
+                      STD_OUT => pipeline_STD_OUT);
105 170
     end generate;  
171
+    
172
+    instance_perif_ecran : PeripheriqueEcran 
173
+    generic map ( Nb_Bits => 16)
174
+    port map ( CLK => my_CLK,
175
+               CLK_VGA => CLK,
176
+               RST => my_RST,
177
+               
178
+               vgaRed   => vgaRed,
179
+               vgaBlue  => vgaBlue,
180
+               vgaGreen => vgaGreen,
181
+               Hsync    => Hsync,
182
+               Vsync    => Vsync,
183
+                         
184
+               STD_OUT =>     intern_STD_OUT,
185
+               STD_OUT_Av =>  intern_STD_OUT_Av,
186
+               STD_OUT_Int => intern_STD_OUT_Int);
187
+               
188
+    instance_perif_clavier : PeripheriqueClavier 
189
+    generic map (Nb_Bits => 16)
190
+    port map ( CLK => my_CLK,
191
+               RST => my_RST,
192
+               PS2Clk => PS2Clk,
193
+               PS2Data => PS2Data,
194
+               STD_IN => STD_IN,
195
+               STD_IN_Av => STD_IN_Av,
196
+               STD_IN_Request => STD_IN_Request,
197
+               STD_OUT =>    clavier_STD_OUT,
198
+               STD_OUT_Av => clavier_STD_OUT_Av);
106 199
           
107 200
               
108 201
     -- Gestion du RST (inversion d'état)
109 202
     my_RST <= '1' when btnC = '0' else
110 203
               '0';
204
+              
205
+    
206
+    intern_STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
207
+    intern_STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
208
+    intern_STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
209
+    
111 210
 end Structural;
112 211
 

+ 51
- 3
Processeur.xpr View File

@@ -35,7 +35,7 @@
35 35
     <Option Name="DSAVendor" Val="xilinx"/>
36 36
     <Option Name="DSABoardId" Val="basys3"/>
37 37
     <Option Name="DSANumComputeUnits" Val="16"/>
38
-    <Option Name="WTXSimLaunchSim" Val="473"/>
38
+    <Option Name="WTXSimLaunchSim" Val="543"/>
39 39
     <Option Name="WTModelSimLaunchSim" Val="0"/>
40 40
     <Option Name="WTQuestaLaunchSim" Val="0"/>
41 41
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -251,9 +251,39 @@
251 251
           <Attr Name="UsedIn" Val="simulation"/>
252 252
         </FileInfo>
253 253
       </File>
254
+      <File Path="$PSRCDIR/sources_1/new/IntToASCII.vhd">
255
+        <FileInfo>
256
+          <Attr Name="UsedIn" Val="synthesis"/>
257
+          <Attr Name="UsedIn" Val="simulation"/>
258
+        </FileInfo>
259
+      </File>
260
+      <File Path="$PSRCDIR/sources_1/new/ScreenDriver.vhd">
261
+        <FileInfo>
262
+          <Attr Name="UsedIn" Val="synthesis"/>
263
+          <Attr Name="UsedIn" Val="simulation"/>
264
+        </FileInfo>
265
+      </File>
266
+      <File Path="$PSRCDIR/sources_1/new/PeripheriqueEcran.vhd">
267
+        <FileInfo>
268
+          <Attr Name="UsedIn" Val="synthesis"/>
269
+          <Attr Name="UsedIn" Val="simulation"/>
270
+        </FileInfo>
271
+      </File>
272
+      <File Path="$PSRCDIR/sources_1/new/PeripheriqueClavier.vhd">
273
+        <FileInfo>
274
+          <Attr Name="UsedIn" Val="synthesis"/>
275
+          <Attr Name="UsedIn" Val="simulation"/>
276
+        </FileInfo>
277
+      </File>
278
+      <File Path="$PSRCDIR/sources_1/new/KeyboardDriver.vhd">
279
+        <FileInfo>
280
+          <Attr Name="UsedIn" Val="synthesis"/>
281
+          <Attr Name="UsedIn" Val="simulation"/>
282
+        </FileInfo>
283
+      </File>
254 284
       <Config>
255 285
         <Option Name="DesignMode" Val="RTL"/>
256
-        <Option Name="TopModule" Val="SystemKeyboardScreen"/>
286
+        <Option Name="TopModule" Val="System"/>
257 287
       </Config>
258 288
     </FileSet>
259 289
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@@ -397,9 +427,26 @@
397 427
           <Attr Name="UsedIn" Val="simulation"/>
398 428
         </FileInfo>
399 429
       </File>
430
+      <File Path="$PSRCDIR/sim_1/new/TestScreenDriver.vhd">
431
+        <FileInfo>
432
+          <Attr Name="UsedIn" Val="synthesis"/>
433
+          <Attr Name="UsedIn" Val="simulation"/>
434
+        </FileInfo>
435
+      </File>
436
+      <File Path="$PSRCDIR/sim_1/new/TestSystem.vhd">
437
+        <FileInfo>
438
+          <Attr Name="UsedIn" Val="synthesis"/>
439
+          <Attr Name="UsedIn" Val="simulation"/>
440
+        </FileInfo>
441
+      </File>
442
+      <File Path="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg">
443
+        <FileInfo>
444
+          <Attr Name="UsedIn" Val="simulation"/>
445
+        </FileInfo>
446
+      </File>
400 447
       <Config>
401 448
         <Option Name="DesignMode" Val="RTL"/>
402
-        <Option Name="TopModule" Val="Test_SystemKeyboardScreen"/>
449
+        <Option Name="TopModule" Val="TestSystem"/>
403 450
         <Option Name="TopLib" Val="xil_defaultlib"/>
404 451
         <Option Name="TransportPathDelay" Val="0"/>
405 452
         <Option Name="TransportIntDelay" Val="0"/>
@@ -408,6 +455,7 @@
408 455
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
409 456
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
410 457
         <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
458
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg"/>
411 459
       </Config>
412 460
     </FileSet>
413 461
   </FileSets>

+ 581
- 0
SimulationsConfig/TestSystem_behav.wcfg View File

@@ -0,0 +1,581 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<wave_config>
3
+   <wave_state>
4
+   </wave_state>
5
+   <db_ref_list>
6
+      <db_ref path="TestSystem_behav.wdb" id="1">
7
+         <top_modules>
8
+            <top_module name="TestSystem" />
9
+            <top_module name="font" />
10
+            <top_module name="screenproperties" />
11
+         </top_modules>
12
+      </db_ref>
13
+   </db_ref_list>
14
+   <zoom_setting>
15
+      <ZoomStartTime time="2944585505728fs"></ZoomStartTime>
16
+      <ZoomEndTime time="3965757255329fs"></ZoomEndTime>
17
+      <Cursor1Time time="7176632820000fs"></Cursor1Time>
18
+   </zoom_setting>
19
+   <column_width_setting>
20
+      <NameColumnWidth column_width="251"></NameColumnWidth>
21
+      <ValueColumnWidth column_width="185"></ValueColumnWidth>
22
+   </column_width_setting>
23
+   <WVObjectSize size="7" />
24
+   <wvobject type="logic" fp_name="/TestSystem/CLK">
25
+      <obj_property name="ElementShortName">CLK</obj_property>
26
+      <obj_property name="ObjectShortName">CLK</obj_property>
27
+   </wvobject>
28
+   <wvobject type="group" fp_name="group135">
29
+      <obj_property name="label">Pipeline</obj_property>
30
+      <obj_property name="DisplayName">label</obj_property>
31
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/CLK">
32
+         <obj_property name="ElementShortName">CLK</obj_property>
33
+         <obj_property name="ObjectShortName">CLK</obj_property>
34
+      </wvobject>
35
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN">
36
+         <obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
37
+         <obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
38
+      </wvobject>
39
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN_Av">
40
+         <obj_property name="ElementShortName">STD_IN_Av</obj_property>
41
+         <obj_property name="ObjectShortName">STD_IN_Av</obj_property>
42
+      </wvobject>
43
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_IN_Request">
44
+         <obj_property name="ElementShortName">STD_IN_Request</obj_property>
45
+         <obj_property name="ObjectShortName">STD_IN_Request</obj_property>
46
+      </wvobject>
47
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT">
48
+         <obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
49
+         <obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
50
+      </wvobject>
51
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT_Av">
52
+         <obj_property name="ElementShortName">STD_OUT_Av</obj_property>
53
+         <obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
54
+      </wvobject>
55
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/STD_OUT_Int">
56
+         <obj_property name="ElementShortName">STD_OUT_Int</obj_property>
57
+         <obj_property name="ObjectShortName">STD_OUT_Int</obj_property>
58
+      </wvobject>
59
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_1">
60
+         <obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
61
+         <obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
62
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
63
+      </wvobject>
64
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_1">
65
+         <obj_property name="ElementShortName">A_from_1[15:0]</obj_property>
66
+         <obj_property name="ObjectShortName">A_from_1[15:0]</obj_property>
67
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
68
+      </wvobject>
69
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_1">
70
+         <obj_property name="ElementShortName">B_from_1[15:0]</obj_property>
71
+         <obj_property name="ObjectShortName">B_from_1[15:0]</obj_property>
72
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
73
+      </wvobject>
74
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/C_from_1">
75
+         <obj_property name="ElementShortName">C_from_1[15:0]</obj_property>
76
+         <obj_property name="ObjectShortName">C_from_1[15:0]</obj_property>
77
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
78
+      </wvobject>
79
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_2">
80
+         <obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
81
+         <obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
82
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
83
+      </wvobject>
84
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_2">
85
+         <obj_property name="ElementShortName">A_from_2[15:0]</obj_property>
86
+         <obj_property name="ObjectShortName">A_from_2[15:0]</obj_property>
87
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
88
+      </wvobject>
89
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_2">
90
+         <obj_property name="ElementShortName">B_from_2[15:0]</obj_property>
91
+         <obj_property name="ObjectShortName">B_from_2[15:0]</obj_property>
92
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
93
+      </wvobject>
94
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/C_from_2">
95
+         <obj_property name="ElementShortName">C_from_2[15:0]</obj_property>
96
+         <obj_property name="ObjectShortName">C_from_2[15:0]</obj_property>
97
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
98
+      </wvobject>
99
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_3">
100
+         <obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
101
+         <obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
102
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
103
+      </wvobject>
104
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_3">
105
+         <obj_property name="ElementShortName">A_from_3[15:0]</obj_property>
106
+         <obj_property name="ObjectShortName">A_from_3[15:0]</obj_property>
107
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
108
+      </wvobject>
109
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_3">
110
+         <obj_property name="ElementShortName">B_from_3[15:0]</obj_property>
111
+         <obj_property name="ObjectShortName">B_from_3[15:0]</obj_property>
112
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
113
+      </wvobject>
114
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/Instruction_from_4">
115
+         <obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
116
+         <obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
117
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
118
+      </wvobject>
119
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/A_from_4">
120
+         <obj_property name="ElementShortName">A_from_4[15:0]</obj_property>
121
+         <obj_property name="ObjectShortName">A_from_4[15:0]</obj_property>
122
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
123
+      </wvobject>
124
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/B_from_4">
125
+         <obj_property name="ElementShortName">B_from_4[15:0]</obj_property>
126
+         <obj_property name="ObjectShortName">B_from_4[15:0]</obj_property>
127
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
128
+      </wvobject>
129
+   </wvobject>
130
+   <wvobject type="group" fp_name="group133">
131
+      <obj_property name="label">Gestion Instructions</obj_property>
132
+      <obj_property name="DisplayName">label</obj_property>
133
+      <obj_property name="isExpanded"></obj_property>
134
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/CLK">
135
+         <obj_property name="ElementShortName">CLK</obj_property>
136
+         <obj_property name="ObjectShortName">CLK</obj_property>
137
+      </wvobject>
138
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Z">
139
+         <obj_property name="ElementShortName">Z</obj_property>
140
+         <obj_property name="ObjectShortName">Z</obj_property>
141
+      </wvobject>
142
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/A">
143
+         <obj_property name="ElementShortName">A[15:0]</obj_property>
144
+         <obj_property name="ObjectShortName">A[15:0]</obj_property>
145
+      </wvobject>
146
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/B">
147
+         <obj_property name="ElementShortName">B[15:0]</obj_property>
148
+         <obj_property name="ObjectShortName">B[15:0]</obj_property>
149
+      </wvobject>
150
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/C">
151
+         <obj_property name="ElementShortName">C[15:0]</obj_property>
152
+         <obj_property name="ObjectShortName">C[15:0]</obj_property>
153
+      </wvobject>
154
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Instruction">
155
+         <obj_property name="ElementShortName">Instruction[4:0]</obj_property>
156
+         <obj_property name="ObjectShortName">Instruction[4:0]</obj_property>
157
+      </wvobject>
158
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Pointeur_instruction">
159
+         <obj_property name="ElementShortName">Pointeur_instruction[8:0]</obj_property>
160
+         <obj_property name="ObjectShortName">Pointeur_instruction[8:0]</obj_property>
161
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
162
+      </wvobject>
163
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Tableau">
164
+         <obj_property name="ElementShortName">Tableau[1:3]</obj_property>
165
+         <obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
166
+      </wvobject>
167
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Adresse_Retour">
168
+         <obj_property name="ElementShortName">Adresse_Retour[8:0]</obj_property>
169
+         <obj_property name="ObjectShortName">Adresse_Retour[8:0]</obj_property>
170
+      </wvobject>
171
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/Compteur_PRI">
172
+         <obj_property name="ElementShortName">Compteur_PRI</obj_property>
173
+         <obj_property name="ObjectShortName">Compteur_PRI</obj_property>
174
+      </wvobject>
175
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/locked">
176
+         <obj_property name="ElementShortName">locked</obj_property>
177
+         <obj_property name="ObjectShortName">locked</obj_property>
178
+      </wvobject>
179
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/compteur">
180
+         <obj_property name="ElementShortName">compteur</obj_property>
181
+         <obj_property name="ObjectShortName">compteur</obj_property>
182
+      </wvobject>
183
+      <wvobject type="other" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage1/bulles">
184
+         <obj_property name="ElementShortName">bulles</obj_property>
185
+         <obj_property name="ObjectShortName">bulles</obj_property>
186
+      </wvobject>
187
+   </wvobject>
188
+   <wvobject type="group" fp_name="group132">
189
+      <obj_property name="label">Registres</obj_property>
190
+      <obj_property name="DisplayName">label</obj_property>
191
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/CLK">
192
+         <obj_property name="ElementShortName">CLK</obj_property>
193
+         <obj_property name="ObjectShortName">CLK</obj_property>
194
+      </wvobject>
195
+      <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/W">
196
+         <obj_property name="ElementShortName">W</obj_property>
197
+         <obj_property name="ObjectShortName">W</obj_property>
198
+      </wvobject>
199
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrA">
200
+         <obj_property name="ElementShortName">AddrA[3:0]</obj_property>
201
+         <obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
202
+      </wvobject>
203
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrB">
204
+         <obj_property name="ElementShortName">AddrB[3:0]</obj_property>
205
+         <obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
206
+      </wvobject>
207
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrC">
208
+         <obj_property name="ElementShortName">AddrC[3:0]</obj_property>
209
+         <obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
210
+      </wvobject>
211
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/AddrW">
212
+         <obj_property name="ElementShortName">AddrW[3:0]</obj_property>
213
+         <obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
214
+      </wvobject>
215
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/DATA">
216
+         <obj_property name="ElementShortName">DATA[15:0]</obj_property>
217
+         <obj_property name="ObjectShortName">DATA[15:0]</obj_property>
218
+      </wvobject>
219
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QA">
220
+         <obj_property name="ElementShortName">QA[15:0]</obj_property>
221
+         <obj_property name="ObjectShortName">QA[15:0]</obj_property>
222
+      </wvobject>
223
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QB">
224
+         <obj_property name="ElementShortName">QB[15:0]</obj_property>
225
+         <obj_property name="ObjectShortName">QB[15:0]</obj_property>
226
+      </wvobject>
227
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/QC">
228
+         <obj_property name="ElementShortName">QC[15:0]</obj_property>
229
+         <obj_property name="ObjectShortName">QC[15:0]</obj_property>
230
+      </wvobject>
231
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage2_5/instance_BancRegistres/REGISTRES">
232
+         <obj_property name="ElementShortName">REGISTRES[255:0]</obj_property>
233
+         <obj_property name="ObjectShortName">REGISTRES[255:0]</obj_property>
234
+      </wvobject>
235
+   </wvobject>
236
+   <wvobject type="group" fp_name="group134">
237
+      <obj_property name="label">Memoire</obj_property>
238
+      <obj_property name="DisplayName">label</obj_property>
239
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/EBP">
240
+         <obj_property name="ElementShortName">EBP[4:0]</obj_property>
241
+         <obj_property name="ObjectShortName">EBP[4:0]</obj_property>
242
+      </wvobject>
243
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/New_EBP">
244
+         <obj_property name="ElementShortName">New_EBP[4:0]</obj_property>
245
+         <obj_property name="ObjectShortName">New_EBP[4:0]</obj_property>
246
+      </wvobject>
247
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/Addr_MemoireDonnees">
248
+         <obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
249
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
250
+      </wvobject>
251
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/IN_Addr_MemoireDonnees">
252
+         <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
253
+         <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
254
+      </wvobject>
255
+      <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/Addr_MemoireDonnees_EBP">
256
+         <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
257
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
258
+      </wvobject>
259
+      <wvobject type="group" fp_name="group197">
260
+         <obj_property name="label">MemoireDonnees</obj_property>
261
+         <obj_property name="DisplayName">label</obj_property>
262
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/MEMORY">
263
+            <obj_property name="ElementShortName">MEMORY[511:0]</obj_property>
264
+            <obj_property name="ObjectShortName">MEMORY[511:0]</obj_property>
265
+         </wvobject>
266
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/D_OUT">
267
+            <obj_property name="ElementShortName">D_OUT[15:0]</obj_property>
268
+            <obj_property name="ObjectShortName">D_OUT[15:0]</obj_property>
269
+         </wvobject>
270
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/Addr">
271
+            <obj_property name="ElementShortName">Addr[4:0]</obj_property>
272
+            <obj_property name="ObjectShortName">Addr[4:0]</obj_property>
273
+         </wvobject>
274
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/RW">
275
+            <obj_property name="ElementShortName">RW</obj_property>
276
+            <obj_property name="ObjectShortName">RW</obj_property>
277
+         </wvobject>
278
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/D_IN">
279
+            <obj_property name="ElementShortName">D_IN[15:0]</obj_property>
280
+            <obj_property name="ObjectShortName">D_IN[15:0]</obj_property>
281
+         </wvobject>
282
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/CALL">
283
+            <obj_property name="ElementShortName">CALL</obj_property>
284
+            <obj_property name="ObjectShortName">CALL</obj_property>
285
+         </wvobject>
286
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/IN_EBP">
287
+            <obj_property name="ElementShortName">IN_EBP[15:0]</obj_property>
288
+            <obj_property name="ObjectShortName">IN_EBP[15:0]</obj_property>
289
+         </wvobject>
290
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
291
+            <obj_property name="ElementShortName">IN_AddrRet[15:0]</obj_property>
292
+            <obj_property name="ObjectShortName">IN_AddrRet[15:0]</obj_property>
293
+         </wvobject>
294
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/RET">
295
+            <obj_property name="ElementShortName">RET</obj_property>
296
+            <obj_property name="ObjectShortName">RET</obj_property>
297
+         </wvobject>
298
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
299
+            <obj_property name="ElementShortName">OUT_EBP[15:0]</obj_property>
300
+            <obj_property name="ObjectShortName">OUT_EBP[15:0]</obj_property>
301
+         </wvobject>
302
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
303
+            <obj_property name="ElementShortName">OUT_AddrRet[15:0]</obj_property>
304
+            <obj_property name="ObjectShortName">OUT_AddrRet[15:0]</obj_property>
305
+         </wvobject>
306
+      </wvobject>
307
+      <wvobject type="group" fp_name="group198">
308
+         <obj_property name="label">MemoireAdressesRetour</obj_property>
309
+         <obj_property name="DisplayName">label</obj_property>
310
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/R">
311
+            <obj_property name="ElementShortName">R</obj_property>
312
+            <obj_property name="ObjectShortName">R</obj_property>
313
+         </wvobject>
314
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/W">
315
+            <obj_property name="ElementShortName">W</obj_property>
316
+            <obj_property name="ObjectShortName">W</obj_property>
317
+         </wvobject>
318
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/D_IN">
319
+            <obj_property name="ElementShortName">D_IN[4:0]</obj_property>
320
+            <obj_property name="ObjectShortName">D_IN[4:0]</obj_property>
321
+         </wvobject>
322
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/D_OUT">
323
+            <obj_property name="ElementShortName">D_OUT[4:0]</obj_property>
324
+            <obj_property name="ObjectShortName">D_OUT[4:0]</obj_property>
325
+         </wvobject>
326
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/MEMORY">
327
+            <obj_property name="ElementShortName">MEMORY[19:0]</obj_property>
328
+            <obj_property name="ObjectShortName">MEMORY[19:0]</obj_property>
329
+         </wvobject>
330
+         <wvobject type="array" fp_name="/TestSystem/instance/instance/instance_securisee/instance_Etage4/instance_MemoireEBP/Addr">
331
+            <obj_property name="ElementShortName">Addr[2:0]</obj_property>
332
+            <obj_property name="ObjectShortName">Addr[2:0]</obj_property>
333
+         </wvobject>
334
+      </wvobject>
335
+   </wvobject>
336
+   <wvobject type="group" fp_name="group136">
337
+      <obj_property name="label">PeripheriqueEcran</obj_property>
338
+      <obj_property name="DisplayName">label</obj_property>
339
+      <wvobject type="group" fp_name="group216">
340
+         <obj_property name="label">VGAControleur</obj_property>
341
+         <obj_property name="DisplayName">label</obj_property>
342
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_RED">
343
+            <obj_property name="ElementShortName">VGA_RED[3:0]</obj_property>
344
+            <obj_property name="ObjectShortName">VGA_RED[3:0]</obj_property>
345
+         </wvobject>
346
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_BLUE">
347
+            <obj_property name="ElementShortName">VGA_BLUE[3:0]</obj_property>
348
+            <obj_property name="ObjectShortName">VGA_BLUE[3:0]</obj_property>
349
+         </wvobject>
350
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_GREEN">
351
+            <obj_property name="ElementShortName">VGA_GREEN[3:0]</obj_property>
352
+            <obj_property name="ObjectShortName">VGA_GREEN[3:0]</obj_property>
353
+         </wvobject>
354
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_HS">
355
+            <obj_property name="ElementShortName">VGA_HS</obj_property>
356
+            <obj_property name="ObjectShortName">VGA_HS</obj_property>
357
+         </wvobject>
358
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_VS">
359
+            <obj_property name="ElementShortName">VGA_VS</obj_property>
360
+            <obj_property name="ObjectShortName">VGA_VS</obj_property>
361
+         </wvobject>
362
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/X">
363
+            <obj_property name="ElementShortName">X</obj_property>
364
+            <obj_property name="ObjectShortName">X</obj_property>
365
+         </wvobject>
366
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/Y">
367
+            <obj_property name="ElementShortName">Y</obj_property>
368
+            <obj_property name="ObjectShortName">Y</obj_property>
369
+         </wvobject>
370
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/PIXEL_ON">
371
+            <obj_property name="ElementShortName">PIXEL_ON</obj_property>
372
+            <obj_property name="ObjectShortName">PIXEL_ON</obj_property>
373
+         </wvobject>
374
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/CLK">
375
+            <obj_property name="ElementShortName">CLK</obj_property>
376
+            <obj_property name="ObjectShortName">CLK</obj_property>
377
+         </wvobject>
378
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/active">
379
+            <obj_property name="ElementShortName">active</obj_property>
380
+            <obj_property name="ObjectShortName">active</obj_property>
381
+         </wvobject>
382
+      </wvobject>
383
+      <wvobject type="group" fp_name="group217">
384
+         <obj_property name="label">Ecran</obj_property>
385
+         <obj_property name="DisplayName">label</obj_property>
386
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CLK">
387
+            <obj_property name="ElementShortName">CLK</obj_property>
388
+            <obj_property name="ObjectShortName">CLK</obj_property>
389
+         </wvobject>
390
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_Av">
391
+            <obj_property name="ElementShortName">Data_Av</obj_property>
392
+            <obj_property name="ObjectShortName">Data_Av</obj_property>
393
+         </wvobject>
394
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_IN">
395
+            <obj_property name="ElementShortName">Data_IN[0:6]</obj_property>
396
+            <obj_property name="ObjectShortName">Data_IN[0:6]</obj_property>
397
+         </wvobject>
398
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/X">
399
+            <obj_property name="ElementShortName">X</obj_property>
400
+            <obj_property name="ObjectShortName">X</obj_property>
401
+         </wvobject>
402
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Y">
403
+            <obj_property name="ElementShortName">Y</obj_property>
404
+            <obj_property name="ObjectShortName">Y</obj_property>
405
+         </wvobject>
406
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/OUT_ON">
407
+            <obj_property name="ElementShortName">OUT_ON</obj_property>
408
+            <obj_property name="ObjectShortName">OUT_ON</obj_property>
409
+         </wvobject>
410
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Ecran">
411
+            <obj_property name="ElementShortName">Ecran[0:2239]</obj_property>
412
+            <obj_property name="ObjectShortName">Ecran[0:2239]</obj_property>
413
+         </wvobject>
414
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/L">
415
+            <obj_property name="ElementShortName">L[0:6]</obj_property>
416
+            <obj_property name="ObjectShortName">L[0:6]</obj_property>
417
+         </wvobject>
418
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/C">
419
+            <obj_property name="ElementShortName">C[0:6]</obj_property>
420
+            <obj_property name="ObjectShortName">C[0:6]</obj_property>
421
+         </wvobject>
422
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/InitialL">
423
+            <obj_property name="ElementShortName">InitialL[0:6]</obj_property>
424
+            <obj_property name="ObjectShortName">InitialL[0:6]</obj_property>
425
+         </wvobject>
426
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Full">
427
+            <obj_property name="ElementShortName">Full</obj_property>
428
+            <obj_property name="ObjectShortName">Full</obj_property>
429
+         </wvobject>
430
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement">
431
+            <obj_property name="ElementShortName">point_dereferencement</obj_property>
432
+            <obj_property name="ObjectShortName">point_dereferencement</obj_property>
433
+         </wvobject>
434
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement_ecriture">
435
+            <obj_property name="ElementShortName">point_dereferencement_ecriture</obj_property>
436
+            <obj_property name="ObjectShortName">point_dereferencement_ecriture</obj_property>
437
+         </wvobject>
438
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentCodeASCII">
439
+            <obj_property name="ElementShortName">CurrentCodeASCII[0:6]</obj_property>
440
+            <obj_property name="ObjectShortName">CurrentCodeASCII[0:6]</obj_property>
441
+         </wvobject>
442
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentFont">
443
+            <obj_property name="ElementShortName">CurrentFont[0:63]</obj_property>
444
+            <obj_property name="ObjectShortName">CurrentFont[0:63]</obj_property>
445
+         </wvobject>
446
+      </wvobject>
447
+      <wvobject type="group" fp_name="group218">
448
+         <obj_property name="label">ScreenDriver</obj_property>
449
+         <obj_property name="DisplayName">label</obj_property>
450
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/CLK">
451
+            <obj_property name="ElementShortName">CLK</obj_property>
452
+            <obj_property name="ObjectShortName">CLK</obj_property>
453
+         </wvobject>
454
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/Value">
455
+            <obj_property name="ElementShortName">Value[15:0]</obj_property>
456
+            <obj_property name="ObjectShortName">Value[15:0]</obj_property>
457
+         </wvobject>
458
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/ValueAv">
459
+            <obj_property name="ElementShortName">ValueAv</obj_property>
460
+            <obj_property name="ObjectShortName">ValueAv</obj_property>
461
+         </wvobject>
462
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/IsInt">
463
+            <obj_property name="ElementShortName">IsInt</obj_property>
464
+            <obj_property name="ObjectShortName">IsInt</obj_property>
465
+         </wvobject>
466
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutData">
467
+            <obj_property name="ElementShortName">OutData[0:6]</obj_property>
468
+            <obj_property name="ObjectShortName">OutData[0:6]</obj_property>
469
+         </wvobject>
470
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutDataAv">
471
+            <obj_property name="ElementShortName">OutDataAv</obj_property>
472
+            <obj_property name="ObjectShortName">OutDataAv</obj_property>
473
+         </wvobject>
474
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/intern_value">
475
+            <obj_property name="ElementShortName">intern_value[15:0]</obj_property>
476
+            <obj_property name="ObjectShortName">intern_value[15:0]</obj_property>
477
+         </wvobject>
478
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/current_hexa">
479
+            <obj_property name="ElementShortName">current_hexa[3:0]</obj_property>
480
+            <obj_property name="ObjectShortName">current_hexa[3:0]</obj_property>
481
+         </wvobject>
482
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/compteur">
483
+            <obj_property name="ElementShortName">compteur</obj_property>
484
+            <obj_property name="ObjectShortName">compteur</obj_property>
485
+         </wvobject>
486
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/work_in_progess">
487
+            <obj_property name="ElementShortName">work_in_progess</obj_property>
488
+            <obj_property name="ObjectShortName">work_in_progess</obj_property>
489
+         </wvobject>
490
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/x_to_send">
491
+            <obj_property name="ElementShortName">x_to_send</obj_property>
492
+            <obj_property name="ObjectShortName">x_to_send</obj_property>
493
+         </wvobject>
494
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/first_detected">
495
+            <obj_property name="ElementShortName">first_detected</obj_property>
496
+            <obj_property name="ObjectShortName">first_detected</obj_property>
497
+         </wvobject>
498
+      </wvobject>
499
+   </wvobject>
500
+   <wvobject type="group" fp_name="group159">
501
+      <obj_property name="label">Peripherique Clavier</obj_property>
502
+      <obj_property name="DisplayName">label</obj_property>
503
+      <wvobject type="group" fp_name="group160">
504
+         <obj_property name="label">Keyboard</obj_property>
505
+         <obj_property name="DisplayName">label</obj_property>
506
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/CLK">
507
+            <obj_property name="ElementShortName">CLK</obj_property>
508
+            <obj_property name="ObjectShortName">CLK</obj_property>
509
+         </wvobject>
510
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Clk">
511
+            <obj_property name="ElementShortName">PS2Clk</obj_property>
512
+            <obj_property name="ObjectShortName">PS2Clk</obj_property>
513
+         </wvobject>
514
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Data">
515
+            <obj_property name="ElementShortName">PS2Data</obj_property>
516
+            <obj_property name="ObjectShortName">PS2Data</obj_property>
517
+         </wvobject>
518
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_read">
519
+            <obj_property name="ElementShortName">Data_read</obj_property>
520
+            <obj_property name="ObjectShortName">Data_read</obj_property>
521
+         </wvobject>
522
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_av">
523
+            <obj_property name="ElementShortName">Data_av</obj_property>
524
+            <obj_property name="ObjectShortName">Data_av</obj_property>
525
+         </wvobject>
526
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data">
527
+            <obj_property name="ElementShortName">Data[0:6]</obj_property>
528
+            <obj_property name="ObjectShortName">Data[0:6]</obj_property>
529
+         </wvobject>
530
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/alert">
531
+            <obj_property name="ElementShortName">alert</obj_property>
532
+            <obj_property name="ObjectShortName">alert</obj_property>
533
+         </wvobject>
534
+      </wvobject>
535
+      <wvobject type="group" fp_name="group161">
536
+         <obj_property name="label">KeyboardDriver</obj_property>
537
+         <obj_property name="DisplayName">label</obj_property>
538
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/CLK">
539
+            <obj_property name="ElementShortName">CLK</obj_property>
540
+            <obj_property name="ObjectShortName">CLK</obj_property>
541
+         </wvobject>
542
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_read">
543
+            <obj_property name="ElementShortName">Data_read</obj_property>
544
+            <obj_property name="ObjectShortName">Data_read</obj_property>
545
+         </wvobject>
546
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_av">
547
+            <obj_property name="ElementShortName">Data_av</obj_property>
548
+            <obj_property name="ObjectShortName">Data_av</obj_property>
549
+         </wvobject>
550
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data">
551
+            <obj_property name="ElementShortName">Data[0:6]</obj_property>
552
+            <obj_property name="ObjectShortName">Data[0:6]</obj_property>
553
+         </wvobject>
554
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN">
555
+            <obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
556
+            <obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
557
+         </wvobject>
558
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Av">
559
+            <obj_property name="ElementShortName">STD_IN_Av</obj_property>
560
+            <obj_property name="ObjectShortName">STD_IN_Av</obj_property>
561
+         </wvobject>
562
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Request">
563
+            <obj_property name="ElementShortName">STD_IN_Request</obj_property>
564
+            <obj_property name="ObjectShortName">STD_IN_Request</obj_property>
565
+         </wvobject>
566
+         <wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT">
567
+            <obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
568
+            <obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
569
+            <obj_property name="Radix">HEXRADIX</obj_property>
570
+         </wvobject>
571
+         <wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT_Av">
572
+            <obj_property name="ElementShortName">STD_OUT_Av</obj_property>
573
+            <obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
574
+         </wvobject>
575
+         <wvobject type="other" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/intern_value">
576
+            <obj_property name="ElementShortName">intern_value</obj_property>
577
+            <obj_property name="ObjectShortName">intern_value</obj_property>
578
+         </wvobject>
579
+      </wvobject>
580
+   </wvobject>
581
+</wave_config>

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