From 8b1dc18f3a1b93b760b560bca2c3e54a53de6ca0 Mon Sep 17 00:00:00 2001 From: Faure Paul Date: Tue, 13 Jul 2021 17:26:44 +0200 Subject: [PATCH] =?UTF-8?q?Ajout=20module=20ecran=20et=20clavier=20au=20pr?= =?UTF-8?q?ocesseur=20(TAF=20:=20version=20non=20s=C3=A9cu,=20Tester)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../digilent-xdc-master/Basys-3-Master.xdc | 4 +- .../sim_1/new/TestScreenDriver.vhd | 87 +++ Processeur.srcs/sim_1/new/TestSystem.vhd | 90 +++ Processeur.srcs/sources_1/new/Ecran.vhd | 4 +- .../new/Etage1_LectureInstruction.vhd | 46 +- .../sources_1/new/Etage2-5_Registres.vhd | 40 +- .../sources_1/new/Etage4_Memoire.vhd | 34 +- Processeur.srcs/sources_1/new/IntToASCII.vhd | 0 .../sources_1/new/KeyboardDriver.vhd | 86 +++ .../sources_1/new/MemoireInstructions.vhd | 2 +- .../sources_1/new/PeripheriqueClavier.vhd | 107 ++++ .../sources_1/new/PeripheriqueEcran.vhd | 150 +++++ Processeur.srcs/sources_1/new/Pipeline.vhd | 154 +++-- .../sources_1/new/ScreenDriver.vhd | 142 +++++ Processeur.srcs/sources_1/new/System.vhd | 129 +++- Processeur.xpr | 54 +- SimulationsConfig/TestSystem_behav.wcfg | 581 ++++++++++++++++++ 17 files changed, 1588 insertions(+), 122 deletions(-) create mode 100644 Processeur.srcs/sim_1/new/TestScreenDriver.vhd create mode 100644 Processeur.srcs/sim_1/new/TestSystem.vhd create mode 100644 Processeur.srcs/sources_1/new/IntToASCII.vhd create mode 100644 Processeur.srcs/sources_1/new/KeyboardDriver.vhd create mode 100644 Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd create mode 100644 Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd create mode 100644 Processeur.srcs/sources_1/new/ScreenDriver.vhd create mode 100644 SimulationsConfig/TestSystem_behav.wcfg diff --git a/Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc b/Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc index 8434483..9be331d 100644 --- a/Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc +++ b/Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc @@ -108,8 +108,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK ##Buttons -#set_property PACKAGE_PIN U18 [get_ports btnC] -# set_property IOSTANDARD LVCMOS33 [get_ports btnC] +set_property PACKAGE_PIN U18 [get_ports btnC] + set_property IOSTANDARD LVCMOS33 [get_ports btnC] ##set_property PACKAGE_PIN T18 [get_ports btnU] # #set_property IOSTANDARD LVCMOS33 [get_ports btnU] #set_property PACKAGE_PIN W19 [get_ports btnL] diff --git a/Processeur.srcs/sim_1/new/TestScreenDriver.vhd b/Processeur.srcs/sim_1/new/TestScreenDriver.vhd new file mode 100644 index 0000000..d6e3f1e --- /dev/null +++ b/Processeur.srcs/sim_1/new/TestScreenDriver.vhd @@ -0,0 +1,87 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.07.2021 11:39:21 +-- Design Name: +-- Module Name: TestScreenDriver - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TestScreenDriver is +-- Port ( ); +end TestScreenDriver; + +architecture Behavioral of TestScreenDriver is + + component ScreenDriver + Generic ( Nb_bits : Natural + ); + Port ( CLK : in STD_LOGIC; + Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + ValueAv : in STD_LOGIC; + IsInt : in STD_LOGIC; + OutData : out STD_LOGIC_VECTOR (0 to 6); + OutDataAv : out STD_LOGIC); + end component; + + signal CLK : STD_LOGIC := '0'; + signal Value : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); + signal ValueAv : STD_LOGIC := '0'; + signal IsInt : STD_LOGIC := '0'; + signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0'); + signal OutDataAv : STD_LOGIC := '0'; + + constant CLK_period : time := 10 ns; + +begin + + instance : ScreenDriver + Generic map ( Nb_bits => 16) + Port map ( CLK => CLK , + Value => Value , + ValueAv => ValueAv , + IsInt => IsInt , + OutData => OutData , + OutDataAv => OutDataAv ); + + CLK_process : process + begin + CLK <= '1'; + wait for CLK_period/2; + CLK <= '0'; + wait for CLK_period/2; + end process; + + process + begin + Value <= "0000000001010101" after 10 ns, "11111111111111111" after 80 ns; + ValueAv <= '1' after 10 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns; + IsInt <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns; + wait; + end process; + +end Behavioral; diff --git a/Processeur.srcs/sim_1/new/TestSystem.vhd b/Processeur.srcs/sim_1/new/TestSystem.vhd new file mode 100644 index 0000000..91c7dcb --- /dev/null +++ b/Processeur.srcs/sim_1/new/TestSystem.vhd @@ -0,0 +1,90 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12.07.2021 08:34:17 +-- Design Name: +-- Module Name: TestSystem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TestSystem is +-- Port ( ); +end TestSystem; + +architecture Behavioral of TestSystem is + + component System is + Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + btnC : in STD_LOGIC; + CLK : STD_LOGIC); + end component; + + signal CLK : STD_LOGIC := '0'; + signal btnC : STD_LOGIC := '0'; + signal PS2Clk : STD_LOGIC := '0'; + signal PS2Data : STD_LOGIC := '0'; + signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); + signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); + signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); + signal Hsync : STD_LOGIC := '0'; + signal Vsync : STD_LOGIC := '0'; + + constant CLK_period : time := 10 ns; + +begin + instance : System + port map (vgaRed => vgaRed, + vgaBlue => vgaBlue, + vgaGreen => vgaGreen, + Hsync => Hsync, + Vsync => Vsync, + PS2Clk => PS2Clk, + PS2Data => PS2Data, + btnC => btnC, + CLK => CLK); + + CLK_process :process + begin + CLK <= '1'; + wait for CLK_period/2; + CLK <= '0'; + wait for CLK_period/2; + end process; + + process + begin + PS2Clk <= '1' after 3200 us, '0' after 3250 us, '1' after 3300 us, '0' after 3350 us, '1' after 3400 us, '0' after 3450 us, '1' after 3500 us, '0' after 3550 us, '1' after 3600 us, '0' after 3650 us, '1' after 3700 us, '0' after 3750 us, '1' after 3800 us, '0' after 3850 us, '1' after 3900 us, '0' after 3950 us, '1' after 4000 us, '0' after 4050 us, '1' after 4100 us, '0' after 4150 us, '1' after 4200 us, '0' after 4250 us, '1' after 5000 us, '0' after 5050 us, '1' after 5100 us, '0' after 5150 us, '1' after 5200 us, '0' after 5250 us, '1' after 5300 us, '0' after 5350 us, '1' after 5400 us, '0' after 5450 us, '1' after 5500 us, '0' after 5550 us, '1' after 5600 us, '0' after 5650 us, '1' after 5700 us, '0' after 5750 us, '1' after 5800 us, '0' after 5850 us, '1' after 5900 us, '0' after 5950 us, '1' after 6000 us, '0' after 6050 us; + PS2Data <= '0' after 3200 us, '1' after 3300 us, '0' after 3400 us, '1' after 3500 us, '0' after 3600 us, '1' after 3700 us, '1' after 3800 us, '1' after 3900 us, '0' after 4000 us, '0' after 4100 us, '1' after 4200 us, '0' after 4300 us, '0' after 5000 us, '0' after 5100 us, '1' after 5200 us, '0' after 5300 us, '1' after 5400 us, '1' after 5500 us, '0' after 5600 us, '1' after 5700 us, '0' after 5800 us, '1' after 5900 us, '1' after 6000 us, '0' after 6100 us; + wait; + end process; +end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Ecran.vhd b/Processeur.srcs/sources_1/new/Ecran.vhd index b9a2e5e..2f4934c 100644 --- a/Processeur.srcs/sources_1/new/Ecran.vhd +++ b/Processeur.srcs/sources_1/new/Ecran.vhd @@ -46,7 +46,7 @@ architecture Behavioral of Ecran is end component; constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000"; - constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001101"; + constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001010"; constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111"; signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); --(0 => '1', 1 => '0', 2 => '0', 3 => '1', 4 => '0', 5 => '0', 6 => '0', others => '0'); @@ -125,7 +125,7 @@ begin point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht))); point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C))); - CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y/Display_CaracterHeight < L_Blocks and X/Display_CaracterWidht < C_Blocks and RST='1') else + CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y < screen_height and X < screen_width and RST='1') else "0000000"; OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width)); diff --git a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd index 558c594..8b86aea 100644 --- a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd +++ b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd @@ -50,14 +50,17 @@ -- Instructions_critiques_lecture_C(5) = '0' --> AFC ne lit pas dans le registre de l'opérande C -- Instructions_critiques_ecriture(5) = '1' --> AFC ecrit dans le registre de l'opérande A - Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP - Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ - Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL - Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET - Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP + Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP + Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ + Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI + Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC + Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL + Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET + Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP Port ( CLK : in STD_LOGIC; -- Clock RST : in STD_LOGIC; -- Reset Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ) + STD_IN_Request : in STD_LOGIC; A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C @@ -117,6 +120,9 @@ -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k signal compteur : integer := 0; + -- Compteur de protection des collisions entre les prints + signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0; + -- Signal d'arret (STOP 0) signal locked : boolean := false; @@ -153,16 +159,20 @@ Tableau <= (others => -1); Pointeur_Instruction <= (others => '0'); compteur <= 0; + Compteur_PRI <= 0; locked <= false; C <= Argument_nul; B <= Argument_nul; A <= Argument_nul; Instruction <= Instruction_nulle; - else + elsif (STD_IN_Request = '0') then -- Avancement des instructions en écritures dans le pipeline Tableau(3) <= Tableau(2); Tableau(2) <= Tableau(1); Tableau(1) <= -1; + if (Compteur_PRI > 0) then + Compteur_PRI <= Compteur_PRI - 1; + end if; if (not bulles) then -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if) if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then @@ -212,6 +222,14 @@ B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); + elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then + -- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions + Compteur_PRI <= Nb_bits/4 + 1; + C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); + B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); + A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); + Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); + Pointeur_Instruction <= Pointeur_Instruction + 1; else -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); @@ -276,12 +294,24 @@ or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3)) ) + ) + or + ( + ( + (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) + or + (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC) + ) + and + ( + not (Compteur_PRI = 0) + ) ); -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour - R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else + R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET and STD_IN_Request = '0' else '0'; - W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else + W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL and STD_IN_Request = '0' else '0'; diff --git a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd index 881c723..3f6d85b 100644 --- a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd +++ b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd @@ -29,12 +29,17 @@ entity Etage2_5_Registres is Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd) Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd) Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd) - Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI - Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET + Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI + Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC + Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET Port ( CLK : in STD_LOGIC; -- Clock RST : in STD_LOGIC; -- Reset STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC; IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2 IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2 IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2 @@ -95,7 +100,7 @@ architecture Behavioral of Etage2_5_Registres is signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); + begin instance_LC : LC @@ -147,22 +152,19 @@ begin intern_OUT_2_C; OUT_2_Instruction <= (others => '0') when RST = '0' else IN_2_Instruction; - - -- Gestion de STD_OU (peut être améliorée) - process - begin - -- Synchronisation sur la clock - wait until CLK'event and CLK = '1'; - if (RST = '0') then - intern_STD_OUT <= (others => '0'); - else - if (IN_2_Instruction = Code_Instruction_PRI) then - intern_STD_OUT <= intern_OUT_2_A; - end if; - end if; - end process; - STD_OUT <= intern_STD_OUT when RST = '1' else - (others => '0'); + + STD_OUT <= (others => '0') when RST = '0' else + intern_OUT_2_A; + STD_OUT_Av <= '0' when RST = '0' else + '1' when IN_2_Instruction = Code_Instruction_PRI or IN_2_Instruction = Code_Instruction_PRIC else + '0'; + STD_OUT_Int <= '0' when RST = '0' else + '1' when IN_2_Instruction = Code_Instruction_PRI else + '0'; + + STD_IN_Request <= '0' when RST = '0' else + '1' when IN_5_Instruction = Code_Instruction_GET and STD_IN_Av = '0' else + '0'; diff --git a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd index f15aab7..1720e61 100644 --- a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd +++ b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd @@ -49,15 +49,21 @@ architecture Structural of Etage4_Memoire is component MemoireDonnees is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Mem_size : Natural); - Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - RW : in STD_LOGIC; - D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - RST : in STD_LOGIC; - CLK : in STD_LOGIC; - D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); + Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire + Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire + Mem_size : Natural); -- Nombre de mot stockables + Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir + RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write) + D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0) + CALL : in STD_LOGIC; -- '1' -> CALL en cours + IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL + IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL + RET : in STD_LOGIC; -- '1' -> RET en cours + OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET + OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET + RST : in STD_LOGIC; -- Reset + CLK : in STD_LOGIC; -- Clock + D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire end component; component MemoireAdressesRetour is @@ -112,6 +118,10 @@ signal E : STD_LOGIC; signal F : STD_LOGIC; + -- Signaux inutiles + signal OUT_EBP : STD_LOGIC_VECTOR (Nb_bits-1 downto 0); + signal OUT_AddrRet : STD_LOGIC_VECTOR (Nb_bits-1 downto 0); + begin instance_LC : LC -- Link controleur sur la mémoire de donnees @@ -155,6 +165,12 @@ port map ( Addr => Addr_MemoireDonnees, RW => Commande_MemoireDonnees(0), D_IN => IN_B, + CALL => '0', + IN_EBP => (others => '0'), + IN_AddrRet => (others => '0'), + RET => '0', + OUT_EBP => OUT_EBP, + OUT_AddrRet => OUT_AddrRet, RST => RST, CLK => CLK, D_OUT => Sortie_MemoireDonnees); diff --git a/Processeur.srcs/sources_1/new/IntToASCII.vhd b/Processeur.srcs/sources_1/new/IntToASCII.vhd new file mode 100644 index 0000000..e69de29 diff --git a/Processeur.srcs/sources_1/new/KeyboardDriver.vhd b/Processeur.srcs/sources_1/new/KeyboardDriver.vhd new file mode 100644 index 0000000..3a9d3cf --- /dev/null +++ b/Processeur.srcs/sources_1/new/KeyboardDriver.vhd @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13.07.2021 09:30:08 +-- Design Name: +-- Module Name: KeyboardDriver - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity KeyboardDriver is + Generic (Nb_Bits : Natural); + Port (CLK : in STD_LOGIC; + Data_read : out STD_LOGIC; + Data_av : in STD_LOGIC; + Data : in STD_LOGIC_VECTOR (0 to 6); + STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_IN_Av : out STD_LOGIC; + STD_IN_Request : in STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC); +end KeyboardDriver; + +architecture Behavioral of KeyboardDriver is + + signal intern_value : Natural := 0; + signal work_in_progress : BOOLEAN := false; + signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0'); + + +begin + + process + begin + wait until CLK'event and CLK = '1'; + STD_IN_Av <= '0'; + STD_OUT_Av <= '0'; + if not(work_in_progress) then + intern_value <= 0; + end if; + if STD_IN_Request = '1' then + work_in_progress <= true; + if Data_av = '1' then + STD_OUT <= Zeros & Data; + STD_OUT_Av <= '1'; + if (Data = "1111111") then + intern_value <= intern_value / 10; + elsif (Data = "0001101") then + STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits)); + STD_IN_Av <= '1'; + work_in_progress <= false; + elsif (Data >= "0110000" and Data <= "0111001") then + intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6))); + end if; + end if; + end if; + end process; + + Data_read <= '0' when STD_IN_Request = '0' else Data_av; + +end Behavioral; diff --git a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd index c525a7a..dbc5950 100644 --- a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd +++ b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd @@ -32,7 +32,7 @@ end MemoireInstructions; architecture Behavioral of MemoireInstructions is -- Do not touch until (-- Skadoosh) -- Do not add any Skadoosh - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010100000000000000000000000010001000000010000000000000000010000000000100000000000000000101000000000000000000000000010011010000100000001000000000100110000000100000010000000000101100000001000000010000000001011000000000000000000000000010010000000100000000000000000100100000000000000000000000010100000000000000000000000000010110000001100000011000000000101100000010000000100000000001011000000010000000100000000010110000000000000000000000000111101000100000000000000000001000000000010000001000000000000010000001000000010000000110100100000011000000010000000001000000000100000000100000000010000000000000000010000000000001000000010000000100000001101001000000110000001000000000010000000001000000000000000001010100010100000000000000000010001000000100000000000000000010000000001000000000000000001000001010110000000000000000000011000001000000010000000010010010000010000000000000000000010100000010000000100000001101001000000110000100000000000010000000001000000001000000000100100000001000000000000000001001000000000000000100000000101000000000000000000000000000101100000000000000000000000001111001101010000000000000000101010000101000000000000000001000100000000000000000000000001001000000000000000000000000101010000101000000000000000001000100000000000000000000000001001000000001111111100000000100000100000000000000000000000001100000001000000010000000001001000000010000000000000000010010000000000000001000000001010000000000000000000000000001011000010010000100100000000010110000100000001000000000000101100000111000010100000000001011000001100000011000000000010110000010100000101000000000101100000100000001000000000001011000000110000001100000000010110000001000000010000000000101100000001000000010000000001011000000000000000000000000011110001010000000000000000000100000000110000010100000000000001000010100000101000001000010010000100000000001000000000100000001010000001100000000001101000010100000100000000000010000000100000000101000000000000100001010000010100000100001010000010100000011100000000000100000100000001001000010000100100001001000000010000000000011000010000000100000001001010000000100100000110000000000100100001000000001010000000001110000001110000100100000000010010000100100000000000000001000000101010000000000000000000011000010010000100100000111010010000100100000000000000000010100000111000001110000100001001000010000000100000000000010000000011100000110000000000100100000110000000010000000010010000001010000000000000000101011100100000000000000000001000100000101000000000000000001001000001010000000000000000101010001010000000000000000001000100000101000000000000000001001000001011111111100000000101010001010000000000000000001000100000101000000000000000001001000001010000000000000000101010001010000000000000000001000100000101000000000000000001001000001011111111100000000010010000010000000000000000000100100000011000000000000000001001000000100000000000000000010010000000100000000000000000100100000000000000000000000001111010110110000000000000000"; + signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101100000000000000000000000000000000000000000000000001000100000000000000010000000000000000000000000000000001000000000000000000100000000000000000000000000000000010100000000000000000000000000000000000000000000000001010000000000111001010000000000000010000000000000000010100000000000000000100000000000000100000000000000000010110000000000010100000000000000010000000000000000000101100000000000100110000000000000011000000000000000001011000000000001001000000000000000100000000000000000010110000000000010001000000000000000100000000000000000101100000000000100000000000000000000000000000000000001011000000000000111100000000000011110000000000000000010110000000000001110000000000000111000000000000000000101100000000000011010000000000001101000000000000000001011000000000000110000000000000011000000000000000000010110000000000001011000000000000101100000000000000000101100000000000010100000000000001010000000000000000001011000000000000100100000000000010010000000000000000010110000000000001000000000000000100000000000000000000101100000000000001110000000000000111000000000000000001011000000000000000100000000000001100000000000000000010110000000000000000000000000000010100000000000000000100100000000000001100000000000000000000000000000000001011000000000000011000000000000001100000000000000000010010000000000000101000000000000000000000000000000000101100000000000001010000000000000101000000000000000010010000000000000010000000000000000000000000000000000010010000000000000100000000000000101000000000000000000101100000000000001000000000000000100000000000000000010010000000000000001100000000000000000000000000000000100100000000000000010000000000000000000000000000000001001000000000000000010000000000000000000000000000000010010000000000000000000000000000000000000000000000000010010000000000000011000000000110010100000000000000000101100000000000000110000000000000011000000000000000001001000000000000001000000000011011010000000000000000010110000000000000010000000000000001000000000000000000100100000000000000010000000001101101000000000000000001011000000000000000100000000000000010000000000000000010010000000000000000000000000110000100000000000000000101100000000000000000000000000000000000000000000000010010000000000000111100000000000000000000000000000000100100000000000001110000000000000000000000000000000001001000000000000011010000000000000000000000000000000010010000000000000110000000000000000000000000000000000010010000000000001111000000000111001000000000000000000100100000000000011100000000001100111000000000000000001001000000000000110100000000011011110000000000000000010010000000000001100000000000111001000000000000000001001000000000000010110000000000000000000000000000000010010000000000000101000000000000000000000000000000000100100000000000001001000000000000000000000000000000001001000000000000010000000000000000000000000000000000001001000000000000101100000000011100000000000000000000010010000000000001010000000000010000000000000000000000100100000000000010010000000001101110000000000000000001001000000000000100000000000011101010000000000000000100100000000000000111000000000000000000000000000000001001000000000000001100000000000000000000000000000000010010000000000000010100000000000000000000000000000000100100000000000000100000000000000000000000000000000000100100000000000001110000000000100111000000000000000001001000000000000011000000000011001000000000000000000010010000000000000101000000000010000000000000000000000100100000000000001000000000001110100000000000000000010010000000000000001100000000000000000000000000000000100100000000000000010000000000000000000000000000000001001000000000000000010000000000000000000000000000000010010000000000000000000000000000000000000000000000000010010000000000000011000000000111010100000000000000000100100000000000000100000000001100010000000000000000001001000000000000000100000000011001010000000000000000010010000000000000000000000000100010000000000000000001010100000000000000000000000000000000000000000000000001011000000000001000100000000000000010000000000000000010110000000000010000000000000000000000000000000000000101100000000000011110000000000001111000000000000000001011000000000000111000000000000011100000000000000000010110000000000001101000000000000110100000000000000000101100000000000011000000000000001100000000000000000001011000000000000101100000000000010110000000000000000010110000000000001010000000000000101000000000000000000101100000000000010010000000000001001000000000000000001011000000000000100000000000000010000000000000000000010110000000000000111000000000000011100000000000000000101100000000000001100000000000000110000000000000000001011000000000000010100000000000001010000000000000000010110000000000000100000000000000010000000000000000000101100000000000000110000000000000011000000000000000001011000000000000001000000000000000100000000000000000100100000000000000001000000000000000000000000000000001001000000000000000000000000000000000000000000000000001001000000000000000100000000000010100000000000000000010110000000000000001000000000000000100000000000000000100100000000000000000000000001100101000000000000000001011000000000000000000000000000000000000000000000000100100000000000001111000000000000000000000000000000001001000000000000011100000000000000000000000000000000010010000000000000110100000000000000000000000000000000100100000000000001100000000000000000000000000000000000100100000000000011110000000001101101000000000000000001001000000000000111000000000011010010000000000000000010010000000000001101000000000111010000000000000000000100100000000000011000000000001101001000000000000000010010000000000000101100000000000000000000000000000000100100000000000001010000000000000000000000000000000001001000000000000010010000000000000000000000000000000010010000000000000100000000000000000000000000000000000010010000000000001011000000000110011100000000000000000100100000000000010100000000001100101000000000000000001001000000000000100100000000011011000000000000000000010010000000000001000000000000010000000000000000000001001000000000000001110000000000000000000000000000000010010000000000000011000000000000000000000000000000000100100000000000000101000000000000000000000000000000001001000000000000001000000000000000000000000000000000001001000000000000011100000000011011100000000000000000010010000000000000110000000000110111100000000000000000100100000000000001010000000001101001000000000000000001001000000000000010000000000011101000000000000000000100100000000000000011000000000000000000000000000000001001000000000000000100000000000000000000000000000000010010000000000000000100000000000000000000000000000000100100000000000000000000000000000000000000000000000000100100000000000000110000000001100011000000000000000001001000000000000001000000000011011100000000000000000010010000000000000001000000000110111100000000000000000100100000000000000000000000001000110000000000000000010101000000000000000000000000000000000000000000000000010110000000000010100000000000000010000000000000000000101100000000000100110000000000000011000000000000000001011000000000001001000000000000000100000000000000000010110000000000010001000000000000000100000000000000000101100000000000100000000000000000000000000000000000001011000000000000111100000000000011110000000000000000010110000000000001110000000000000111000000000000000000101100000000000011010000000000001101000000000000000001011000000000000110000000000000011000000000000000000010110000000000001011000000000000101100000000000000000101100000000000010100000000000001010000000000000000001011000000000000100100000000000010010000000000000000010110000000000001000000000000000100000000000000000000101100000000000001110000000000000111000000000000000001011000000000000011000000000000001100000000000000000010110000000000000101000000000000010100000000000000001001000000000000001000000000000000000000000000000000001001000000000000010000000000000010100000000000000000010110000000000000100000000000000010000000000000000001001000000000000000110000000000000000000000000000000010010000000000000001000000000000000000000000000000000100100000000000000001000000000000000000000000000000001001000000000000000000000000000000000000000000000000001001000000000000001100000000010001000000000000000000010110000000000000011000000000000001100000000000000000100100000000000000100000000001000101000000000000000001011000000000000001000000000000000100000000000000000010010000000000000001000000000100101100000000000000000101100000000000000010000000000000001000000000000000001001000000000000000000000000010000110000000000000000010110000000000000000000000000000000000000000000000001001000000000000011110000000000000000000000000000000010010000000000000111000000000000000000000000000000000100100000000000001101000000000000000000000000000000001001000000000000011000000000000000000000000000000000001001000000000000111100000000010000010000000000000000010010000000000001110000000000100100000000000000000000100100000000000011010000000000100000000000000000000001001000000000000110000000000010011100000000000000000100100000000000001011000000000000000000000000000000001001000000000000010100000000000000000000000000000000010010000000000000100100000000000000000000000000000000100100000000000001000000000000000000000000000000000000100100000000000010110000000001000101000000000000000001001000000000000101000000000010001010000000000000000010010000000000001001000000000100001000000000000000000100100000000000010000000000000100000000000000000000010010000000000000011100000000000000000000000000000000100100000000000000110000000000000000000000000000000001001000000000000001010000000000000000000000000000000010010000000000000010000000000000000000000000000000000010010000000000000111000000000100010100000000000000000100100000000000001100000000001010110000000000000000001001000000000000010100000000010000010000000000000000010010000000000000100000000000100100000000000000000001001000000000000000110000000000000000000000000000000010010000000000000001000000000000000000000000000000000100100000000000000001000000000000000000000000000000001001000000000000000000000000000000000000000000000000001001000000000000001100000000001000000000000000000000010010000000000000010000000000101010100000000000000000100100000000000000010000000001001111000000000000000001001000000000000000000000000010110010000000000000000101010000000000000000000000000000000000000000000000000101100000000000111110000000000001111000000000000000001011000000000001111000000000000011100000000000000000010110000000000011101000000000000110100000000000000000101100000000000111000000000000001100000000000000000001011000000000001101100000000000010110000000000000000010110000000000011010000000000000101000000000000000000101100000000000110010000000000001001000000000000000001011000000000001100000000000000010000000000000000000010110000000000001010000000000000011000000000000000000101100000000000010010000000000000100000000000000000001011000000000000100000000000000001110000000000000000010110000000000000111000000000000010100000000000000000101100000000000001100000000000000001000000000000000001011000000000000010100000000000000000000000000000000011110000000001101100000000000000000000000000000000000100000000000000000010000000000000101000000000000000000001000000000000010100000000000001010000000000000111010010000000000000111000000000000000100000000000000000100000000000000001010000000000000001000000000000000010010000000000000010100000000000000000000000000000000010010000000000000101000000000000101000000000000000001000100000000000001010000000000000000000000000000000001100000000000000010100000000000001010000000000000000000010000000000000101000000000000011100000000000001010101000000000000001110000000000001000000000000000000000010000000000000010100000000000001000000000000000101010010000000000000100000000000000000100000000000000000111000000000000010000000000000000111000000000000000001001000000000000011100000000000000000000000000000000010110000000000010111000000000000011100000000000000000100000000000000001010000000000000001000000000000000010010000000000000011000000000000000000000000000000000100100000000000000100000000000000000000000000000000001001000000000000000110000000000000000000000000000000010010000000000000010100000000000000000000000000000000010010000000000000110000000000010000000000000000000000100100000000000001000000000000111101000000000000000001001000000000000001100000000001000000000000000000000010010000000000000101000000000101110100000000000000001000100000000000001010000000000000000000000000000000001000000000000000010100000000000000010000000000000000100100000000000000110000000000000000000000000000000001001000000000000001000000000000000000000000000000000010010000000000000001100000000000000000000000000000000100100000000000000101000000000000000000000000000000000100100000000000001100000000001011011000000000000000001001000000000000010000000000011000100000000000000000010010000000000000011000000000110000100000000000000000100100000000000001010000000001110100000000000000000010000000000001001011000000000000000000000000000000000000110000000000000110000000000000011000000000000001010100100000000000001100000000000000000000000000000000001011000000000001011000000000000001100000000000000000001010000000000000101000000000000010100000000000000110100100000000000000110000000000000101000000000000000001000000000000000010100000000000000010000000000000000010000000000000000001000000000000010100000000000000000100100000000000001010000000000000000000000000000000001111000000000101000000000000000000000000000000000000010000000000000000001000000000000010100000000000000000000100000000000001010000000000000101000000000000001101001000000000000001100000000000000010000000000000000010000000000000000101000000000000000100000000000000000110100000000000001010000000000000011000000000000000001000000000000000001100000000000000000000000000000000000010000000000000101000000000000010100000000000000110101000000000000001010000000000000111000000000000000001011000000000001010100000000000001010000000000000000000100000000000000011000000000000010000000000000000110100100000000000001000000000000000001000000000000000000011000000000000001100000000000000110000000000000100010000000000000000100000000000000000100000000000000000100100000000000000110000000000000101000000000000000001110000000000000011100000000000001000000000000000000010010000000000000100000000000000000000000000000000001000000000000011010100000000000000000000000000000000000011000000000000010000000000000001000000000000000010010010000000000000100000000000000000000000000000000000101100000000000101000000000000000100000000000000000000101000000000000001000000000000000100000000000000011010010000000000000011000000000000101000000000000000000101100000000000100110000000000000011000000000000000001000000000000000001000000000000000010000000000000000010110000000000010010000000000000001000000000000000000100100000000000000010000000000000001000000000000000001011000000000001000100000000000000010000000000000000100110000000000000000000000000000000000000000000000000101100000000000100000000000000000000000000000000000010010000000000000111100000000000000000000000000000000100100000000000001110000000000000000000000000000000001001000000000000011010000000000000000000000000000000001001000000000000111100000000000010100000000000000000010110000000000001111000000000000111100000000000000000100100000000000011100000000001110010000000000000000001011000000000000111000000000000011100000000000000000010010000000000001101000000000111010100000000000000000101100000000000011010000000000001101000000000000000010010000000000000110000000000000000000000000000000000100100000000000001011000000000000000000000000000000001001000000000000010100000000000000000000000000000000010010000000000000100100000000000000000000000000000000010010000000000001100000000000110010100000000000000000101100000000000011000000000000001100000000000000000001001000000000000101100000000011011000000000000000000010110000000000001011000000000000101100000000000000000100100000000000010100000000001100001000000000000000001011000000000000101000000000000010100000000000000000010010000000000001001000000000111011000000000000000000101100000000000010010000000000001001000000000000000010010000000000000100000000000000000000000000000000000100100000000000000111000000000000000000000000000000001001000000000000001100000000000000000000000000000000010010000000000000010100000000000000000000000000000000010010000000000001000000000000010000000000000000000000101100000000000010000000000000001000000000000000000001001000000000000011100000000011001010000000000000000010110000000000000111000000000000011100000000000000000100100000000000001100000000001101110000000000000000001011000000000000011000000000000001100000000000000000010010000000000000101000000000111010100000000000000000101100000000000001010000000000000101000000000000000010010000000000000010000000000000000000000000000000000100100000000000000011000000000000000000000000000000001001000000000000000100000000000000000000000000000000010010000000000000000100000000000000000000000000000000010010000000000000100000000000010000000000000000000000101100000000000001000000000000000100000000000000000001001000000000000001100000000011100100000000000000000010110000000000000011000000000000001100000000000000000100100000000000000100000000001101001000000000000000001011000000000000001000000000000000100000000000000000010010000000000000001000000000111001100000000000000000101100000000000000010000000000000001000000000000000010010000000000000000000000000000000000000000000000000100100000000000001111000000000000000000000000000000001001000000000000011100000000000000000000000000000000010010000000000000110100000000000000000000000000000000010010000000000000000000000000110100100000000000000000101100000000000000000000000000000000000000000000000001001000000000000111100000000011000010000000000000000010010000000000001110000000000111001100000000000000000100100000000000011010000000000100000000000000000000010010000000000000110000000000000000000000000000000000100100000000000001011000000000000000000000000000000001001000000000000010100000000000000000000000000000000010010000000000000100100000000000000000000000000000000010010000000000001100000000000111101000000000000000000100100000000000010110000000001100101000000000000000001001000000000000101000000000011011000000000000000000010010000000000001001000000000110110000000000000000001001000000000000010000000000000000000000000000000000010010000000000000011100000000000000000000000000000000100100000000000000110000000000000000000000000000000001001000000000000001010000000000000000000000000000000001001000000000000100000000000011010010000000000000000010010000000000000111000000000111010100000000000000000100100000000000001100000000001100101000000000000000001001000000000000010100000000010101100000000000000000010010000000000000100000000000000000000000000000000000100100000000000000110000000000000000000000000000000001001000000000000001000000000000000000000000000000000010010000000000000001000000000000000000000000000000000100100000000000000000000000000000000000000000000000001111000000010001110000000000000000000000000000000000"; -- Skadoosh begin D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); diff --git a/Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd b/Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd new file mode 100644 index 0000000..ca44652 --- /dev/null +++ b/Processeur.srcs/sources_1/new/PeripheriqueClavier.vhd @@ -0,0 +1,107 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13.07.2021 09:30:08 +-- Design Name: +-- Module Name: PeripheriqueClavier - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PeripheriqueClavier is + Generic (Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_IN_Av : out STD_LOGIC; + STD_IN_Request : in STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC); +end PeripheriqueClavier; + +architecture Behavioral of PeripheriqueClavier is + + component KeyboardDriver + Generic (Nb_Bits : Natural); + Port (CLK : in STD_LOGIC; + Data_read : out STD_LOGIC; + Data_av : in STD_LOGIC; + Data : in STD_LOGIC_VECTOR (0 to 6); + STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_IN_Av : out STD_LOGIC; + STD_IN_Request : in STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC); + end component; + + component Keyboard + Port (CLK : in STD_LOGIC; + + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + + Data_read : in STD_LOGIC; + Data_av : out STD_LOGIC; + Data : out STD_LOGIC_VECTOR (0 to 6); + + alert : out STD_LOGIC); + end component; + + signal Data_read : STD_LOGIC := '0'; + signal Data_av : STD_LOGIC := '0'; + signal Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0'); + + signal nothing : STD_LOGIC := '0'; + +begin + + instance_Keyboard : Keyboard + port map (CLK => CLK, + + PS2Clk => PS2Clk, + PS2Data => PS2Data, + + Data_read => Data_read, + Data_av => Data_av, + Data => Data, + + alert => nothing); + + instance_KeyboardDriver : KeyboardDriver + generic map (Nb_Bits => Nb_Bits) + port map (CLK => CLK, + Data_read => Data_read, + Data_av => Data_av, + Data => Data, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => STD_OUT, + STD_OUT_Av => STD_OUT_Av); + +end Behavioral; diff --git a/Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd b/Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd new file mode 100644 index 0000000..9084dc8 --- /dev/null +++ b/Processeur.srcs/sources_1/new/PeripheriqueEcran.vhd @@ -0,0 +1,150 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.07.2021 15:25:56 +-- Design Name: +-- Module Name: PeripheriqueEcran - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +use work.ScreenProperties.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PeripheriqueEcran is + Generic ( Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + CLK_VGA : in STD_LOGIC; + RST : in STD_LOGIC; + + vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + + STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : in STD_LOGIC; + STD_OUT_Int : in STD_LOGIC); +end PeripheriqueEcran; + +architecture Behavioral of PeripheriqueEcran is + +component VGAControler is + Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0); + VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0); + VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0); + VGA_HS : out STD_LOGIC; + VGA_VS : out STD_LOGIC; + + X : out X_T; + Y : out Y_T; + PIXEL_ON : in STD_LOGIC; + + CLK : in STD_LOGIC; + RST : in STD_LOGIC); + end component; + + component clk_wiz_0 + port + (-- Clock in ports + clk_in1 : in std_logic; + -- Clock out ports + clk_out1 : out std_logic + ); + end component; + + component Ecran is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + Data_Av : in STD_LOGIC; + Data_IN : in STD_LOGIC_VECTOR (0 to 6); + X : in X_T; + Y : in Y_T; + OUT_ON : out STD_LOGIC); + end component; + + component ScreenDriver + Generic ( Nb_bits : Natural + ); + Port ( CLK : in STD_LOGIC; + Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + ValueAv : in STD_LOGIC; + IsInt : in STD_LOGIC; + OutData : out STD_LOGIC_VECTOR (0 to 6); + OutDataAv : out STD_LOGIC); + end component; + + signal my_X : X_T := 0; + signal my_Y : Y_T := 0; + signal my_PIXEL_ON : STD_LOGIC := '0'; + signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0'); + signal OutDataAv : STD_LOGIC := '0'; + signal my_CLK : STD_LOGIC := '0'; + +begin + + instanceVGA : VGAControler + port map( VGA_RED => vgaRed, + VGA_BLUE => vgaBlue, + VGA_GREEN => vgaGreen, + VGA_HS => Hsync, + VGA_VS => Vsync, + + X => my_X, + Y => my_Y, + PIXEL_ON => my_PIXEL_ON, + + CLK => my_CLK, + RST => RST); + + + clk_wiz_0_inst : clk_wiz_0 + port map ( + clk_in1 => CLK_VGA, + clk_out1 => my_CLK + ); + + + instance_Ecran : Ecran + port map ( CLK => CLK, + RST => RST, + Data_Av => OutDataAv, + Data_IN => OutData, + X => my_X, + Y => my_Y, + OUT_ON => my_PIXEL_ON); + + instance_ScreenDriver : ScreenDriver + Generic map ( Nb_bits => Nb_Bits + ) + Port map ( CLK => CLK, + Value => STD_OUT, + ValueAv => STD_OUT_Av, + IsInt => STD_OUT_Int, + OutData => OutData, + OutDataAv => OutDataAv); + +end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Pipeline.vhd b/Processeur.srcs/sources_1/new/Pipeline.vhd index 2d2d639..2e27daf 100644 --- a/Processeur.srcs/sources_1/new/Pipeline.vhd +++ b/Processeur.srcs/sources_1/new/Pipeline.vhd @@ -44,10 +44,14 @@ entity Pipeline is Adresse_mem_size : Natural := 5; Memoire_Adresses_Retour_Size : Natural := 16; Adresse_Memoire_Adresses_Retour_Size : Natural := 4); - Port (CLK : STD_LOGIC; - RST : STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); + Port (CLK : in STD_LOGIC; + RST : in STD_LOGIC; + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); end Pipeline; architecture Behavioral of Pipeline is @@ -67,12 +71,15 @@ architecture Behavioral of Pipeline is Instructions_critiques_ecriture : STD_LOGIC_VECTOR; Code_Instruction_JMP : STD_LOGIC_VECTOR; Code_Instruction_JMZ : STD_LOGIC_VECTOR; + Code_Instruction_PRI : STD_LOGIC_VECTOR; + Code_Instruction_PRIC : STD_LOGIC_VECTOR; Code_Instruction_CALL : STD_LOGIC_VECTOR; Code_Instruction_RET : STD_LOGIC_VECTOR; Code_Instruction_STOP : STD_LOGIC_VECTOR); Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; Z : in STD_LOGIC; + STD_IN_Request : in STD_LOGIC; A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -80,30 +87,35 @@ architecture Behavioral of Pipeline is end component; component Etage2_5_Registres is - Generic ( Nb_bits : Natural; - Nb_registres : Natural; - Addr_registres_size : Natural; - Instruction_bus_size : Natural; - Bits_Controle_LC_5 : STD_LOGIC_VECTOR; - Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; - Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; - Code_Instruction_PRI : STD_LOGIC_VECTOR; - Code_Instruction_GET : STD_LOGIC_VECTOR); - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); + Generic ( Nb_bits : Natural; -- Taille d'un mot binaire + Nb_registres : Natural; -- Nombre de registres du processeurs + Addr_registres_size : Natural; -- Nombre de bits pour adresser les registres + Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) + Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd) + Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd) + Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd) + Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI + Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC + Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET + Port ( CLK : in STD_LOGIC; -- Clock + RST : in STD_LOGIC; -- Reset + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC; + IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2 + IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2 + IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2 + IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction de l'étage 2 + OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A de l'étage 2 + OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B de l'étage 2 + OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C de l'étage 2 + OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction de l'étage 2 + IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 5 + IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 5 + IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Entrée de l'instruction de l'étage 5 end component; component Etage3_Calcul is @@ -181,27 +193,31 @@ architecture Behavioral of Pipeline is signal O : STD_LOGIC := '0'; signal C : STD_LOGIC := '0'; - constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111"; - constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001"; + signal intern_STD_IN_Request : STD_LOGIC := '0'; + + + constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111"; + constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001"; constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000"; - constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001"; - constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; - constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111"; - constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111"; - constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000"; - constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; + constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001"; + constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111"; + constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111"; + constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111011001111111111"; + constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000"; + constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110"; constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111"; constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000"; constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001"; - constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; - constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; - constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; - constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; + constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; -------- TO BE DONE + constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; + constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; + constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; + constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110"; - constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000"; - constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110"; - constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110"; - constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; + constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000"; + constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110"; + constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110"; + constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110"; begin instance_Etage1 : Etage1_LectureInstruction generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size, @@ -218,6 +234,8 @@ begin Instructions_critiques_ecriture => Instructions_critiques_ecriture, Code_Instruction_JMP => Code_Instruction_JMP, Code_Instruction_JMZ => Code_Instruction_JMZ, + Code_Instruction_PRI => Code_Instruction_PRI, + Code_Instruction_PRIC => Code_Instruction_PRIC, Code_Instruction_CALL => Code_Instruction_CALL, Code_Instruction_RET => Code_Instruction_RET, Code_Instruction_STOP => Code_Instruction_STOP @@ -226,6 +244,7 @@ begin CLK => CLK, RST => RST, Z => Z, + STD_IN_Request => intern_STD_IN_Request, A => A_from_1, B => B_from_1, C => C_from_1, @@ -241,12 +260,17 @@ begin Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A, Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B, Code_Instruction_PRI => Code_Instruction_PRI, + Code_Instruction_PRIC => Code_Instruction_PRIC, Code_Instruction_GET => Code_Instruction_GET ) port map( CLK => CLK, RST => RST, - STD_IN => STD_IN, - STD_OUT => STD_OUT, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => intern_STD_IN_Request, + STD_OUT => STD_OUT, + STD_OUT_Av => STD_OUT_Av, + STD_OUT_Int => STD_OUT_Int, IN_2_A => A_to_2, IN_2_B => B_to_2, IN_2_C => C_to_2, @@ -303,26 +327,30 @@ begin OUT_B => B_from_4, OUT_Instruction => Instruction_from_4 ); + + STD_IN_Request <= intern_STD_IN_Request; process begin wait until CLK'event and CLK = '1'; - A_to_2 <= A_from_1; - B_to_2 <= B_from_1; - C_to_2 <= C_from_1; - Instruction_to_2 <= Instruction_from_1; - - A_to_3 <= A_from_2; - B_to_3 <= B_from_2; - C_to_3 <= C_from_2; - Instruction_to_3 <= Instruction_from_2; - - A_to_4 <= A_from_3; - B_to_4 <= B_from_3; - Instruction_to_4 <= Instruction_from_3; - - A_to_5 <= A_from_4; - B_to_5 <= B_from_4; - Instruction_to_5 <= Instruction_from_4; + if (intern_STD_IN_Request = '0') then + A_to_2 <= A_from_1; + B_to_2 <= B_from_1; + C_to_2 <= C_from_1; + Instruction_to_2 <= Instruction_from_1; + + A_to_3 <= A_from_2; + B_to_3 <= B_from_2; + C_to_3 <= C_from_2; + Instruction_to_3 <= Instruction_from_2; + + A_to_4 <= A_from_3; + B_to_4 <= B_from_3; + Instruction_to_4 <= Instruction_from_3; + + A_to_5 <= A_from_4; + B_to_5 <= B_from_4; + Instruction_to_5 <= Instruction_from_4; + end if; end process; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/ScreenDriver.vhd b/Processeur.srcs/sources_1/new/ScreenDriver.vhd new file mode 100644 index 0000000..736d631 --- /dev/null +++ b/Processeur.srcs/sources_1/new/ScreenDriver.vhd @@ -0,0 +1,142 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.07.2021 09:54:12 +-- Design Name: +-- Module Name: ScreenDriver - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ScreenDriver is + Generic ( Nb_bits : Natural + ); + Port ( CLK : in STD_LOGIC; + Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + ValueAv : in STD_LOGIC; + IsInt : in STD_LOGIC; + OutData : out STD_LOGIC_VECTOR (0 to 6); + OutDataAv : out STD_LOGIC); +end ScreenDriver; + +architecture Behavioral of ScreenDriver is + + signal intern_value : STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0) := (others => '0'); + signal current_hexa : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); + subtype compteur_T is Natural range 0 to Nb_bits/4 - 1; + signal compteur : compteur_T := 0; + signal work_in_progess : BOOLEAN := false; + signal x_to_send : BOOLEAN := false; + signal first_detected : BOOLEAN := false; + + +begin + + current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4); + + process + begin + wait until CLK'event and CLK = '1'; + if ValueAv = '1' then + if IsInt = '0' then + OutData <= Value (6 downto 0); + else + intern_value <= Value; + OutData <= "0110000"; + x_to_send <= true; + end if; + OutDataAv <= '1'; + elsif x_to_send then + OutData <= "1111000"; + OutDataAv <= '1'; + x_to_send <= false; + work_in_progess <= true; + first_detected <= false; + elsif work_in_progess then + case current_hexa is + when "0000" => + if first_detected or compteur = Nb_bits/4 - 1 then + OutData <= "0110000"; + end if; + when "0001" => + OutData <= "0110001"; + when "0010" => + OutData <= "0110010"; + when "0011" => + OutData <= "0110011"; + when "0100" => + OutData <= "0110100"; + when "0101" => + OutData <= "0110101"; + when "0110" => + OutData <= "0110110"; + when "0111" => + OutData <= "0110111"; + when "1000" => + OutData <= "0111000"; + when "1001" => + OutData <= "0111001"; + when "1010" => + OutData <= "1000001"; + when "1011" => + OutData <= "1000010"; + when "1100" => + OutData <= "1000011"; + when "1101" => + OutData <= "1000100"; + when "1110" => + OutData <= "1000101"; + when "1111" => + OutData <= "1000110"; + when others => + OutData <= "0000001"; + end case; + + + if first_detected or not (current_hexa = "0000") or compteur = Nb_bits/4 - 1 then + OutDataAv <= '1'; + first_detected <= true; + else + OutDataAv <= '0'; + first_detected <= false; + end if; + + if (compteur = Nb_bits/4 - 1) then + compteur <= 0; + work_in_progess <= false; + x_to_send <= false; + first_detected <= false; + else + compteur <= compteur + 1; + end if; + else + OutDataAv <= '0'; + end if; + end process; + +end Behavioral; diff --git a/Processeur.srcs/sources_1/new/System.vhd b/Processeur.srcs/sources_1/new/System.vhd index 346296c..8d02367 100644 --- a/Processeur.srcs/sources_1/new/System.vhd +++ b/Processeur.srcs/sources_1/new/System.vhd @@ -24,8 +24,13 @@ use IEEE.STD_LOGIC_1164.ALL; -- Récupération d'un bouton pour RST -- Récupération de la clock entity System is - Port ( led : out STD_LOGIC_VECTOR (7 downto 0); - sw : in STD_LOGIC_VECTOR (7 downto 0); + Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; btnC : in STD_LOGIC; CLK : STD_LOGIC); end System; @@ -45,10 +50,14 @@ architecture Structural of System is Adresse_mem_size : Natural := 5; Memoire_Adresses_Retour_Size : Natural := 16; Adresse_Memoire_Adresses_Retour_Size : Natural := 4); - Port (CLK : STD_LOGIC; - RST : STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); + Port (CLK : in STD_LOGIC; + RST : in STD_LOGIC; + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); end component; component Pipeline_NS is @@ -66,6 +75,36 @@ architecture Structural of System is STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; + component PeripheriqueEcran + Generic ( Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + CLK_VGA : in STD_LOGIC; + RST : in STD_LOGIC; + + vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + + STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : in STD_LOGIC; + STD_OUT_Int : in STD_LOGIC); + end component; + + component PeripheriqueClavier + Generic (Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_IN_Av : out STD_LOGIC; + STD_IN_Request : in STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC); + end component; + component Clock_Divider is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); @@ -74,10 +113,22 @@ architecture Structural of System is -- signaux auxiliaires signal my_RST : STD_LOGIC; signal my_CLK : STD_LOGIC; + signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); + signal STD_IN_Av : STD_LOGIC := '0'; + signal STD_IN_Request : STD_LOGIC := '0'; + signal intern_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); + signal intern_STD_OUT_Av : STD_LOGIC := '0'; + signal intern_STD_OUT_Int : STD_LOGIC := '0'; + signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); + signal pipeline_STD_OUT_Av : STD_LOGIC := '0'; + signal pipeline_STD_OUT_Int : STD_LOGIC := '0'; + signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); + signal clavier_STD_OUT_Av : STD_LOGIC := '0'; + signal clavier_STD_OUT_Int : STD_LOGIC := '0'; constant SECURISED : boolean := true; -begin +begin -- Diviseur de clock clk_div : Clock_Divider @@ -88,25 +139,73 @@ begin -- Generation du processeur en fonction de la condition sécurisé ou non instance: if (SECURISED) generate instance_securisee : entity work.Pipeline - generic map (Addr_Memoire_Instruction_Size => 8, - Memoire_Instruction_Size => 256) + generic map (Nb_bits => 16, + Instruction_En_Memoire_Size => 53, + Addr_Memoire_Instruction_Size => 9, + Memoire_Instruction_Size => 512, + Instruction_Bus_Size => 5, + Nb_Instructions => 32, + Nb_Registres => 16, + Addr_registres_size => 4, + Memoire_Size => 32, + Adresse_mem_size => 5, + Memoire_Adresses_Retour_Size => 4, + Adresse_Memoire_Adresses_Retour_Size => 2) port map (CLK => my_CLK, RST => my_RST, - STD_IN => sw, - STD_OUT => led); + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => pipeline_STD_OUT, + STD_OUT_Av => pipeline_STD_OUT_Av, + STD_OUT_Int => pipeline_STD_OUT_Int); else generate instance_non_securisee : entity work.Pipeline_NS - generic map (Addr_Memoire_Instruction_Size => 8, - Memoire_Instruction_Size => 256) + generic map (Addr_Memoire_Instruction_Size => 9, + Memoire_Instruction_Size => 512) port map (CLK => my_CLK, RST => my_RST, - STD_IN => sw, - STD_OUT => led); + STD_IN => STD_IN, + STD_OUT => pipeline_STD_OUT); end generate; + + instance_perif_ecran : PeripheriqueEcran + generic map ( Nb_Bits => 16) + port map ( CLK => my_CLK, + CLK_VGA => CLK, + RST => my_RST, + + vgaRed => vgaRed, + vgaBlue => vgaBlue, + vgaGreen => vgaGreen, + Hsync => Hsync, + Vsync => Vsync, + + STD_OUT => intern_STD_OUT, + STD_OUT_Av => intern_STD_OUT_Av, + STD_OUT_Int => intern_STD_OUT_Int); + + instance_perif_clavier : PeripheriqueClavier + generic map (Nb_Bits => 16) + port map ( CLK => my_CLK, + RST => my_RST, + PS2Clk => PS2Clk, + PS2Data => PS2Data, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => clavier_STD_OUT, + STD_OUT_Av => clavier_STD_OUT_Av); -- Gestion du RST (inversion d'état) my_RST <= '1' when btnC = '0' else '0'; + + + intern_STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT; + intern_STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av; + intern_STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int; + end Structural; diff --git a/Processeur.xpr b/Processeur.xpr index 13a1977..702c566 100644 --- a/Processeur.xpr +++ b/Processeur.xpr @@ -35,7 +35,7 @@