ADC interuption soon finish

This commit is contained in:
Clement Marce 2023-03-31 12:17:01 +02:00
parent 1c84636b75
commit 8d1127512c
4 changed files with 37 additions and 17 deletions

View file

@ -11,8 +11,9 @@ typedef struct
} MyADC_Struct_TypeDef; } MyADC_Struct_TypeDef;
void MyADC_Base_Init(MyADC_Struct_TypeDef * ADC); void MyADC_Base_Init(MyADC_Struct_TypeDef * ADC, void (*fct)(void));
void MyADC_Base_Start(ADC_TypeDef * ADC); void MyADC_Base_Start(ADC_TypeDef * ADC);
void MyADC_Base_Stop(ADC_TypeDef * ADC); void MyADC_Base_Stop(ADC_TypeDef * ADC);
void MyADC_Base_Interuption(ADC_TypeDef * ADC);
#endif #endif

View file

@ -1,39 +1,46 @@
#include "Driver_ADC.h" #include "Driver_ADC.h"
#include "Driver_GPIO.h" #include "Driver_GPIO.h"
//----------------------INIT--------------------//
void MyADC_Base_Init(MyADC_Struct_TypeDef * ADC){
MyGPIO_Struct_TypeDef * GPIO_ADC; void (*PtrfctADC)(void); //Déclaration du pointeur de fonction ADC
//----------------------INIT--------------------//
void MyADC_Base_Init(MyADC_Struct_TypeDef * ADC, void (*fct)(void)){
MyGPIO_Struct_TypeDef * GPIO_ADC; //Déclaration du GPIO de l'ADC
PtrfctADC=fct; //Affectation du pointeur de fonction ADC
//Division par 6 de la clock (72MHz) pour l'ADC (14MHz max) //Division par 6 de la clock (72MHz) pour l'ADC (14MHz max)
RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6;
//Selection du channel PC0 pour l'ADC //Affectation du channel PC0 pour l'ADC
GPIO_ADC->GPIO = GPIOC; GPIO_ADC->GPIO = GPIOC;
GPIO_ADC->GPIO_Conf = In_Analog; GPIO_ADC->GPIO_Conf = In_Analog;
GPIO_ADC->GPIO_Pin = 0; GPIO_ADC->GPIO_Pin = 0;
//Selection entre ADC1 ou ADC2 //Sart et choix de ADC1 ou ADC2
if(ADC->ADC == ADC1){ MyADC_Base_Start(ADC->ADC);
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; //Enable Clock ADC1 MyADC_Base_Interuption(ADC->ADC);
}else if(ADC->ADC == ADC2){
RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; //Enable Clock ADC2
}
} }
//-------------------------------------------------------------------//
//----------------------------- FONCTIONS ---------------------------//
//-------------------------------------------------------------------//
//---------------------START--------------------// //---------------------START--------------------//
void MyADC_Base_Start(ADC_TypeDef * ADC){ void MyADC_Base_Start(ADC_TypeDef * ADC){
if(ADC == ADC1){ if(ADC == ADC1){
ADC1->CR2 |= ADC_CR2_ADON; //Enable ADC1 ADC1->CR2 |= ADC_CR2_ADON; //Enable ADC1
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; //Clock enable ADC1
} else if (ADC == ADC2){ } else if (ADC == ADC2){
ADC2->CR2 |= ADC_CR2_ADON; //Enable ADC2 ADC2->CR2 |= ADC_CR2_ADON; //Enable ADC2
RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; //Clock enable ADC2
} }
} }
//---------------------STOP--------------------// //---------------------STOP--------------------//
void MyADC_Base_Stop(ADC_TypeDef * ADC){ void MyADC_Base_Stop(ADC_TypeDef * ADC){
if(ADC == ADC1){ if(ADC == ADC1){
@ -43,9 +50,17 @@ void MyADC_Base_Stop(ADC_TypeDef * ADC){
} }
} }
//--------------------HANDLER---------------// //-----------------INTERRUPTION-------------//
void ADC1_2_IRQHandler (void) { void MyADC_Base_Interuption(ADC_TypeDef * ADC){
ADC1->SR &= ~(1<<1); //RAZ du flag end of conversion ADC->CR1 |= ADC_CR1_EOCIE; //Interruption active
NVIC->ISER[0] |= (0x1<<ADC1_2_IRQn); //Interruption active au niveau du coeur
//GESTION PRIO ??????????????
}
//--------------------HANDLER---------------//
void ADC1_2_IRQHandler (void) {
PtrfctADC();
ADC1->SR &= ~(1<<1); //RAZ du flag end of conversion
} }

View file

@ -479,7 +479,7 @@
<GroupNumber>1</GroupNumber> <GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber> <FileNumber>3</FileNumber>
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\Drivers\Sources\Driver_ADC.c</PathWithFileName> <PathWithFileName>..\Drivers\Sources\Driver_ADC.c</PathWithFileName>

View file

@ -28,6 +28,10 @@ int main (void){
while(1){ while(1){
} }
//TEST ADC
} }