274 lines
7.4 KiB
VHDL
274 lines
7.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:52:06 05/04/2021
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-- Design Name:
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-- Module Name: processeur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity processeur is
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Port ( CLK: in STD_LOGIC ;
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RST : in STD_LOGIC);
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end processeur;
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architecture Behavioral of processeur is
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COMPONENT bm_instr
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PORT(
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IN_addr : IN std_logic_vector(7 downto 0);
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OUT_data : OUT std_logic_vector(7 downto 0);
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CLK : IN std_logic
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);
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END COMPONENT;
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COMPONENT pipeline
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PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0);
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A_IN : in STD_LOGIC_VECTOR (7 downto 0);
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B_IN : in STD_LOGIC_VECTOR (7 downto 0);
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C_IN : in STD_LOGIC_VECTOR (7 downto 0);
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OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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C_OUT : out STD_LOGIC_VECTOR (7 downto 0)
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);
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END COMPONENT;
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COMPONENT br
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PORT(
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A_addr : IN std_logic_vector(3 downto 0);
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B_addr : IN std_logic_vector(3 downto 0);
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W_addr : IN std_logic_vector(3 downto 0);
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W : IN std_logic;
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Data : IN std_logic_vector(7 downto 0);
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RST : IN std_logic;
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CLK : IN std_logic;
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QA : OUT std_logic_vector(7 downto 0);
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QB : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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COMPONENT alu
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PORT(
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A : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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Ctrl_Alu : IN std_logic_vector(2 downto 0);
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N : OUT std_logic;
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O : OUT std_logic;
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Z : OUT std_logic;
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C : OUT std_logic;
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S : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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COMPONENT bm_data
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PORT(
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IN_addr : IN std_logic_vector(7 downto 0);
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IN_data : IN std_logic_vector(7 downto 0);
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RW : IN std_logic;
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RST : IN std_logic;
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CLK : IN std_logic;
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OUT_data : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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signal RST : std_logic := '0';
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signal CLK : std_logic := '0';
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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--Inputs
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signal IP : std_logic_vector(7 downto 0) := (others => '0');
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signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
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signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
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signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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signal OUT_data : std_logic_vector(7 downto 0);
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signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
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signal A_LIDI_OUT : std_logic_vector(7 downto 0);
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signal B_LIDI_OUT : std_logic_vector(7 downto 0);
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signal C_LIDI_OUT : std_logic_vector(7 downto 0);
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signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
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signal A_DIEX_OUT : std_logic_vector(7 downto 0);
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signal B_DIEX_OUT : std_logic_vector(7 downto 0);
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signal C_DIEX_OUT : std_logic_vector(7 downto 0);
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signal O_ALU_OUT : std_logic;
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signal N_ALU_OUT : std_logic;
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signal Z_ALU_OUT : std_logic;
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signal C_ALU_OUT : std_logic;
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signal A_EXMem_OUT : std_logic_vector(7 downto 0);
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signal B_EXMem_OUT : std_logic_vector(7 downto 0);
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signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
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signal A_MemRE_OUT : std_logic_vector(7 downto 0);
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signal B_MemRE_OUT : std_logic_vector(7 downto 0);
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signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
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--AUX
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signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
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signal RW_LC : std_logic;
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signal addr_dm_MUX : std_logic_vector(7 downto 0);
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signal in_dm_MUX : std_logic_vector(7 downto 0);
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signal out_dm_MUX : std_logic_vector(7 downto 0);
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signal W_br_LC : std_logic;
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begin
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-- Instantiate adresse des instructions
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addr_instructions: bm_instr PORT MAP (
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IP => IN_addr,
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OUT_data => OUT_data,
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CLK => CLK
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);
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-- Instantiate pipeline LI_LD
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LI_LD : pipeline PORT MAP (
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OP_IN <= OUT_data(31 downto 24),
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A_IN <= OUT_data(23 downto 16),
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B_IN <= OUT_data(15 downto 8),
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C_IN <= OUT_data(7 downto 0),
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CLK => CLK,
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A_OUT => A_LIDI_OUT,
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B_OUT => B_LIDI_OUT,
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C_OUT => C_LIDI_OUT,
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OP_OUT => OP_LIDI_OUT
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);
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W_br_LC <= '1' when OP_MemRE_OUT = x"07" else
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'0';
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-- Instanciate banc de registre
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banc_registres : br PORT MAP (
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B_LIDI_OUT => A_addr,
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C_LIDI_OUT => B_addr,
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A_MemRE_OUT => W_addr,
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W_br_LC => W, --ATTENTION LC
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B_MemRE_OUT => Data,
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RST => RST,
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CLK => CLK,
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QA => QA_IN_MUX,
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QB => C_DIEX_IN
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);
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B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" else B_LIDI_OUT ;
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-- Instantiate pipeline DI_EX
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DI_EX : pipeline PORT MAP (
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OP_IN <= OP_LIDI_OUT,
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A_IN <= A_LIDI_OUT,
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B_IN <= B_DIEX_IN,
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C_IN <= C_DIEX_IN,
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CLK => CLK,
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A_OUT => A_DIEX_OUT,
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B_OUT => B_DIEX_OUT,
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C_OUT => C_DIEX_OUT,
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OP_OUT => OP_DIEX_OUT
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);
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Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else
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"010" when OP_DIEX_OUT = x"03" else
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"011" when OP_DIEX_OUT = x"02" else
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"000";
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-- Instantiate alu
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UAL : alu PORT MAP (
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A <= B_DIEX_OUT,
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B <= C_DIEX_OUT,
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Ctrl_Alu <= Ctr_AlU_LC,
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N => N_ALU_OUT,
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O => O_ALU_OUT,
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Z => Z_ALU_OUT,
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C => C_ALU_OUT,
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S => S_IN_MUX
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);
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B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else
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B_DIEX_OUT ;
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-- Instantiate pipeline EX_Mem
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EX_Mem : pipeline PORT MAP (
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OP_IN <= OP_DIEX_OUT,
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A_IN <= A_DIEX_OUT,
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B_IN <= B_EXMem_IN,
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C_IN <= x"00",
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CLK => CLK,
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A_OUT => A_EXMem_OUT,
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B_OUT => B_EXMem_OUT,
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C_OUT => open,
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OP_OUT => OP_EXMem_OUT
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);
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RW_LC <= '0' when OP_EXMem_OUT = x"08" else
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'1';
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addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
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A_EXMem_OUT;
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in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
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B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
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B_EXMem_OUT;
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-- Instantiate banc de données
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data_memory: bm_data PORT MAP (
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addr_dm_MUX => IN_addr,
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B_MemRE_IN => IN_data,
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RW_LC => RW,
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RST => RST,
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CLK => CLK,
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OUT_data => out_dm_MUX
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);
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-- Instantiate pipeline Mem_RE
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Mem_RE : pipeline PORT MAP (
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OP_IN <= OP_EXMem_OUT,
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A_IN <= A_EXMem_OUT,
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B_IN <= OUT_data(15 downto 8),
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C_IN <= x"00",
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CLK => CLK,
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A_OUT => A_MemRE_OUT,
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B_OUT => B_MemRE_OUT,
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C_OUT => open,
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OP_OUT => OP_MemRE_OUT
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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IP <= IP + "00000001";
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end Behavioral;
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