Browse Source

Tests for processor ongoing

Foussats Morgane 4 months ago
parent
commit
56ee58bb48
77 changed files with 2995 additions and 3559 deletions
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      a.out
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      instructions.txt
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BIN
a.out View File


+ 859
- 859
analyse_syntaxique.output
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+ 877
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analyse_syntaxique.tab.c
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+ 69
- 93
analyse_syntaxique.tab.h View File

@@ -1,14 +1,13 @@
1
-/* A Bison parser, made by GNU Bison 2.3.  */
1
+/* A Bison parser, made by GNU Bison 3.0.4.  */
2 2
 
3
-/* Skeleton interface for Bison's Yacc-like parsers in C
3
+/* Bison interface for Yacc-like parsers in C
4 4
 
5
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
6
-   Free Software Foundation, Inc.
5
+   Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
7 6
 
8
-   This program is free software; you can redistribute it and/or modify
7
+   This program is free software: you can redistribute it and/or modify
9 8
    it under the terms of the GNU General Public License as published by
10
-   the Free Software Foundation; either version 2, or (at your option)
11
-   any later version.
9
+   the Free Software Foundation, either version 3 of the License, or
10
+   (at your option) any later version.
12 11
 
13 12
    This program is distributed in the hope that it will be useful,
14 13
    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -16,9 +15,7 @@
16 15
    GNU General Public License for more details.
17 16
 
18 17
    You should have received a copy of the GNU General Public License
19
-   along with this program; if not, write to the Free Software
20
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
21
-   Boston, MA 02110-1301, USA.  */
18
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22 19
 
23 20
 /* As a special exception, you may create a larger work that contains
24 21
    part or all of the Bison parser skeleton and distribute that work
@@ -33,99 +30,78 @@
33 30
    This special exception was added by the Free Software Foundation in
34 31
    version 2.2 of Bison.  */
35 32
 
36
-/* Tokens.  */
33
+#ifndef YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
34
+# define YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
35
+/* Debug traces.  */
36
+#ifndef YYDEBUG
37
+# define YYDEBUG 1
38
+#endif
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+#if YYDEBUG
40
+extern int yydebug;
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+#endif
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+
43
+/* Token type.  */
37 44
 #ifndef YYTOKENTYPE
38 45
 # define YYTOKENTYPE
39
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
40
-      know about them.  */
41
-   enum yytokentype {
42
-     tENTIER = 258,
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-     tENTIEREXP = 259,
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-     tADD = 260,
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-     tSUB = 261,
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-     tMUL = 262,
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-     tDIV = 263,
48
-     tPO = 264,
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-     tPF = 265,
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-     tAO = 266,
51
-     tAF = 267,
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-     tERROR = 268,
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-     tAPPERSAND = 269,
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-     tPV = 270,
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-     tVIRGULE = 271,
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-     tAFFECTATION = 272,
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-     tEGAL = 273,
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-     tDIFF = 274,
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-     tLT = 275,
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-     tGT = 276,
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-     tGTE = 277,
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-     tLTE = 278,
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-     tMAIN = 279,
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-     tINT = 280,
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-     tPRINT = 281,
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-     tRETURN = 282,
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-     tOR = 283,
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-     tAND = 284,
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-     tIF = 285,
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-     tELSE = 286,
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-     tWHILE = 287,
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-     tCONST = 288,
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-     tVAR = 289,
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-     tNOT = 290
75
-   };
46
+  enum yytokentype
47
+  {
48
+    tENTIER = 258,
49
+    tENTIEREXP = 259,
50
+    tADD = 260,
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+    tSUB = 261,
52
+    tMUL = 262,
53
+    tDIV = 263,
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+    tPO = 264,
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+    tPF = 265,
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+    tAO = 266,
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+    tAF = 267,
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+    tERROR = 268,
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+    tAPPERSAND = 269,
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+    tPV = 270,
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+    tVIRGULE = 271,
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+    tAFFECTATION = 272,
63
+    tEGAL = 273,
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+    tDIFF = 274,
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+    tLT = 275,
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+    tGT = 276,
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+    tGTE = 277,
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+    tLTE = 278,
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+    tMAIN = 279,
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+    tINT = 280,
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+    tPRINT = 281,
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+    tRETURN = 282,
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+    tOR = 283,
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+    tAND = 284,
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+    tIF = 285,
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+    tELSE = 286,
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+    tWHILE = 287,
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+    tCONST = 288,
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+    tVAR = 289,
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+    tNOT = 290
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+  };
76 82
 #endif
77
-/* Tokens.  */
78
-#define tENTIER 258
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-#define tENTIEREXP 259
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-#define tADD 260
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-#define tSUB 261
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-#define tMUL 262
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-#define tDIV 263
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-#define tPO 264
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-#define tPF 265
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-#define tAO 266
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-#define tAF 267
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-#define tERROR 268
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-#define tAPPERSAND 269
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-#define tPV 270
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-#define tVIRGULE 271
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-#define tAFFECTATION 272
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-#define tEGAL 273
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-#define tDIFF 274
95
-#define tLT 275
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-#define tGT 276
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-#define tGTE 277
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-#define tLTE 278
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-#define tMAIN 279
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-#define tINT 280
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-#define tPRINT 281
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-#define tRETURN 282
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-#define tOR 283
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-#define tAND 284
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-#define tIF 285
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-#define tELSE 286
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-#define tWHILE 287
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-#define tCONST 288
109
-#define tVAR 289
110
-#define tNOT 290
111
-
112
-
113
-
114 83
 
84
+/* Value type.  */
115 85
 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
116
-typedef union YYSTYPE
117
-#line 1 "analyse_syntaxique.y"
86
+
87
+union YYSTYPE
118 88
 {
89
+#line 1 "analyse_syntaxique.y" /* yacc.c:1909  */
90
+
119 91
 int nombre;
120 92
 char id[30];
121
-}
122
-/* Line 1529 of yacc.c.  */
123
-#line 124 "analyse_syntaxique.tab.h"
124
-	YYSTYPE;
125
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
126
-# define YYSTYPE_IS_DECLARED 1
93
+
94
+#line 95 "analyse_syntaxique.tab.h" /* yacc.c:1909  */
95
+};
96
+
97
+typedef union YYSTYPE YYSTYPE;
127 98
 # define YYSTYPE_IS_TRIVIAL 1
99
+# define YYSTYPE_IS_DECLARED 1
128 100
 #endif
129 101
 
102
+
130 103
 extern YYSTYPE yylval;
131 104
 
105
+int yyparse (void);
106
+
107
+#endif /* !YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED  */

+ 2
- 2
analyse_syntaxique.y View File

@@ -157,7 +157,7 @@ If : tIF tPO Cond tPF {
157 157
     free_temp(&table);
158 158
     $1 = array.index;
159 159
 }
160
-tAO {table.depth++;} Instructions {generate_instruction_1(&array, JMP, -1)} tAF {remove_symboles(&table); table.depth--;}
160
+tAO {table.depth++;} Instructions {generate_instruction_1(&array, JMP, -1);} tAF {remove_symboles(&table); table.depth--;}
161 161
 {
162 162
     int adr_jmp = array.index;
163 163
     update_jmf(&array, $1, adr_jmp);
@@ -203,7 +203,7 @@ Invocation : tVAR tPO {table.depth++; prepare_function_call(&table); return_valu
203 203
 
204 204
 Args : Arg SuiteArgs ;
205 205
 Args :
206
-Arg : E {int arg_addr = prepare_argument_push(&table); generate_instruction_2(&array, COP, arg_addr, $1); free_temp(&table)};
206
+Arg : E {int arg_addr = prepare_argument_push(&table); generate_instruction_2(&array, COP, arg_addr, $1); free_temp(&table);};
207 207
 SuiteArgs : tVIRGULE Arg SuiteArgs ;
208 208
 SuiteArgs : ;
209 209
 

+ 16
- 11
instructions.txt View File

@@ -1,11 +1,16 @@
1
-0	 AFC 49 2
2
-1	 COP 0 49
3
-2	 LEA 49 0
4
-3	 COP 1 49
5
-4	 AFC 49 2
6
-5	 COP_STR [1] 49
7
-6	 COP 49 1
8
-7	 COP_LD 49 [49]
9
-8	 COP 2 49
10
-9	 AFC 49 0
11
-10	 RET 49
1
+0	 AFC 49 4
2
+1	 COP 1 49
3
+2	 AFC 49 1
4
+3	 RET 49
5
+4	 RET_FUN
6
+5	 AFC 49 2
7
+6	 COP 0 49
8
+7	 LEA 49 0
9
+8	 COP 1 49
10
+9	 AFC 49 2
11
+10	 COP_STR [1] 49
12
+11	 COP 49 1
13
+12	 COP_LD 49 [49]
14
+13	 COP 2 49
15
+14	 AFC 49 0
16
+15	 RET 49

+ 227
- 219
lex.yy.c
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+ 5
- 0
script.sh View File

@@ -2,6 +2,11 @@ bison -d -t analyse_syntaxique.y -v
2 2
 flex analyse_lexicale.lex 
3 3
 gcc -w *.c -ly
4 4
 echo "
5
+    int fonction1(int a){
6
+      int b = 4;
7
+      return 1;
8
+    }
9
+
5 10
     int main(){
6 11
       int c = 2;
7 12
       int * p;

+ 21
- 22
xilinx/ALU/ALU.gise View File

@@ -25,14 +25,15 @@
25 25
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
26 26
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
27 27
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
28
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_data_test_beh.prj"/>
29 28
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
30
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_data_test_isim_beh.wdb"/>
29
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
31 30
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
31
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
32 32
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
33 33
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
34 34
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
35 35
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
36
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
36 37
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
37 38
   </files>
38 39
 
@@ -45,7 +46,7 @@
45 46
       <status xil_pn:value="SuccessfullyRun"/>
46 47
       <status xil_pn:value="ReadyToRun"/>
47 48
     </transform>
48
-    <transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618572938">
49
+    <transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620134567">
49 50
       <status xil_pn:value="SuccessfullyRun"/>
50 51
       <status xil_pn:value="ReadyToRun"/>
51 52
       <outfile xil_pn:name="alu.vhd"/>
@@ -56,20 +57,22 @@
56 57
       <outfile xil_pn:name="bm_instr_test.vhd"/>
57 58
       <outfile xil_pn:name="br.vhd"/>
58 59
       <outfile xil_pn:name="br_test.vhd"/>
60
+      <outfile xil_pn:name="pipeline.vhd"/>
61
+      <outfile xil_pn:name="processeur.vhd"/>
59 62
     </transform>
60
-    <transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8940589992921887805" xil_pn:start_ts="1618572911">
63
+    <transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-182187785304845874" xil_pn:start_ts="1620134030">
61 64
       <status xil_pn:value="SuccessfullyRun"/>
62 65
       <status xil_pn:value="ReadyToRun"/>
63 66
     </transform>
64
-    <transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1570780385922884283" xil_pn:start_ts="1618572911">
67
+    <transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5858825779926760884" xil_pn:start_ts="1620134030">
65 68
       <status xil_pn:value="SuccessfullyRun"/>
66 69
       <status xil_pn:value="ReadyToRun"/>
67 70
     </transform>
68
-    <transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8229480169080511278" xil_pn:start_ts="1618303356">
71
+    <transform xil_pn:end_ts="1620126566" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="9006895703308992987" xil_pn:start_ts="1620126566">
69 72
       <status xil_pn:value="SuccessfullyRun"/>
70 73
       <status xil_pn:value="ReadyToRun"/>
71 74
     </transform>
72
-    <transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618572938">
75
+    <transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620134567">
73 76
       <status xil_pn:value="SuccessfullyRun"/>
74 77
       <status xil_pn:value="ReadyToRun"/>
75 78
       <outfile xil_pn:name="alu.vhd"/>
@@ -80,25 +83,21 @@
80 83
       <outfile xil_pn:name="bm_instr_test.vhd"/>
81 84
       <outfile xil_pn:name="br.vhd"/>
82 85
       <outfile xil_pn:name="br_test.vhd"/>
86
+      <outfile xil_pn:name="pipeline.vhd"/>
87
+      <outfile xil_pn:name="processeur.vhd"/>
83 88
     </transform>
84
-    <transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2732656885201204134" xil_pn:start_ts="1618572938">
85
-      <status xil_pn:value="SuccessfullyRun"/>
89
+    <transform xil_pn:end_ts="1620134568" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6599872206167540207" xil_pn:start_ts="1620134567">
90
+      <status xil_pn:value="FailedRun"/>
86 91
       <status xil_pn:value="ReadyToRun"/>
87
-      <status xil_pn:value="OutOfDateForOutputs"/>
88
-      <status xil_pn:value="OutputChanged"/>
89
-      <outfile xil_pn:name="bm_data_test_beh.prj"/>
90
-      <outfile xil_pn:name="bm_data_test_isim_beh.exe"/>
91
-      <outfile xil_pn:name="fuse.log"/>
92
-      <outfile xil_pn:name="isim"/>
93
-      <outfile xil_pn:name="xilinxsim.ini"/>
94 92
     </transform>
95
-    <transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5666824002871888647" xil_pn:start_ts="1618572940">
96
-      <status xil_pn:value="SuccessfullyRun"/>
93
+    <transform xil_pn:end_ts="1620126600" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1620126600">
94
+      <status xil_pn:value="AbortedRun"/>
97 95
       <status xil_pn:value="ReadyToRun"/>
98
-      <status xil_pn:value="OutOfDateForOutputs"/>
99
-      <status xil_pn:value="OutputChanged"/>
100
-      <outfile xil_pn:name="bm_data_test_isim_beh.wdb"/>
101
-      <outfile xil_pn:name="isim.cmd"/>
96
+      <status xil_pn:value="OutOfDateForInputs"/>
97
+      <status xil_pn:value="OutOfDateForProperties"/>
98
+      <status xil_pn:value="OutOfDateForPredecessor"/>
99
+      <status xil_pn:value="OutOfDateForced"/>
100
+      <status xil_pn:value="InputRemoved"/>
102 101
     </transform>
103 102
   </transforms>
104 103
 

+ 26
- 18
xilinx/ALU/ALU.xise View File

@@ -16,7 +16,7 @@
16 16
 
17 17
   <files>
18 18
     <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
19
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
19
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
20 20
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
21 21
     </file>
22 22
     <file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
@@ -26,7 +26,7 @@
26 26
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
27 27
     </file>
28 28
     <file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
29
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
29
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
30 30
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
31 31
     </file>
32 32
     <file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
@@ -36,11 +36,11 @@
36 36
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
37 37
     </file>
38 38
     <file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
39
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
39
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
40 40
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
41 41
     </file>
42 42
     <file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
43
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
43
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
44 44
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
45 45
     </file>
46 46
     <file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
@@ -50,11 +50,19 @@
50 50
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
51 51
     </file>
52 52
     <file xil_pn:name="bm_data_test.vhd" xil_pn:type="FILE_VHDL">
53
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
53
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
54 54
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
55 55
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
56 56
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
57 57
     </file>
58
+    <file xil_pn:name="pipeline.vhd" xil_pn:type="FILE_VHDL">
59
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
60
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
61
+    </file>
62
+    <file xil_pn:name="processeur.vhd" xil_pn:type="FILE_VHDL">
63
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
64
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
65
+    </file>
58 66
   </files>
59 67
 
60 68
   <properties>
@@ -171,9 +179,9 @@
171 179
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
172 180
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
173 181
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
174
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|alu|Behavioral" xil_pn:valueState="non-default"/>
175
-    <property xil_pn:name="Implementation Top File" xil_pn:value="alu.vhd" xil_pn:valueState="non-default"/>
176
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/alu" xil_pn:valueState="non-default"/>
182
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
183
+    <property xil_pn:name="Implementation Top File" xil_pn:value="processeur.vhd" xil_pn:valueState="non-default"/>
184
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
177 185
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
178 186
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
179 187
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -236,7 +244,7 @@
236 244
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
237 245
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
238 246
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
239
-    <property xil_pn:name="Output File Name" xil_pn:value="alu" xil_pn:valueState="default"/>
247
+    <property xil_pn:name="Output File Name" xil_pn:value="processeur" xil_pn:valueState="default"/>
240 248
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
241 249
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
242 250
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -249,10 +257,10 @@
249 257
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
250 258
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
251 259
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
252
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="alu_map.vhd" xil_pn:valueState="default"/>
253
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
254
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
255
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
260
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="processeur_map.vhd" xil_pn:valueState="default"/>
261
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="processeur_timesim.vhd" xil_pn:valueState="default"/>
262
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="processeur_synthesis.vhd" xil_pn:valueState="default"/>
263
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="processeur_translate.vhd" xil_pn:valueState="default"/>
256 264
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
257 265
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
258 266
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -274,7 +282,7 @@
274 282
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
275 283
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
276 284
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
277
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="alu" xil_pn:valueState="default"/>
285
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="processeur" xil_pn:valueState="default"/>
278 286
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
279 287
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
280 288
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -297,8 +305,8 @@
297 305
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
298 306
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
299 307
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
300
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/bm_data_test" xil_pn:valueState="non-default"/>
301
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="non-default"/>
308
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
309
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="non-default"/>
302 310
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
303 311
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
304 312
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -316,7 +324,7 @@
316 324
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
317 325
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
318 326
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
319
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="default"/>
327
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="default"/>
320 328
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
321 329
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
322 330
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -366,7 +374,7 @@
366 374
     <!--                                                                                  -->
367 375
     <!-- The following properties are for internal use only. These should not be modified.-->
368 376
     <!--                                                                                  -->
369
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_data_test|behavior" xil_pn:valueState="non-default"/>
377
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
370 378
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
371 379
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
372 380
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

+ 1
- 1
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File

@@ -8,7 +8,7 @@
8 8
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9 9
 
10 10
 <messages>
11
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd&quot; into library work</arg>
11
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg>
12 12
 </msg>
13 13
 
14 14
 </messages>

+ 2
- 2
xilinx/ALU/alu_summary.html View File

@@ -72,9 +72,9 @@
72 72
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
73 73
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
74 74
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
75
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>jeu. avr. 15 10:54:50 2021</TD></TR>
75
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>ven. avr. 16 13:37:05 2021</TD></TR>
76 76
 </TABLE>
77 77
 
78 78
 
79
-<br><center><b>Date Generated:</b> 04/16/2021 - 12:24:04</center>
79
+<br><center><b>Date Generated:</b> 05/04/2021 - 12:54:59</center>
80 80
 </BODY></HTML>

+ 0
- 2
xilinx/ALU/bm_data_test_beh.prj View File

@@ -1,2 +0,0 @@
1
-vhdl work "bm.vhd"
2
-vhdl work "bm_data_test.vhd"

BIN
xilinx/ALU/bm_data_test_isim_beh.wdb View File


+ 3
- 3
xilinx/ALU/bm_instr.vhd View File

@@ -25,14 +25,14 @@ use IEEE.NUMERIC_STD.ALL;
25 25
 
26 26
 entity bm_instr is
27 27
     Port ( IN_addr : in  STD_LOGIC_VECTOR (7 downto 0);
28
-           OUT_data : out  STD_LOGIC_VECTOR (7 downto 0);
28
+           OUT_data : out  STD_LOGIC_VECTOR (31 downto 0);
29 29
            CLK : in  STD_LOGIC);
30 30
 end bm_instr;
31 31
 
32 32
 architecture Behavioral of bm_instr is
33 33
 
34
-type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
35
-signal instr_memory: mem := (1 => "00000001", others =>"00000000");
34
+type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
35
+signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
36 36
 
37 37
 begin
38 38
 

+ 2
- 2
xilinx/ALU/bm_instr_test.vhd View File

@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF bm_instr_test IS
42 42
     COMPONENT bm_instr
43 43
     PORT(
44 44
          IN_addr : IN  std_logic_vector(7 downto 0);
45
-         OUT_data : OUT  std_logic_vector(7 downto 0);
45
+         OUT_data : OUT  std_logic_vector(31 downto 0);
46 46
          CLK : IN  std_logic
47 47
         );
48 48
     END COMPONENT;
@@ -53,7 +53,7 @@ ARCHITECTURE behavior OF bm_instr_test IS
53 53
    signal CLK : std_logic := '0';
54 54
 
55 55
  	--Outputs
56
-   signal OUT_data : std_logic_vector(7 downto 0);
56
+   signal OUT_data : std_logic_vector(31 downto 0);
57 57
 
58 58
    -- Clock period definitions
59 59
    constant CLK_period : time := 10 ns;

+ 2
- 0
xilinx/ALU/bm_instr_test_beh.prj View File

@@ -0,0 +1,2 @@
1
+vhdl work "bm_instr.vhd"
2
+vhdl work "bm_instr_test.vhd"

BIN
xilinx/ALU/bm_instr_test_isim_beh.wdb View File


+ 26
- 20
xilinx/ALU/fuse.log View File

@@ -1,25 +1,31 @@
1
-Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj work.bm_data_test 
1
+Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj work.processeur 
2 2
 ISim O.87xd (signature 0x8ddf5b5d)
3 3
 Number of CPUs detected in this system: 12
4 4
 Turning on mult-threading, number of parallel sub-compilation jobs: 24 
5 5
 Determining compilation order of HDL files
6
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
7
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
8
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
6 9
 Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
7
-Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd" into library work
8
-Starting static elaboration
9
-Completed static elaboration
10
-Fuse Memory Usage: 98496 KB
11
-Fuse CPU Usage: 730 ms
12
-Compiling package standard
13
-Compiling package std_logic_1164
14
-Compiling package std_logic_arith
15
-Compiling package std_logic_unsigned
16
-Compiling package numeric_std
17
-Compiling architecture behavioral of entity bm_data [bm_data_default]
18
-Compiling architecture behavior of entity bm_data_test
19
-Time Resolution for simulation is 1ps.
20
-Waiting for 1 sub-compilation(s) to finish...
21
-Compiled 8 VHDL Units
22
-Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe
23
-Fuse Memory Usage: 1722956 KB
24
-Fuse CPU Usage: 850 ms
25
-GCC CPU Usage: 1640 ms
10
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
11
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
12
+ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <rst> is already declared in this region.
13
+ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <clk> is already declared in this region.
14
+ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <ip> is not declared in <bm_instr>
15
+ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <in_addr> has no actual or default value.
16
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <op_in> is not declared.
17
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <a_in> is not declared.
18
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <b_in> is not declared.
19
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <c_in> is not declared.
20
+ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <clk> is not declared in <pipeline>
21
+ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <b_lidi_out> is not declared in <br>
22
+ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <a_addr> has no actual or default value.
23
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <op_in> is not declared.
24
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <a_in> is not declared.
25
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <b_in> is not declared.
26
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <c_in> is not declared.
27
+ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <clk> is not declared in <pipeline>
28
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <a> is not declared.
29
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <b> is not declared.
30
+ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <ctrl_alu> is not declared.
31
+Sorry, too many errors..

+ 57
- 0
xilinx/ALU/fuse.xmsgs View File

@@ -5,5 +5,62 @@
5 5
      behavior or data corruption.  It is strongly advised that
6 6
      users do not edit the contents of this file. -->
7 7
 <messages>
8
+<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: &lt;<arg fmt="%s" index="1">rst</arg>&gt; is already declared in this region.
9
+</msg>
10
+
11
+<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: &lt;<arg fmt="%s" index="1">clk</arg>&gt; is already declared in this region.
12
+</msg>
13
+
14
+<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic &lt;<arg fmt="%s" index="1">ip</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">bm_instr</arg>&gt;
15
+</msg>
16
+
17
+<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal &lt;<arg fmt="%s" index="1">in_addr</arg>&gt; has no actual or default value.
18
+</msg>
19
+
20
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
21
+</msg>
22
+
23
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
24
+</msg>
25
+
26
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
27
+</msg>
28
+
29
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
30
+</msg>
31
+
32
+<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
33
+</msg>
34
+
35
+<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic &lt;<arg fmt="%s" index="1">b_lidi_out</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">br</arg>&gt;
36
+</msg>
37
+
38
+<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal &lt;<arg fmt="%s" index="1">a_addr</arg>&gt; has no actual or default value.
39
+</msg>
40
+
41
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
42
+</msg>
43
+
44
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
45
+</msg>
46
+
47
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
48
+</msg>
49
+
50
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
51
+</msg>
52
+
53
+<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
54
+</msg>
55
+
56
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: &lt;<arg fmt="%s" index="1">a</arg>&gt; is not declared.
57
+</msg>
58
+
59
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: &lt;<arg fmt="%s" index="1">b</arg>&gt; is not declared.
60
+</msg>
61
+
62
+<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: &lt;<arg fmt="%s" index="1">ctrl_alu</arg>&gt; is not declared.
63
+</msg>
64
+
8 65
 </messages>
9 66
 

+ 1
- 1
xilinx/ALU/fuseRelaunch.cmd View File

@@ -1 +1 @@
1
--intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj" "work.bm_data_test" 
1
+-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj" "work.processeur" 

+ 19
- 15
xilinx/ALU/iseconfig/ALU.projectmgr View File

@@ -9,13 +9,13 @@
9 9
          <ClosedNodesVersion>2</ClosedNodesVersion>
10 10
       </ClosedNodes>
11 11
       <SelectedItems>
12
-         <SelectedItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
12
+         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
13 13
       </SelectedItems>
14 14
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15 15
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000145000000020000000000000000000000000200000064ffffffff000000810000000300000002000001450000000100000003000000000000000100000003</ViewHeaderState>
16
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
17 17
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18
-      <CurrentItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
18
+      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
19 19
    </ItemView>
20 20
    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21 21
       <ClosedNodes>
@@ -23,13 +23,13 @@
23 23
          <ClosedNode>Design Utilities</ClosedNode>
24 24
       </ClosedNodes>
25 25
       <SelectedItems>
26
-         <SelectedItem/>
26
+         <SelectedItem></SelectedItem>
27 27
       </SelectedItems>
28 28
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
29 29
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
30 30
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
31 31
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
32
-      <CurrentItem/>
32
+      <CurrentItem></CurrentItem>
33 33
    </ItemView>
34 34
    <ItemView guiview="File" >
35 35
       <ClosedNodes>
@@ -68,35 +68,39 @@
68 68
       </SelectedItems>
69 69
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
70 70
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
71
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
71
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
72 72
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
73 73
       <CurrentItem></CurrentItem>
74 74
    </ItemView>
75 75
    <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
76 76
       <ClosedNodes>
77 77
          <ClosedNodesVersion>2</ClosedNodesVersion>
78
+         <ClosedNode>/alu_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|alu_test.vhd</ClosedNode>
79
+         <ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode>
80
+         <ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode>
81
+         <ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
78 82
       </ClosedNodes>
79 83
       <SelectedItems>
80
-         <SelectedItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</SelectedItem>
84
+         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
81 85
       </SelectedItems>
82 86
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
83 87
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
84
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000184000000020000000000000000000000000200000064ffffffff000000810000000300000002000001840000000100000003000000000000000100000003</ViewHeaderState>
88
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
85 89
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
86
-      <CurrentItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</CurrentItem>
90
+      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
87 91
    </ItemView>
88 92
    <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
89 93
       <ClosedNodes>
90 94
          <ClosedNodesVersion>1</ClosedNodesVersion>
91 95
       </ClosedNodes>
92 96
       <SelectedItems>
93
-         <SelectedItem>View Compilation Log</SelectedItem>
97
+         <SelectedItem></SelectedItem>
94 98
       </SelectedItems>
95 99
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
96 100
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
97
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
101
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
98 102
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
99
-      <CurrentItem>View Compilation Log</CurrentItem>
103
+      <CurrentItem></CurrentItem>
100 104
    </ItemView>
101 105
    <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
102 106
       <ClosedNodes>
@@ -107,7 +111,7 @@
107 111
       </SelectedItems>
108 112
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
109 113
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
110
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
114
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
111 115
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
112 116
       <CurrentItem>Simulate Behavioral Model</CurrentItem>
113 117
    </ItemView>
@@ -125,6 +129,6 @@
125 129
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
126 130
       <CurrentItem/>
127 131
    </ItemView>
128
-   <SourceProcessView>000000ff0000000000000002000001620000011b01000000040100000002</SourceProcessView>
129
-   <CurrentView>Implementation</CurrentView>
132
+   <SourceProcessView>000000ff0000000000000002000001a6000000db01000000040100000002</SourceProcessView>
133
+   <CurrentView>Behavioral Simulation</CurrentView>
130 134
 </Project>

+ 47
- 47
xilinx/ALU/iseconfig/alu.xreport View File

@@ -1,33 +1,33 @@
1 1
 <?xml version='1.0' encoding='UTF-8'?>
2 2
 <report-views version="2.0" >
3 3
  <header>
4
-  <DateModified>2021-04-16T12:24:04</DateModified>
5
-  <ModuleName>alu</ModuleName>
4
+  <DateModified>2021-05-04T15:10:56</DateModified>
5
+  <ModuleName>processeur</ModuleName>
6 6
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
8 8
   <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
9
-  <DateInitialized>2021-04-13T10:12:38</DateInitialized>
9
+  <DateInitialized>2021-05-04T13:11:55</DateInitialized>
10 10
   <EnableMessageFiltering>false</EnableMessageFiltering>
11 11
  </header>
12 12
  <body>
13 13
   <viewgroup label="Design Overview" >
14
-   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="alu_summary.html" label="Summary" >
14
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="processeur_summary.html" label="Summary" >
15 15
     <toc-item title="Design Overview" target="Design Overview" />
16 16
     <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
17 17
     <toc-item title="Performance Summary" target="Performance Summary" />
18 18
     <toc-item title="Failing Constraints" target="Failing Constraints" />
19 19
     <toc-item title="Detailed Reports" target="Detailed Reports" />
20 20
    </view>
21
-   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="alu_envsettings.html" label="System Settings" />
22
-   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="alu_map.xrpt" label="IOB Properties" />
23
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="alu_map.xrpt" label="Control Set Information" />
24
-   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="alu_map.xrpt" label="Module Level Utilization" />
25
-   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="alu.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
26
-   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="alu_par.xrpt" label="Pinout Report" />
27
-   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="alu_par.xrpt" label="Clock Report" />
28
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="alu.twx" label="Static Timing" />
29
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/fit/report.htm" label="CPLD Fitter Report" />
30
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/tim/report.htm" label="CPLD Timing Report" />
21
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="processeur_envsettings.html" label="System Settings" />
22
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="processeur_map.xrpt" label="IOB Properties" />
23
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="processeur_map.xrpt" label="Control Set Information" />
24
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="processeur_map.xrpt" label="Module Level Utilization" />
25
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="processeur.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
26
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="processeur_par.xrpt" label="Pinout Report" />
27
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="processeur_par.xrpt" label="Clock Report" />
28
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="processeur.twx" label="Static Timing" />
29
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/fit/report.htm" label="CPLD Fitter Report" />
30
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/tim/report.htm" label="CPLD Timing Report" />
31 31
   </viewgroup>
32 32
   <viewgroup label="XPS Errors and Warnings" >
33 33
    <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
@@ -38,7 +38,7 @@
38 38
    <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
39 39
    <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
40 40
    <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
41
-   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="alu.log" label="System Log File" />
41
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="processeur.log" label="System Log File" />
42 42
   </viewgroup>
43 43
   <viewgroup label="Errors and Warnings" >
44 44
    <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
@@ -54,7 +54,7 @@
54 54
    <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
55 55
   </viewgroup>
56 56
   <viewgroup label="Detailed Reports" >
57
-   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="alu.syr" label="Synthesis Report" >
57
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="processeur.syr" label="Synthesis Report" >
58 58
     <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
59 59
     <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
60 60
     <toc-item title="HDL Compilation" target="   HDL Compilation   " />
@@ -80,15 +80,15 @@
80 80
     <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
81 81
     <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
82 82
    </view>
83
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.srr" label="Synplify Report" />
84
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.prec_log" label="Precision Report" />
85
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="alu.bld" label="Translation Report" >
83
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.srr" label="Synplify Report" />
84
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.prec_log" label="Precision Report" />
85
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="processeur.bld" label="Translation Report" >
86 86
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
87 87
     <toc-item title="Command Line" target="Command Line:" />
88 88
     <toc-item title="Partition Status" target="Partition Implementation Status" />
89 89
     <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
90 90
    </view>
91
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="alu_map.mrp" label="Map Report" >
91
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="processeur_map.mrp" label="Map Report" >
92 92
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
93 93
     <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
94 94
     <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
@@ -104,7 +104,7 @@
104 104
     <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
105 105
     <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
106 106
    </view>
107
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="alu.par" label="Place and Route Report" >
107
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="processeur.par" label="Place and Route Report" >
108 108
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
109 109
     <toc-item title="Device Utilization" target="Device Utilization Summary:" />
110 110
     <toc-item title="Router Information" target="Starting Router" />
@@ -113,7 +113,7 @@
113 113
     <toc-item title="Timing Results" target="Timing Score:" />
114 114
     <toc-item title="Final Summary" target="Peak Memory Usage:" />
115 115
    </view>
116
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="alu.twr" label="Post-PAR Static Timing Report" >
116
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="processeur.twr" label="Post-PAR Static Timing Report" >
117 117
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
118 118
     <toc-item title="Timing Report Description" target="Device,package,speed:" />
119 119
     <toc-item title="Informational Messages" target="INFO:" />
@@ -124,22 +124,22 @@
124 124
     <toc-item title="Timing Summary" target="Timing summary:" />
125 125
     <toc-item title="Trace Settings" target="Trace Settings:" />
126 126
    </view>
127
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.rpt" label="CPLD Fitter Report (Text)" >
127
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.rpt" label="CPLD Fitter Report (Text)" >
128 128
     <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
129 129
     <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
130 130
     <toc-item title="Pin Resources" target="** Pin Resources **" />
131 131
     <toc-item title="Global Resources" target="** Global Control Resources **" />
132 132
    </view>
133
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.tim" label="CPLD Timing Report (Text)" >
133
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.tim" label="CPLD Timing Report (Text)" >
134 134
     <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
135 135
     <toc-item title="Performance Summary" target="Performance Summary:" />
136 136
    </view>
137
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="alu.pwr" label="Power Report" >
137
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="processeur.pwr" label="Power Report" >
138 138
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
139 139
     <toc-item title="Power summary" target="Power summary" />
140 140
     <toc-item title="Thermal summary" target="Thermal summary" />
141 141
    </view>
142
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="alu.bgn" label="Bitgen Report" >
142
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="processeur.bgn" label="Bitgen Report" >
143 143
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
144 144
     <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
145 145
     <toc-item title="Final Summary" target="DRC detected" />
@@ -147,20 +147,20 @@
147 147
   </viewgroup>
148 148
   <viewgroup label="Secondary Reports" >
149 149
    <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
150
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/alu_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
150
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/processeur_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
151 151
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
152 152
    </view>
153
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/alu_translate.nlf" label="Post-Translate Simulation Model Report" >
153
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/processeur_translate.nlf" label="Post-Translate Simulation Model Report" >
154 154
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
155 155
    </view>
156
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
157
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu_map.map" label="Map Log File" >
156
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
157
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur_map.map" label="Map Log File" >
158 158
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
159 159
     <toc-item title="Design Information" target="Design Information" />
160 160
     <toc-item title="Design Summary" target="Design Summary" />
161 161
    </view>
162 162
    <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
163
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.twr" label="Post-Map Static Timing Report" >
163
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.twr" label="Post-Map Static Timing Report" >
164 164
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
165 165
     <toc-item title="Timing Report Description" target="Device,package,speed:" />
166 166
     <toc-item title="Informational Messages" target="INFO:" />
@@ -171,43 +171,43 @@
171 171
     <toc-item title="Timing Summary" target="Timing summary:" />
172 172
     <toc-item title="Trace Settings" target="Trace Settings:" />
173 173
    </view>
174
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/alu_map.nlf" label="Post-Map Simulation Model Report" />
175
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_map.psr" label="Physical Synthesis Report" >
174
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/processeur_map.nlf" label="Post-Map Simulation Model Report" />
175
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_map.psr" label="Physical Synthesis Report" >
176 176
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
177 177
    </view>
178
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="alu_pad.txt" label="Pad Report" >
178
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="processeur_pad.txt" label="Pad Report" >
179 179
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
180 180
    </view>
181
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu.unroutes" label="Unroutes Report" >
181
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur.unroutes" label="Unroutes Report" >
182 182
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183 183
    </view>
184
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.tsi" label="Post-Map Constraints Interaction Report" >
184
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.tsi" label="Post-Map Constraints Interaction Report" >
185 185
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
186 186
    </view>
187
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.grf" label="Guide Results Report" />
188
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.dly" label="Asynchronous Delay Report" />
189
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.clk_rgn" label="Clock Region Report" />
190
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.tsi" label="Post-Place and Route Constraints Interaction Report" >
187
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.grf" label="Guide Results Report" />
188
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.dly" label="Asynchronous Delay Report" />
189
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.clk_rgn" label="Clock Region Report" />
190
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.tsi" label="Post-Place and Route Constraints Interaction Report" >
191 191
     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
192 192
    </view>
193
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
194
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/alu_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
195
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_sta.nlf" label="Primetime Netlist Report" >
193
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
194
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/processeur_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
195
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_sta.nlf" label="Primetime Netlist Report" >
196 196
     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
197 197
    </view>
198
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="alu.ibs" label="IBIS Model" >
198
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="processeur.ibs" label="IBIS Model" >
199 199
     <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
200 200
     <toc-item title="Component" target="Component " />
201 201
    </view>
202
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lck" label="Back-annotate Pin Report" >
202
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lck" label="Back-annotate Pin Report" >
203 203
     <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
204 204
     <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
205 205
    </view>
206
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lpc" label="Locked Pin Constraints" >
206
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lpc" label="Locked Pin Constraints" >
207 207
     <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
208 208
     <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
209 209
    </view>
210
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/alu_timesim.nlf" label="Post-Fit Simulation Model Report" />
210
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/processeur_timesim.nlf" label="Post-Fit Simulation Model Report" />
211 211
    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
212 212
    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
213 213
   </viewgroup>

+ 9
- 1
xilinx/ALU/isim.log View File

@@ -1,5 +1,5 @@
1 1
 ISim log file
2
-Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.wdb 
2
+Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb 
3 3
 ISim O.87xd (signature 0x8ddf5b5d)
4 4
 WARNING: A WEBPACK license was found.
5 5
 WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@@ -11,4 +11,12 @@ Time resolution is 1 ps
11 11
 # run 1000 ns
12 12
 Simulator is doing circuit initialization process.
13 13
 Finished circuit initialization process.
14
+ISim O.87xd (signature 0x8ddf5b5d)
15
+WARNING: A WEBPACK license was found.
16
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
17
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
18
+This is a Lite version of ISim.
19
+# run 1000 ns
20
+Simulator is doing circuit initialization process.
21
+Finished circuit initialization process.
14 22
 # exit 0

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe View File


+ 0
- 0
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimcrash.log View File


+ 0
- 29
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   bm_data_test_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  0
5
-     -socket  53487
6
-
7
-Fri Apr 16 13:35:42 2021
8
-
9
-
10
- Elaboration Time: 0.01 sec
11
-
12
- Current Memory Usage: 183.046 Meg
13
-
14
- Total Signals          : 13
15
- Total Nets             : 2075
16
- Total Signal Drivers   : 7
17
- Total Blocks           : 6
18
- Total Primitive Blocks : 5
19
- Total Processes        : 3
20
- Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 2577
22
-Total Line Count : 27
23
-
24
- Total Simulation Time: 0.1 sec
25
-
26
- Current Memory Usage: 258.548 Meg
27
-
28
-Fri Apr 16 13:37:04 2021
29
-

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 0
- 181
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c View File

@@ -1,181 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
25
-extern char *IEEE_P_2592010699;
26
-extern char *IEEE_P_1242562249;
27
-
28
-int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
29
-unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
30
-
31
-
32
-static void work_a_1466808984_3212880686_p_0(char *t0)
33
-{
34
-    char *t1;
35
-    char *t2;
36
-    char *t3;
37
-    unsigned char t4;
38
-    char *t5;
39
-    unsigned char t6;
40
-    char *t7;
41
-    int t8;
42
-    int t9;
43
-    unsigned int t10;
44
-    unsigned int t11;
45
-    unsigned int t12;
46
-    char *t13;
47
-    char *t14;
48
-    char *t15;
49
-    char *t16;
50
-    char *t17;
51
-    char *t18;
52
-    unsigned char t19;
53
-
54
-LAB0:    t1 = (t0 + 3144U);
55
-    t2 = *((char **)t1);
56
-    if (t2 == 0)
57
-        goto LAB2;
58
-
59
-LAB3:    goto *t2;
60
-
61
-LAB2:    xsi_set_current_line(42, ng0);
62
-
63
-LAB6:    t2 = (t0 + 3464);
64
-    *((int *)t2) = 1;
65
-    *((char **)t1) = &&LAB7;
66
-
67
-LAB1:    return;
68
-LAB4:    t5 = (t0 + 3464);
69
-    *((int *)t5) = 0;
70
-    xsi_set_current_line(43, ng0);
71
-    t2 = (t0 + 1352U);
72
-    t3 = *((char **)t2);
73
-    t4 = *((unsigned char *)t3);
74
-    t6 = (t4 == (unsigned char)3);
75
-    if (t6 != 0)
76
-        goto LAB8;
77
-
78
-LAB10:    xsi_set_current_line(46, ng0);
79
-    t2 = (t0 + 1192U);
80
-    t3 = *((char **)t2);
81
-    t2 = (t0 + 1032U);
82
-    t5 = *((char **)t2);
83
-    t2 = (t0 + 5968U);
84
-    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
85
-    t9 = (t8 - 0);
86
-    t10 = (t9 * 1);
87
-    t11 = (8U * t10);
88
-    t12 = (0U + t11);
89
-    t7 = (t0 + 3608);
90
-    t13 = (t7 + 56U);
91
-    t14 = *((char **)t13);
92
-    t15 = (t14 + 56U);
93
-    t16 = *((char **)t15);
94
-    memcpy(t16, t3, 8U);
95
-    xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
96
-
97
-LAB9:    xsi_set_current_line(48, ng0);
98
-    t2 = (t0 + 1512U);
99
-    t3 = *((char **)t2);
100
-    t4 = *((unsigned char *)t3);
101
-    t6 = (t4 == (unsigned char)2);
102
-    if (t6 != 0)
103
-        goto LAB11;
104
-
105
-LAB13:
106
-LAB12:    goto LAB2;
107
-
108
-LAB5:    t3 = (t0 + 1632U);
109
-    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
110
-    if (t4 == 1)
111
-        goto LAB4;
112
-    else
113
-        goto LAB6;
114
-
115
-LAB7:    goto LAB5;
116
-
117
-LAB8:    xsi_set_current_line(44, ng0);
118
-    t2 = (t0 + 1992U);
119
-    t5 = *((char **)t2);
120
-    t2 = (t0 + 1032U);
121
-    t7 = *((char **)t2);
122
-    t2 = (t0 + 5968U);
123
-    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
124
-    t9 = (t8 - 0);
125
-    t10 = (t9 * 1);
126
-    xsi_vhdl_check_range_of_index(0, 255, 1, t8);
127
-    t11 = (8U * t10);
128
-    t12 = (0 + t11);
129
-    t13 = (t5 + t12);
130
-    t14 = (t0 + 3544);
131
-    t15 = (t14 + 56U);
132
-    t16 = *((char **)t15);
133
-    t17 = (t16 + 56U);
134
-    t18 = *((char **)t17);
135
-    memcpy(t18, t13, 8U);
136
-    xsi_driver_first_trans_fast_port(t14);
137
-    goto LAB9;
138
-
139
-LAB11:    xsi_set_current_line(49, ng0);
140
-    t2 = xsi_get_transient_memory(2048U);
141
-    memset(t2, 0, 2048U);
142
-    t5 = t2;
143
-    t7 = (t0 + 8123);
144
-    t19 = (8U != 0);
145
-    if (t19 == 1)
146
-        goto LAB14;
147
-
148
-LAB15:    t14 = (t0 + 3608);
149
-    t15 = (t14 + 56U);
150
-    t16 = *((char **)t15);
151
-    t17 = (t16 + 56U);
152
-    t18 = *((char **)t17);
153
-    memcpy(t18, t2, 2048U);
154
-    xsi_driver_first_trans_fast(t14);
155
-    xsi_set_current_line(50, ng0);
156
-    t2 = xsi_get_transient_memory(8U);
157
-    memset(t2, 0, 8U);
158
-    t3 = t2;
159
-    memset(t3, (unsigned char)2, 8U);
160
-    t5 = (t0 + 3544);
161
-    t7 = (t5 + 56U);
162
-    t13 = *((char **)t7);
163
-    t14 = (t13 + 56U);
164
-    t15 = *((char **)t14);
165
-    memcpy(t15, t2, 8U);
166
-    xsi_driver_first_trans_fast_port(t5);
167
-    goto LAB12;
168
-
169
-LAB14:    t10 = (2048U / 8U);
170
-    xsi_mem_set_data(t5, t7, 8U, t10);
171
-    goto LAB15;
172
-
173
-}
174
-
175
-
176
-extern void work_a_1466808984_3212880686_init()
177
-{
178
-	static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
179
-	xsi_register_didat("work_a_1466808984_3212880686", "isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
180
-	xsi_register_executes(pe);
181
-}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o View File


+ 0
- 288
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.c View File

@@ -1,288 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd";
25
-
26
-
27
-
28
-static void work_a_2533693612_2372691052_p_0(char *t0)
29
-{
30
-    char *t1;
31
-    char *t2;
32
-    char *t3;
33
-    char *t4;
34
-    char *t5;
35
-    char *t6;
36
-    int64 t7;
37
-    int64 t8;
38
-
39
-LAB0:    t1 = (t0 + 3104U);
40
-    t2 = *((char **)t1);
41
-    if (t2 == 0)
42
-        goto LAB2;
43
-
44
-LAB3:    goto *t2;
45
-
46
-LAB2:    xsi_set_current_line(82, ng0);
47
-    t2 = (t0 + 3736);
48
-    t3 = (t2 + 56U);
49
-    t4 = *((char **)t3);
50
-    t5 = (t4 + 56U);
51
-    t6 = *((char **)t5);
52
-    *((unsigned char *)t6) = (unsigned char)2;
53
-    xsi_driver_first_trans_fast(t2);
54
-    xsi_set_current_line(83, ng0);
55
-    t2 = (t0 + 2128U);
56
-    t3 = *((char **)t2);
57
-    t7 = *((int64 *)t3);
58
-    t8 = (t7 / 2);
59
-    t2 = (t0 + 2912);
60
-    xsi_process_wait(t2, t8);
61
-
62
-LAB6:    *((char **)t1) = &&LAB7;
63
-
64
-LAB1:    return;
65
-LAB4:    xsi_set_current_line(84, ng0);
66
-    t2 = (t0 + 3736);
67
-    t3 = (t2 + 56U);
68
-    t4 = *((char **)t3);
69
-    t5 = (t4 + 56U);
70
-    t6 = *((char **)t5);
71
-    *((unsigned char *)t6) = (unsigned char)3;
72
-    xsi_driver_first_trans_fast(t2);
73
-    xsi_set_current_line(85, ng0);
74
-    t2 = (t0 + 2128U);
75
-    t3 = *((char **)t2);
76
-    t7 = *((int64 *)t3);
77
-    t8 = (t7 / 2);
78
-    t2 = (t0 + 2912);
79
-    xsi_process_wait(t2, t8);
80
-
81
-LAB10:    *((char **)t1) = &&LAB11;
82
-    goto LAB1;
83
-
84
-LAB5:    goto LAB4;
85
-
86
-LAB7:    goto LAB5;
87
-
88
-LAB8:    goto LAB2;
89
-
90
-LAB9:    goto LAB8;
91
-
92
-LAB11:    goto LAB9;
93
-
94
-}
95
-
96
-static void work_a_2533693612_2372691052_p_1(char *t0)
97
-{
98
-    char *t1;
99
-    char *t2;
100
-    int64 t3;
101
-    char *t4;
102
-    int64 t5;
103
-    char *t6;
104
-    char *t7;
105
-    char *t8;
106
-    char *t9;
107
-    char *t10;
108
-
109
-LAB0:    t1 = (t0 + 3352U);
110
-    t2 = *((char **)t1);
111
-    if (t2 == 0)
112
-        goto LAB2;
113
-
114
-LAB3:    goto *t2;
115
-
116
-LAB2:    xsi_set_current_line(93, ng0);
117
-    t3 = (100 * 1000LL);
118
-    t2 = (t0 + 3160);
119
-    xsi_process_wait(t2, t3);
120
-
121
-LAB6:    *((char **)t1) = &&LAB7;
122
-
123
-LAB1:    return;
124
-LAB4:    xsi_set_current_line(94, ng0);
125
-    t2 = (t0 + 2128U);
126
-    t4 = *((char **)t2);
127
-    t3 = *((int64 *)t4);
128
-    t5 = (t3 * 10);
129
-    t2 = (t0 + 3160);
130
-    xsi_process_wait(t2, t5);
131
-
132
-LAB10:    *((char **)t1) = &&LAB11;
133
-    goto LAB1;
134
-
135
-LAB5:    goto LAB4;
136
-
137
-LAB7:    goto LAB5;
138
-
139
-LAB8:    xsi_set_current_line(95, ng0);
140
-    t2 = (t0 + 3800);
141
-    t4 = (t2 + 56U);
142
-    t6 = *((char **)t4);
143
-    t7 = (t6 + 56U);
144
-    t8 = *((char **)t7);
145
-    *((unsigned char *)t8) = (unsigned char)3;
146
-    xsi_driver_first_trans_fast(t2);
147
-    xsi_set_current_line(96, ng0);
148
-    t2 = (t0 + 6536);
149
-    t6 = (t0 + 3864);
150
-    t7 = (t6 + 56U);
151
-    t8 = *((char **)t7);
152
-    t9 = (t8 + 56U);
153
-    t10 = *((char **)t9);
154
-    memcpy(t10, t2, 8U);
155
-    xsi_driver_first_trans_fast(t6);
156
-    xsi_set_current_line(97, ng0);
157
-    t2 = (t0 + 6544);
158
-    t6 = (t0 + 3928);
159
-    t7 = (t6 + 56U);
160
-    t8 = *((char **)t7);
161
-    t9 = (t8 + 56U);
162
-    t10 = *((char **)t9);
163
-    memcpy(t10, t2, 8U);
164
-    xsi_driver_first_trans_fast(t6);
165
-    xsi_set_current_line(98, ng0);
166
-    t3 = (30 * 1000LL);
167
-    t2 = (t0 + 3160);
168
-    xsi_process_wait(t2, t3);
169
-
170
-LAB14:    *((char **)t1) = &&LAB15;
171
-    goto LAB1;
172
-
173
-LAB9:    goto LAB8;
174
-
175
-LAB11:    goto LAB9;
176
-
177
-LAB12:    xsi_set_current_line(99, ng0);
178
-    t2 = (t0 + 6552);
179
-    t6 = (t0 + 3864);
180
-    t7 = (t6 + 56U);
181
-    t8 = *((char **)t7);
182
-    t9 = (t8 + 56U);
183
-    t10 = *((char **)t9);
184
-    memcpy(t10, t2, 8U);
185
-    xsi_driver_first_trans_fast(t6);
186
-    xsi_set_current_line(100, ng0);
187
-    t2 = (t0 + 6560);
188
-    t6 = (t0 + 3928);
189
-    t7 = (t6 + 56U);
190
-    t8 = *((char **)t7);
191
-    t9 = (t8 + 56U);
192
-    t10 = *((char **)t9);
193
-    memcpy(t10, t2, 8U);
194
-    xsi_driver_first_trans_fast(t6);
195
-    xsi_set_current_line(102, ng0);
196
-    t2 = (t0 + 3992);
197
-    t4 = (t2 + 56U);
198
-    t6 = *((char **)t4);
199
-    t7 = (t6 + 56U);
200
-    t8 = *((char **)t7);
201
-    *((unsigned char *)t8) = (unsigned char)3;
202
-    xsi_driver_first_trans_fast(t2);
203
-    xsi_set_current_line(103, ng0);
204
-    t3 = (30 * 1000LL);
205
-    t2 = (t0 + 3160);
206
-    xsi_process_wait(t2, t3);
207
-
208
-LAB18:    *((char **)t1) = &&LAB19;
209
-    goto LAB1;
210
-
211
-LAB13:    goto LAB12;
212
-
213
-LAB15:    goto LAB13;
214
-
215
-LAB16:    xsi_set_current_line(104, ng0);
216
-    t2 = (t0 + 6568);
217
-    t6 = (t0 + 3864);
218
-    t7 = (t6 + 56U);
219
-    t8 = *((char **)t7);
220
-    t9 = (t8 + 56U);
221
-    t10 = *((char **)t9);
222
-    memcpy(t10, t2, 8U);
223
-    xsi_driver_first_trans_fast(t6);
224
-    xsi_set_current_line(105, ng0);
225
-    t3 = (30 * 1000LL);
226
-    t2 = (t0 + 3160);
227
-    xsi_process_wait(t2, t3);
228
-
229
-LAB22:    *((char **)t1) = &&LAB23;
230
-    goto LAB1;
231
-
232
-LAB17:    goto LAB16;
233
-
234
-LAB19:    goto LAB17;
235
-
236
-LAB20:    xsi_set_current_line(106, ng0);
237
-    t2 = (t0 + 6576);
238
-    t6 = (t0 + 3864);
239
-    t7 = (t6 + 56U);
240
-    t8 = *((char **)t7);
241
-    t9 = (t8 + 56U);
242
-    t10 = *((char **)t9);
243
-    memcpy(t10, t2, 8U);
244
-    xsi_driver_first_trans_fast(t6);
245
-    xsi_set_current_line(108, ng0);
246
-    t3 = (30 * 1000LL);
247
-    t2 = (t0 + 3160);
248
-    xsi_process_wait(t2, t3);
249
-
250
-LAB26:    *((char **)t1) = &&LAB27;
251
-    goto LAB1;
252
-
253
-LAB21:    goto LAB20;
254
-
255
-LAB23:    goto LAB21;
256
-
257
-LAB24:    xsi_set_current_line(109, ng0);
258
-    t2 = (t0 + 3800);
259
-    t4 = (t2 + 56U);
260
-    t6 = *((char **)t4);
261
-    t7 = (t6 + 56U);
262
-    t8 = *((char **)t7);
263
-    *((unsigned char *)t8) = (unsigned char)2;
264
-    xsi_driver_first_trans_fast(t2);
265
-    xsi_set_current_line(111, ng0);
266
-
267
-LAB30:    *((char **)t1) = &&LAB31;
268
-    goto LAB1;
269
-
270
-LAB25:    goto LAB24;
271
-
272
-LAB27:    goto LAB25;
273
-
274
-LAB28:    goto LAB2;
275
-
276
-LAB29:    goto LAB28;
277
-
278
-LAB31:    goto LAB29;
279
-
280
-}
281
-
282
-
283
-extern void work_a_2533693612_2372691052_init()
284
-{
285
-	static char *pe[] = {(void *)work_a_2533693612_2372691052_p_0,(void *)work_a_2533693612_2372691052_p_1};
286
-	xsi_register_didat("work_a_2533693612_2372691052", "isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat");
287
-	xsi_register_executes(pe);
288
-}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.lin64.o View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe View File


xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log View File


+ 29
- 0
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log View File

@@ -0,0 +1,29 @@
1
+Command line:
2
+   bm_instr_test_isim_beh.exe
3
+     -simmode  gui
4
+     -simrunnum  0
5
+     -socket  58939
6
+
7
+Tue May  4 13:10:22 2021
8
+
9
+
10
+ Elaboration Time: 0.01 sec
11
+
12
+ Current Memory Usage: 187.593 Meg
13
+
14
+ Total Signals          : 7
15
+ Total Nets             : 8233
16
+ Total Signal Drivers   : 3
17
+ Total Blocks           : 6
18
+ Total Primitive Blocks : 5
19
+ Total Processes        : 3
20
+ Total Traceable Variables  : 16
21
+ Total Scalar Nets and Variables : 8735
22
+Total Line Count : 11
23
+
24
+ Total Simulation Time: 0.03 sec
25
+
26
+ Current Memory Usage: 263.094 Meg
27
+
28
+Tue May  4 13:11:03 2021
29
+

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 84
- 0
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File

@@ -0,0 +1,84 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd";
25
+extern char *IEEE_P_1242562249;
26
+
27
+int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
28
+
29
+
30
+static void work_a_1802466774_3212880686_p_0(char *t0)
31
+{
32
+    char *t1;
33
+    char *t2;
34
+    char *t3;
35
+    int t4;
36
+    int t5;
37
+    unsigned int t6;
38
+    unsigned int t7;
39
+    unsigned int t8;
40
+    char *t9;
41
+    char *t10;
42
+    char *t11;
43
+    char *t12;
44
+    char *t13;
45
+    char *t14;
46
+    char *t15;
47
+
48
+LAB0:    xsi_set_current_line(39, ng0);
49
+
50
+LAB3:    t1 = (t0 + 1512U);
51
+    t2 = *((char **)t1);
52
+    t1 = (t0 + 1032U);
53
+    t3 = *((char **)t1);
54
+    t1 = (t0 + 5224U);
55
+    t4 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t3, t1);
56
+    t5 = (t4 - 0);
57
+    t6 = (t5 * 1);
58
+    xsi_vhdl_check_range_of_index(0, 255, 1, t4);
59
+    t7 = (32U * t6);
60
+    t8 = (0 + t7);
61
+    t9 = (t2 + t8);
62
+    t10 = (t0 + 3064);
63
+    t11 = (t10 + 56U);
64
+    t12 = *((char **)t11);
65
+    t13 = (t12 + 56U);
66
+    t14 = *((char **)t13);
67
+    memcpy(t14, t9, 32U);
68
+    xsi_driver_first_trans_fast_port(t10);
69
+
70
+LAB2:    t15 = (t0 + 2984);
71
+    *((int *)t15) = 1;
72
+
73
+LAB1:    return;
74
+LAB4:    goto LAB2;
75
+
76
+}
77
+
78
+
79
+extern void work_a_1802466774_3212880686_init()
80
+{
81
+	static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
82
+	xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
83
+	xsi_register_executes(pe);
84
+}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o View File


+ 192
- 0
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c View File

@@ -0,0 +1,192 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
25
+
26
+
27
+
28
+static void work_a_4060154216_2372691052_p_0(char *t0)
29
+{
30
+    char *t1;
31
+    char *t2;
32
+    char *t3;
33
+    char *t4;
34
+    char *t5;
35
+    char *t6;
36
+    int64 t7;
37
+    int64 t8;
38
+
39
+LAB0:    t1 = (t0 + 2624U);
40
+    t2 = *((char **)t1);
41
+    if (t2 == 0)
42
+        goto LAB2;
43
+
44
+LAB3:    goto *t2;
45
+
46
+LAB2:    xsi_set_current_line(73, ng0);
47
+    t2 = (t0 + 3256);
48
+    t3 = (t2 + 56U);
49
+    t4 = *((char **)t3);
50
+    t5 = (t4 + 56U);
51
+    t6 = *((char **)t5);
52
+    *((unsigned char *)t6) = (unsigned char)2;
53
+    xsi_driver_first_trans_fast(t2);
54
+    xsi_set_current_line(74, ng0);
55
+    t2 = (t0 + 1648U);
56
+    t3 = *((char **)t2);
57
+    t7 = *((int64 *)t3);
58
+    t8 = (t7 / 2);
59
+    t2 = (t0 + 2432);
60
+    xsi_process_wait(t2, t8);
61
+
62
+LAB6:    *((char **)t1) = &&LAB7;
63
+
64
+LAB1:    return;
65
+LAB4:    xsi_set_current_line(75, ng0);
66
+    t2 = (t0 + 3256);
67
+    t3 = (t2 + 56U);
68
+    t4 = *((char **)t3);
69
+    t5 = (t4 + 56U);
70
+    t6 = *((char **)t5);
71
+    *((unsigned char *)t6) = (unsigned char)3;
72
+    xsi_driver_first_trans_fast(t2);
73
+    xsi_set_current_line(76, ng0);
74
+    t2 = (t0 + 1648U);
75
+    t3 = *((char **)t2);
76
+    t7 = *((int64 *)t3);
77
+    t8 = (t7 / 2);
78
+    t2 = (t0 + 2432);
79
+    xsi_process_wait(t2, t8);
80
+
81
+LAB10:    *((char **)t1) = &&LAB11;
82
+    goto LAB1;
83
+
84
+LAB5:    goto LAB4;
85
+
86
+LAB7:    goto LAB5;
87
+
88
+LAB8:    goto LAB2;
89
+
90
+LAB9:    goto LAB8;
91
+
92
+LAB11:    goto LAB9;
93
+
94
+}
95
+
96
+static void work_a_4060154216_2372691052_p_1(char *t0)
97
+{
98
+    char *t1;
99
+    char *t2;
100
+    int64 t3;
101
+    char *t4;
102
+    int64 t5;
103
+    char *t6;
104
+    char *t7;
105
+    char *t8;
106
+    char *t9;
107
+    char *t10;
108
+
109
+LAB0:    t1 = (t0 + 2872U);
110
+    t2 = *((char **)t1);
111
+    if (t2 == 0)
112
+        goto LAB2;
113
+
114
+LAB3:    goto *t2;
115
+
116
+LAB2:    xsi_set_current_line(84, ng0);
117
+    t3 = (100 * 1000LL);
118
+    t2 = (t0 + 2680);
119
+    xsi_process_wait(t2, t3);
120
+
121
+LAB6:    *((char **)t1) = &&LAB7;
122
+
123
+LAB1:    return;
124
+LAB4:    xsi_set_current_line(86, ng0);
125
+    t2 = (t0 + 1648U);
126
+    t4 = *((char **)t2);
127
+    t3 = *((int64 *)t4);
128
+    t5 = (t3 * 10);
129
+    t2 = (t0 + 2680);
130
+    xsi_process_wait(t2, t5);
131
+
132
+LAB10:    *((char **)t1) = &&LAB11;
133
+    goto LAB1;
134
+
135
+LAB5:    goto LAB4;
136
+
137
+LAB7:    goto LAB5;
138
+
139
+LAB8:    xsi_set_current_line(88, ng0);
140
+    t2 = (t0 + 5568);
141
+    t6 = (t0 + 3320);
142
+    t7 = (t6 + 56U);
143
+    t8 = *((char **)t7);
144
+    t9 = (t8 + 56U);
145
+    t10 = *((char **)t9);
146
+    memcpy(t10, t2, 8U);
147
+    xsi_driver_first_trans_fast(t6);
148
+    xsi_set_current_line(89, ng0);
149
+    t3 = (100 * 1000LL);
150
+    t2 = (t0 + 2680);
151
+    xsi_process_wait(t2, t3);
152
+
153
+LAB14:    *((char **)t1) = &&LAB15;
154
+    goto LAB1;
155
+
156
+LAB9:    goto LAB8;
157
+
158
+LAB11:    goto LAB9;
159
+
160
+LAB12:    xsi_set_current_line(91, ng0);
161
+    t2 = (t0 + 5576);
162
+    t6 = (t0 + 3320);
163
+    t7 = (t6 + 56U);
164
+    t8 = *((char **)t7);
165
+    t9 = (t8 + 56U);
166
+    t10 = *((char **)t9);
167
+    memcpy(t10, t2, 8U);
168
+    xsi_driver_first_trans_fast(t6);
169
+    xsi_set_current_line(94, ng0);
170
+
171
+LAB18:    *((char **)t1) = &&LAB19;
172
+    goto LAB1;
173
+
174
+LAB13:    goto LAB12;
175
+
176
+LAB15:    goto LAB13;
177
+
178
+LAB16:    goto LAB2;
179
+
180
+LAB17:    goto LAB16;
181
+
182
+LAB19:    goto LAB17;
183
+
184
+}
185
+
186
+
187
+extern void work_a_4060154216_2372691052_init()
188
+{
189
+	static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
190
+	xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
191
+	xsi_register_executes(pe);
192
+}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o View File


xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.c → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c View File

@@ -31,11 +31,11 @@ int main(int argc, char **argv)
31 31
     ieee_p_3499444699_init();
32 32
     ieee_p_3620187407_init();
33 33
     ieee_p_1242562249_init();
34
-    work_a_1466808984_3212880686_init();
35
-    work_a_2533693612_2372691052_init();
34
+    work_a_1802466774_3212880686_init();
35
+    work_a_4060154216_2372691052_init();
36 36
 
37 37
 
38
-    xsi_register_tops("work_a_2533693612_2372691052");
38
+    xsi_register_tops("work_a_4060154216_2372691052");
39 39
 
40 40
     IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
41 41
     xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.lin64.o → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe View File


+ 0
- 29
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   br_test_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  0
5
-     -socket  44223
6
-
7
-Fri Apr 16 13:26:05 2021
8
-
9
-
10
- Elaboration Time: 0 sec
11
-
12
- Current Memory Usage: 181.682 Meg
13
-
14
- Total Signals          : 19
15
- Total Nets             : 167
16
- Total Signal Drivers   : 10
17
- Total Blocks           : 6
18
- Total Primitive Blocks : 5
19
- Total Processes        : 5
20
- Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 669
22
-Total Line Count : 33
23
-
24
- Total Simulation Time: 0.01 sec
25
-
26
- Current Memory Usage: 257.184 Meg
27
-
28
-Fri Apr 16 13:26:10 2021
29
-

BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 0
- 345
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.c View File

@@ -1,345 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd";
25
-
26
-
27
-
28
-static void work_a_3692836482_2372691052_p_0(char *t0)
29
-{
30
-    char *t1;
31
-    char *t2;
32
-    char *t3;
33
-    char *t4;
34
-    char *t5;
35
-    char *t6;
36
-    int64 t7;
37
-    int64 t8;
38
-
39
-LAB0:    t1 = (t0 + 3584U);
40
-    t2 = *((char **)t1);
41
-    if (t2 == 0)
42
-        goto LAB2;
43
-
44
-LAB3:    goto *t2;
45
-
46
-LAB2:    xsi_set_current_line(91, ng0);
47
-    t2 = (t0 + 4216);
48
-    t3 = (t2 + 56U);
49
-    t4 = *((char **)t3);
50
-    t5 = (t4 + 56U);
51
-    t6 = *((char **)t5);
52
-    *((unsigned char *)t6) = (unsigned char)2;
53
-    xsi_driver_first_trans_fast(t2);
54
-    xsi_set_current_line(92, ng0);
55
-    t2 = (t0 + 2608U);
56
-    t3 = *((char **)t2);
57
-    t7 = *((int64 *)t3);
58
-    t8 = (t7 / 2);
59
-    t2 = (t0 + 3392);
60
-    xsi_process_wait(t2, t8);
61
-
62
-LAB6:    *((char **)t1) = &&LAB7;
63
-
64
-LAB1:    return;
65
-LAB4:    xsi_set_current_line(93, ng0);
66
-    t2 = (t0 + 4216);
67
-    t3 = (t2 + 56U);
68
-    t4 = *((char **)t3);
69
-    t5 = (t4 + 56U);
70
-    t6 = *((char **)t5);
71
-    *((unsigned char *)t6) = (unsigned char)3;
72
-    xsi_driver_first_trans_fast(t2);
73
-    xsi_set_current_line(94, ng0);
74
-    t2 = (t0 + 2608U);
75
-    t3 = *((char **)t2);
76
-    t7 = *((int64 *)t3);
77
-    t8 = (t7 / 2);
78
-    t2 = (t0 + 3392);
79
-    xsi_process_wait(t2, t8);
80
-
81
-LAB10:    *((char **)t1) = &&LAB11;
82
-    goto LAB1;
83
-
84
-LAB5:    goto LAB4;
85
-
86
-LAB7:    goto LAB5;
87
-
88
-LAB8:    goto LAB2;
89
-
90
-LAB9:    goto LAB8;
91
-
92
-LAB11:    goto LAB9;
93
-
94
-}
95
-
96
-static void work_a_3692836482_2372691052_p_1(char *t0)
97
-{
98
-    char *t1;
99
-    char *t2;
100
-    int64 t3;
101
-    char *t4;
102
-    int64 t5;
103
-    char *t6;
104
-    char *t7;
105
-    char *t8;
106
-    char *t9;
107
-    char *t10;
108
-
109
-LAB0:    t1 = (t0 + 3832U);
110
-    t2 = *((char **)t1);
111
-    if (t2 == 0)
112
-        goto LAB2;
113
-
114
-LAB3:    goto *t2;
115
-
116
-LAB2:    xsi_set_current_line(102, ng0);
117
-    t3 = (100 * 1000LL);
118
-    t2 = (t0 + 3640);
119
-    xsi_process_wait(t2, t3);
120
-
121
-LAB6:    *((char **)t1) = &&LAB7;
122
-
123
-LAB1:    return;
124
-LAB4:    xsi_set_current_line(104, ng0);
125
-    t2 = (t0 + 2608U);
126
-    t4 = *((char **)t2);
127
-    t3 = *((int64 *)t4);
128
-    t5 = (t3 * 10);
129
-    t2 = (t0 + 3640);
130
-    xsi_process_wait(t2, t5);
131
-
132
-LAB10:    *((char **)t1) = &&LAB11;
133
-    goto LAB1;
134
-
135
-LAB5:    goto LAB4;
136
-
137
-LAB7:    goto LAB5;
138
-
139
-LAB8:    xsi_set_current_line(106, ng0);
140
-    t2 = (t0 + 4280);
141
-    t4 = (t2 + 56U);
142
-    t6 = *((char **)t4);
143
-    t7 = (t6 + 56U);
144
-    t8 = *((char **)t7);
145
-    *((unsigned char *)t8) = (unsigned char)3;
146
-    xsi_driver_first_trans_fast(t2);
147
-    xsi_set_current_line(108, ng0);
148
-    t3 = (30 * 1000LL);
149
-    t2 = (t0 + 3640);
150
-    xsi_process_wait(t2, t3);
151
-
152
-LAB14:    *((char **)t1) = &&LAB15;
153
-    goto LAB1;
154
-
155
-LAB9:    goto LAB8;
156
-
157
-LAB11:    goto LAB9;
158
-
159
-LAB12:    xsi_set_current_line(109, ng0);
160
-    t2 = (t0 + 7400);
161
-    t6 = (t0 + 4344);
162
-    t7 = (t6 + 56U);
163
-    t8 = *((char **)t7);
164
-    t9 = (t8 + 56U);
165
-    t10 = *((char **)t9);
166
-    memcpy(t10, t2, 8U);
167
-    xsi_driver_first_trans_fast(t6);
168
-    xsi_set_current_line(110, ng0);
169
-    t2 = (t0 + 7408);
170
-    t6 = (t0 + 4408);
171
-    t7 = (t6 + 56U);
172
-    t8 = *((char **)t7);
173
-    t9 = (t8 + 56U);
174
-    t10 = *((char **)t9);
175
-    memcpy(t10, t2, 4U);
176
-    xsi_driver_first_trans_fast(t6);
177
-    xsi_set_current_line(111, ng0);
178
-    t2 = (t0 + 4472);
179
-    t4 = (t2 + 56U);
180
-    t6 = *((char **)t4);
181
-    t7 = (t6 + 56U);
182
-    t8 = *((char **)t7);
183
-    *((unsigned char *)t8) = (unsigned char)3;
184
-    xsi_driver_first_trans_fast(t2);
185
-    xsi_set_current_line(112, ng0);
186
-    t3 = (30 * 1000LL);
187
-    t2 = (t0 + 3640);
188
-    xsi_process_wait(t2, t3);
189
-
190
-LAB18:    *((char **)t1) = &&LAB19;
191
-    goto LAB1;
192
-
193
-LAB13:    goto LAB12;
194
-
195
-LAB15:    goto LAB13;
196
-
197
-LAB16:    xsi_set_current_line(113, ng0);
198
-    t2 = (t0 + 7412);
199
-    t6 = (t0 + 4408);
200
-    t7 = (t6 + 56U);
201
-    t8 = *((char **)t7);
202
-    t9 = (t8 + 56U);
203
-    t10 = *((char **)t9);
204
-    memcpy(t10, t2, 4U);
205
-    xsi_driver_first_trans_fast(t6);
206
-    xsi_set_current_line(114, ng0);
207
-    t2 = (t0 + 7416);
208
-    t6 = (t0 + 4344);
209
-    t7 = (t6 + 56U);
210
-    t8 = *((char **)t7);
211
-    t9 = (t8 + 56U);
212
-    t10 = *((char **)t9);
213
-    memcpy(t10, t2, 8U);
214
-    xsi_driver_first_trans_fast(t6);
215
-    xsi_set_current_line(115, ng0);
216
-    t3 = (30 * 1000LL);
217
-    t2 = (t0 + 3640);
218
-    xsi_process_wait(t2, t3);
219
-
220
-LAB22:    *((char **)t1) = &&LAB23;
221
-    goto LAB1;
222
-
223
-LAB17:    goto LAB16;
224
-
225
-LAB19:    goto LAB17;
226
-
227
-LAB20:    xsi_set_current_line(117, ng0);
228
-    t2 = (t0 + 4472);
229
-    t4 = (t2 + 56U);
230
-    t6 = *((char **)t4);
231
-    t7 = (t6 + 56U);
232
-    t8 = *((char **)t7);
233
-    *((unsigned char *)t8) = (unsigned char)2;
234
-    xsi_driver_first_trans_fast(t2);
235
-    xsi_set_current_line(118, ng0);
236
-    t2 = (t0 + 7424);
237
-    t6 = (t0 + 4536);
238
-    t7 = (t6 + 56U);
239
-    t8 = *((char **)t7);
240
-    t9 = (t8 + 56U);
241
-    t10 = *((char **)t9);
242
-    memcpy(t10, t2, 4U);
243
-    xsi_driver_first_trans_fast(t6);
244
-    xsi_set_current_line(119, ng0);
245
-    t2 = (t0 + 7428);
246
-    t6 = (t0 + 4600);
247
-    t7 = (t6 + 56U);
248
-    t8 = *((char **)t7);
249
-    t9 = (t8 + 56U);
250
-    t10 = *((char **)t9);
251
-    memcpy(t10, t2, 4U);
252
-    xsi_driver_first_trans_fast(t6);
253
-    xsi_set_current_line(120, ng0);
254
-    t3 = (30 * 1000LL);
255
-    t2 = (t0 + 3640);
256
-    xsi_process_wait(t2, t3);
257
-
258
-LAB26:    *((char **)t1) = &&LAB27;
259
-    goto LAB1;
260
-
261
-LAB21:    goto LAB20;
262
-
263
-LAB23:    goto LAB21;
264
-
265
-LAB24:    xsi_set_current_line(122, ng0);
266
-    t2 = (t0 + 7432);
267
-    t6 = (t0 + 4344);
268
-    t7 = (t6 + 56U);
269
-    t8 = *((char **)t7);
270
-    t9 = (t8 + 56U);
271
-    t10 = *((char **)t9);
272
-    memcpy(t10, t2, 8U);
273
-    xsi_driver_first_trans_fast(t6);
274
-    xsi_set_current_line(123, ng0);
275
-    t3 = (30 * 1000LL);
276
-    t2 = (t0 + 3640);
277
-    xsi_process_wait(t2, t3);
278
-
279
-LAB30:    *((char **)t1) = &&LAB31;
280
-    goto LAB1;
281
-
282
-LAB25:    goto LAB24;
283
-
284
-LAB27:    goto LAB25;
285
-
286
-LAB28:    xsi_set_current_line(124, ng0);
287
-    t2 = (t0 + 4472);
288
-    t4 = (t2 + 56U);
289
-    t6 = *((char **)t4);
290
-    t7 = (t6 + 56U);
291
-    t8 = *((char **)t7);
292
-    *((unsigned char *)t8) = (unsigned char)3;
293
-    xsi_driver_first_trans_fast(t2);
294
-    xsi_set_current_line(125, ng0);
295
-    t3 = (30 * 1000LL);
296
-    t2 = (t0 + 3640);
297
-    xsi_process_wait(t2, t3);
298
-
299
-LAB34:    *((char **)t1) = &&LAB35;
300
-    goto LAB1;
301
-
302
-LAB29:    goto LAB28;
303
-
304
-LAB31:    goto LAB29;
305
-
306
-LAB32:    xsi_set_current_line(126, ng0);
307
-    t2 = (t0 + 4472);
308
-    t4 = (t2 + 56U);
309
-    t6 = *((char **)t4);
310
-    t7 = (t6 + 56U);
311
-    t8 = *((char **)t7);
312
-    *((unsigned char *)t8) = (unsigned char)2;
313
-    xsi_driver_first_trans_fast(t2);
314
-    xsi_set_current_line(127, ng0);
315
-    t2 = (t0 + 4280);
316
-    t4 = (t2 + 56U);
317
-    t6 = *((char **)t4);
318
-    t7 = (t6 + 56U);
319
-    t8 = *((char **)t7);
320
-    *((unsigned char *)t8) = (unsigned char)2;
321
-    xsi_driver_first_trans_fast(t2);
322
-    xsi_set_current_line(128, ng0);
323
-
324
-LAB38:    *((char **)t1) = &&LAB39;
325
-    goto LAB1;
326
-
327
-LAB33:    goto LAB32;
328
-
329
-LAB35:    goto LAB33;
330
-
331
-LAB36:    goto LAB2;
332
-
333
-LAB37:    goto LAB36;
334
-
335
-LAB39:    goto LAB37;
336
-
337
-}
338
-
339
-
340
-extern void work_a_3692836482_2372691052_init()
341
-{
342
-	static char *pe[] = {(void *)work_a_3692836482_2372691052_p_0,(void *)work_a_3692836482_2372691052_p_1};
343
-	xsi_register_didat("work_a_3692836482_2372691052", "isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat");
344
-	xsi_register_executes(pe);
345
-}

BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.lin64.o View File


+ 0
- 343
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c View File

@@ -1,343 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd";
25
-extern char *IEEE_P_2592010699;
26
-extern char *IEEE_P_1242562249;
27
-extern char *IEEE_P_3620187407;
28
-
29
-int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
30
-unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
31
-unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
32
-
33
-
34
-static void work_a_3998322972_3212880686_p_0(char *t0)
35
-{
36
-    char *t1;
37
-    char *t2;
38
-    char *t3;
39
-    unsigned char t4;
40
-    char *t5;
41
-    unsigned char t6;
42
-    char *t7;
43
-    int t8;
44
-    int t9;
45
-    unsigned int t10;
46
-    unsigned int t11;
47
-    unsigned int t12;
48
-    char *t13;
49
-    char *t14;
50
-    char *t15;
51
-    char *t16;
52
-    char *t17;
53
-    unsigned char t18;
54
-    char *t19;
55
-
56
-LAB0:    t1 = (t0 + 3624U);
57
-    t2 = *((char **)t1);
58
-    if (t2 == 0)
59
-        goto LAB2;
60
-
61
-LAB3:    goto *t2;
62
-
63
-LAB2:    xsi_set_current_line(47, ng0);
64
-
65
-LAB6:    t2 = (t0 + 4440);
66
-    *((int *)t2) = 1;
67
-    *((char **)t1) = &&LAB7;
68
-
69
-LAB1:    return;
70
-LAB4:    t5 = (t0 + 4440);
71
-    *((int *)t5) = 0;
72
-    xsi_set_current_line(48, ng0);
73
-    t2 = (t0 + 1512U);
74
-    t3 = *((char **)t2);
75