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Tests for processor ongoing

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Foussats Morgane 2021-05-04 15:24:57 +02:00
rodzic c363024e17
commit 56ee58bb48
77 zmienionych plików z 2996 dodań i 3560 usunięć
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BIN
a.out
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Plik binarny nie jest wyświetlany.

1718
analyse_syntaxique.output
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Plik diff jest za duży Load diff

1847
analyse_syntaxique.tab.c
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Plik diff jest za duży Load diff

162
analyse_syntaxique.tab.h
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@ -1,14 +1,13 @@
/* A Bison parser, made by GNU Bison 2.3. */
/* A Bison parser, made by GNU Bison 3.0.4. */
/* Skeleton interface for Bison's Yacc-like parsers in C
/* Bison interface for Yacc-like parsers in C
Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -16,9 +15,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* As a special exception, you may create a larger work that contains
part or all of the Bison parser skeleton and distribute that work
@ -33,99 +30,78 @@
This special exception was added by the Free Software Foundation in
version 2.2 of Bison. */
/* Tokens. */
#ifndef YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
# define YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 1
#endif
#if YYDEBUG
extern int yydebug;
#endif
/* Token type. */
#ifndef YYTOKENTYPE
# define YYTOKENTYPE
/* Put the tokens into the symbol table, so that GDB and other debuggers
know about them. */
enum yytokentype {
tENTIER = 258,
tENTIEREXP = 259,
tADD = 260,
tSUB = 261,
tMUL = 262,
tDIV = 263,
tPO = 264,
tPF = 265,
tAO = 266,
tAF = 267,
tERROR = 268,
tAPPERSAND = 269,
tPV = 270,
tVIRGULE = 271,
tAFFECTATION = 272,
tEGAL = 273,
tDIFF = 274,
tLT = 275,
tGT = 276,
tGTE = 277,
tLTE = 278,
tMAIN = 279,
tINT = 280,
tPRINT = 281,
tRETURN = 282,
tOR = 283,
tAND = 284,
tIF = 285,
tELSE = 286,
tWHILE = 287,
tCONST = 288,
tVAR = 289,
tNOT = 290
};
enum yytokentype
{
tENTIER = 258,
tENTIEREXP = 259,
tADD = 260,
tSUB = 261,
tMUL = 262,
tDIV = 263,
tPO = 264,
tPF = 265,
tAO = 266,
tAF = 267,
tERROR = 268,
tAPPERSAND = 269,
tPV = 270,
tVIRGULE = 271,
tAFFECTATION = 272,
tEGAL = 273,
tDIFF = 274,
tLT = 275,
tGT = 276,
tGTE = 277,
tLTE = 278,
tMAIN = 279,
tINT = 280,
tPRINT = 281,
tRETURN = 282,
tOR = 283,
tAND = 284,
tIF = 285,
tELSE = 286,
tWHILE = 287,
tCONST = 288,
tVAR = 289,
tNOT = 290
};
#endif
/* Tokens. */
#define tENTIER 258
#define tENTIEREXP 259
#define tADD 260
#define tSUB 261
#define tMUL 262
#define tDIV 263
#define tPO 264
#define tPF 265
#define tAO 266
#define tAF 267
#define tERROR 268
#define tAPPERSAND 269
#define tPV 270
#define tVIRGULE 271
#define tAFFECTATION 272
#define tEGAL 273
#define tDIFF 274
#define tLT 275
#define tGT 276
#define tGTE 277
#define tLTE 278
#define tMAIN 279
#define tINT 280
#define tPRINT 281
#define tRETURN 282
#define tOR 283
#define tAND 284
#define tIF 285
#define tELSE 286
#define tWHILE 287
#define tCONST 288
#define tVAR 289
#define tNOT 290
/* Value type. */
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
typedef union YYSTYPE
#line 1 "analyse_syntaxique.y"
union YYSTYPE
{
#line 1 "analyse_syntaxique.y" /* yacc.c:1909 */
int nombre;
char id[30];
}
/* Line 1529 of yacc.c. */
#line 124 "analyse_syntaxique.tab.h"
YYSTYPE;
# define yystype YYSTYPE /* obsolescent; will be withdrawn */
# define YYSTYPE_IS_DECLARED 1
#line 95 "analyse_syntaxique.tab.h" /* yacc.c:1909 */
};
typedef union YYSTYPE YYSTYPE;
# define YYSTYPE_IS_TRIVIAL 1
# define YYSTYPE_IS_DECLARED 1
#endif
extern YYSTYPE yylval;
int yyparse (void);
#endif /* !YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED */

4
analyse_syntaxique.y
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@ -157,7 +157,7 @@ If : tIF tPO Cond tPF {
free_temp(&table);
$1 = array.index;
}
tAO {table.depth++;} Instructions {generate_instruction_1(&array, JMP, -1)} tAF {remove_symboles(&table); table.depth--;}
tAO {table.depth++;} Instructions {generate_instruction_1(&array, JMP, -1);} tAF {remove_symboles(&table); table.depth--;}
{
int adr_jmp = array.index;
update_jmf(&array, $1, adr_jmp);
@ -203,7 +203,7 @@ Invocation : tVAR tPO {table.depth++; prepare_function_call(&table); return_valu
Args : Arg SuiteArgs ;
Args :
Arg : E {int arg_addr = prepare_argument_push(&table); generate_instruction_2(&array, COP, arg_addr, $1); free_temp(&table)};
Arg : E {int arg_addr = prepare_argument_push(&table); generate_instruction_2(&array, COP, arg_addr, $1); free_temp(&table);};
SuiteArgs : tVIRGULE Arg SuiteArgs ;
SuiteArgs : ;

27
instructions.txt
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@ -1,11 +1,16 @@
0 AFC 49 2
1 COP 0 49
2 LEA 49 0
3 COP 1 49
4 AFC 49 2
5 COP_STR [1] 49
6 COP 49 1
7 COP_LD 49 [49]
8 COP 2 49
9 AFC 49 0
10 RET 49
0 AFC 49 4
1 COP 1 49
2 AFC 49 1
3 RET 49
4 RET_FUN
5 AFC 49 2
6 COP 0 49
7 LEA 49 0
8 COP 1 49
9 AFC 49 2
10 COP_STR [1] 49
11 COP 49 1
12 COP_LD 49 [49]
13 COP 2 49
14 AFC 49 0
15 RET 49

448
lex.yy.c
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Plik diff jest za duży Load diff

5
script.sh
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@ -2,6 +2,11 @@ bison -d -t analyse_syntaxique.y -v
flex analyse_lexicale.lex
gcc -w *.c -ly
echo "
int fonction1(int a){
int b = 4;
return 1;
}
int main(){
int c = 2;
int * p;

43
xilinx/ALU/ALU.gise
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@ -25,14 +25,15 @@
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_data_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_data_test_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
@ -45,7 +46,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618572938">
<transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620134567">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
@ -56,20 +57,22 @@
<outfile xil_pn:name="bm_instr_test.vhd"/>
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
<outfile xil_pn:name="pipeline.vhd"/>
<outfile xil_pn:name="processeur.vhd"/>
</transform>
<transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8940589992921887805" xil_pn:start_ts="1618572911">
<transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-182187785304845874" xil_pn:start_ts="1620134030">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1570780385922884283" xil_pn:start_ts="1618572911">
<transform xil_pn:end_ts="1620134030" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5858825779926760884" xil_pn:start_ts="1620134030">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8229480169080511278" xil_pn:start_ts="1618303356">
<transform xil_pn:end_ts="1620126566" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="9006895703308992987" xil_pn:start_ts="1620126566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618572938">
<transform xil_pn:end_ts="1620134567" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620134567">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
@ -80,25 +83,21 @@
<outfile xil_pn:name="bm_instr_test.vhd"/>
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
<outfile xil_pn:name="pipeline.vhd"/>
<outfile xil_pn:name="processeur.vhd"/>
</transform>
<transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2732656885201204134" xil_pn:start_ts="1618572938">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1620134568" xil_pn:in_ck="-6589781723892986244" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6599872206167540207" xil_pn:start_ts="1620134567">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="bm_data_test_beh.prj"/>
<outfile xil_pn:name="bm_data_test_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5666824002871888647" xil_pn:start_ts="1618572940">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1620126600" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1620126600">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="bm_data_test_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<status xil_pn:value="InputRemoved"/>
</transform>
</transforms>

44
xilinx/ALU/ALU.xise
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@ -16,7 +16,7 @@
<files>
<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
@ -26,7 +26,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
@ -36,11 +36,11 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
@ -50,11 +50,19 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="bm_data_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="pipeline.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="processeur.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
</files>
<properties>
@ -171,9 +179,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|alu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="alu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="processeur.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -236,7 +244,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="alu" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="processeur" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -249,10 +257,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="alu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="processeur_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="processeur_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="processeur_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="processeur_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
@ -274,7 +282,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="alu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="processeur" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@ -297,8 +305,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/bm_data_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/processeur" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -316,7 +324,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.processeur" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -366,7 +374,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_data_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|processeur|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

2
xilinx/ALU/_xmsgs/pn_parser.xmsgs
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@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg>
</msg>
</messages>

4
xilinx/ALU/alu_summary.html
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@ -72,9 +72,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>jeu. avr. 15 10:54:50 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>ven. avr. 16 13:37:05 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 04/16/2021 - 12:24:04</center>
<br><center><b>Date Generated:</b> 05/04/2021 - 12:54:59</center>
</BODY></HTML>

2
xilinx/ALU/bm_data_test_beh.prj
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@ -1,2 +0,0 @@
vhdl work "bm.vhd"
vhdl work "bm_data_test.vhd"

BIN
xilinx/ALU/bm_data_test_isim_beh.wdb
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Plik binarny nie jest wyświetlany.

6
xilinx/ALU/bm_instr.vhd
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@ -25,14 +25,14 @@ use IEEE.NUMERIC_STD.ALL;
entity bm_instr is
Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
OUT_data : out STD_LOGIC_VECTOR (7 downto 0);
OUT_data : out STD_LOGIC_VECTOR (31 downto 0);
CLK : in STD_LOGIC);
end bm_instr;
architecture Behavioral of bm_instr is
type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
signal instr_memory: mem := (1 => "00000001", others =>"00000000");
type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
begin

4
xilinx/ALU/bm_instr_test.vhd
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@ -42,7 +42,7 @@ ARCHITECTURE behavior OF bm_instr_test IS
COMPONENT bm_instr
PORT(
IN_addr : IN std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
@ -53,7 +53,7 @@ ARCHITECTURE behavior OF bm_instr_test IS
signal CLK : std_logic := '0';
--Outputs
signal OUT_data : std_logic_vector(7 downto 0);
signal OUT_data : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;

2
xilinx/ALU/bm_instr_test_beh.prj Normal file
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@ -0,0 +1,2 @@
vhdl work "bm_instr.vhd"
vhdl work "bm_instr_test.vhd"

BIN
xilinx/ALU/bm_instr_test_isim_beh.wdb Normal file
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46
xilinx/ALU/fuse.log
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@ -1,25 +1,31 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj work.bm_data_test
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj work.processeur
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Determining compilation order of HDL files
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 98496 KB
Fuse CPU Usage: 730 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package numeric_std
Compiling architecture behavioral of entity bm_data [bm_data_default]
Compiling architecture behavior of entity bm_data_test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe
Fuse Memory Usage: 1722956 KB
Fuse CPU Usage: 850 ms
GCC CPU Usage: 1640 ms
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <rst> is already declared in this region.
ERROR:HDLCompiler:32 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <clk> is already declared in this region.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <ip> is not declared in <bm_instr>
ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <in_addr> has no actual or default value.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <op_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <a_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <b_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <c_in> is not declared.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <clk> is not declared in <pipeline>
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <b_lidi_out> is not declared in <br>
ERROR:HDLCompiler:432 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <a_addr> has no actual or default value.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <op_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <a_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <b_in> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <c_in> is not declared.
ERROR:HDLCompiler:1314 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <clk> is not declared in <pipeline>
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <a> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <b> is not declared.
ERROR:HDLCompiler:69 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <ctrl_alu> is not declared.
Sorry, too many errors..

57
xilinx/ALU/fuse.xmsgs
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@ -5,5 +5,62 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: &lt;<arg fmt="%s" index="1">rst</arg>&gt; is already declared in this region.
</msg>
<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: &lt;<arg fmt="%s" index="1">clk</arg>&gt; is already declared in this region.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic &lt;<arg fmt="%s" index="1">ip</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">bm_instr</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal &lt;<arg fmt="%s" index="1">in_addr</arg>&gt; has no actual or default value.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic &lt;<arg fmt="%s" index="1">b_lidi_out</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">br</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal &lt;<arg fmt="%s" index="1">a_addr</arg>&gt; has no actual or default value.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: &lt;<arg fmt="%s" index="1">op_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: &lt;<arg fmt="%s" index="1">a_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: &lt;<arg fmt="%s" index="1">b_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: &lt;<arg fmt="%s" index="1">c_in</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic &lt;<arg fmt="%s" index="1">clk</arg>&gt; is not declared in &lt;<arg fmt="%s" index="2">pipeline</arg>&gt;
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: &lt;<arg fmt="%s" index="1">a</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: &lt;<arg fmt="%s" index="1">b</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: &lt;<arg fmt="%s" index="1">ctrl_alu</arg>&gt; is not declared.
</msg>
</messages>

2
xilinx/ALU/fuseRelaunch.cmd
Wyświetl plik

@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj" "work.bm_data_test"
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_beh.prj" "work.processeur"

34
xilinx/ALU/iseconfig/ALU.projectmgr
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@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000145000000020000000000000000000000000200000064ffffffff000000810000000300000002000001450000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
@ -68,35 +68,39 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/alu_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|alu_test.vhd</ClosedNode>
<ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode>
<ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode>
<ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</SelectedItem>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000184000000020000000000000000000000000200000064ffffffff000000810000000300000002000001840000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</CurrentItem>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>View Compilation Log</SelectedItem>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>View Compilation Log</CurrentItem>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
@ -107,7 +111,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
@ -125,6 +129,6 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<SourceProcessView>000000ff0000000000000002000001620000011b01000000040100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<SourceProcessView>000000ff0000000000000002000001a6000000db01000000040100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView>
</Project>

94
xilinx/ALU/iseconfig/alu.xreport
Wyświetl plik

@ -1,33 +1,33 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2021-04-16T12:24:04</DateModified>
<ModuleName>alu</ModuleName>
<DateModified>2021-05-04T15:10:56</DateModified>
<ModuleName>processeur</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
<DateInitialized>2021-04-13T10:12:38</DateInitialized>
<DateInitialized>2021-05-04T13:11:55</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="alu_summary.html" label="Summary" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="processeur_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="alu_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="alu_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="alu_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="alu_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="alu.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="alu_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="alu_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="alu.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/tim/report.htm" label="CPLD Timing Report" />
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="processeur_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="processeur_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="processeur_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="processeur_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="processeur.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="processeur_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="processeur_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="processeur.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="processeur_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
@ -38,7 +38,7 @@
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="alu.log" label="System Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="processeur.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
@ -54,7 +54,7 @@
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="alu.syr" label="Synthesis Report" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="processeur.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
@ -80,15 +80,15 @@
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="alu.bld" label="Translation Report" >
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="processeur.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="alu_map.mrp" label="Map Report" >
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="processeur_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
@ -104,7 +104,7 @@
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="alu.par" label="Place and Route Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="processeur.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
@ -113,7 +113,7 @@
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="alu.twr" label="Post-PAR Static Timing Report" >
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="processeur.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
@ -124,22 +124,22 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.rpt" label="CPLD Fitter Report (Text)" >
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.tim" label="CPLD Timing Report (Text)" >
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="processeur.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="alu.pwr" label="Power Report" >
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="processeur.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="alu.bgn" label="Bitgen Report" >
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="processeur.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
@ -147,20 +147,20 @@
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/alu_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/processeur_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/alu_translate.nlf" label="Post-Translate Simulation Model Report" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/processeur_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu_map.map" label="Map Log File" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.twr" label="Post-Map Static Timing Report" >
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
@ -171,43 +171,43 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/alu_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_map.psr" label="Physical Synthesis Report" >
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/processeur_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="alu_pad.txt" label="Pad Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="processeur_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu.unroutes" label="Unroutes Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="processeur.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.tsi" label="Post-Place and Route Constraints Interaction Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/alu_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_sta.nlf" label="Primetime Netlist Report" >
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/processeur_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="processeur_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="alu.ibs" label="IBIS Model" >
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="processeur.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lck" label="Back-annotate Pin Report" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lpc" label="Locked Pin Constraints" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="processeur.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/alu_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/processeur_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>

10
xilinx/ALU/isim.log
Wyświetl plik

@ -1,5 +1,5 @@
ISim log file
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.wdb
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@ -11,4 +11,12 @@ Time resolution is 1 ps
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe
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29
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log
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@ -1,29 +0,0 @@
Command line:
bm_data_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 53487
Fri Apr 16 13:35:42 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 183.046 Meg
Total Signals : 13
Total Nets : 2075
Total Signal Drivers : 7
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 3
Total Traceable Variables : 16
Total Scalar Nets and Variables : 2577
Total Line Count : 27
Total Simulation Time: 0.1 sec
Current Memory Usage: 258.548 Meg
Fri Apr 16 13:37:04 2021

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat
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xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1
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181
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c
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@ -1,181 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_1242562249;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
static void work_a_1466808984_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
unsigned char t6;
char *t7;
int t8;
int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
unsigned char t19;
LAB0: t1 = (t0 + 3144U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(42, ng0);
LAB6: t2 = (t0 + 3464);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 3464);
*((int *)t5) = 0;
xsi_set_current_line(43, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)3);
if (t6 != 0)
goto LAB8;
LAB10: xsi_set_current_line(46, ng0);
t2 = (t0 + 1192U);
t3 = *((char **)t2);
t2 = (t0 + 1032U);
t5 = *((char **)t2);
t2 = (t0 + 5968U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
t11 = (8U * t10);
t12 = (0U + t11);
t7 = (t0 + 3608);
t13 = (t7 + 56U);
t14 = *((char **)t13);
t15 = (t14 + 56U);
t16 = *((char **)t15);
memcpy(t16, t3, 8U);
xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
LAB9: xsi_set_current_line(48, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)2);
if (t6 != 0)
goto LAB11;
LAB13:
LAB12: goto LAB2;
LAB5: t3 = (t0 + 1632U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(44, ng0);
t2 = (t0 + 1992U);
t5 = *((char **)t2);
t2 = (t0 + 1032U);
t7 = *((char **)t2);
t2 = (t0 + 5968U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
xsi_vhdl_check_range_of_index(0, 255, 1, t8);
t11 = (8U * t10);
t12 = (0 + t11);
t13 = (t5 + t12);
t14 = (t0 + 3544);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t13, 8U);
xsi_driver_first_trans_fast_port(t14);
goto LAB9;
LAB11: xsi_set_current_line(49, ng0);
t2 = xsi_get_transient_memory(2048U);
memset(t2, 0, 2048U);
t5 = t2;
t7 = (t0 + 8123);
t19 = (8U != 0);
if (t19 == 1)
goto LAB14;
LAB15: t14 = (t0 + 3608);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t2, 2048U);
xsi_driver_first_trans_fast(t14);
xsi_set_current_line(50, ng0);
t2 = xsi_get_transient_memory(8U);
memset(t2, 0, 8U);
t3 = t2;
memset(t3, (unsigned char)2, 8U);
t5 = (t0 + 3544);
t7 = (t5 + 56U);
t13 = *((char **)t7);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t2, 8U);
xsi_driver_first_trans_fast_port(t5);
goto LAB12;
LAB14: t10 = (2048U / 8U);
xsi_mem_set_data(t5, t7, 8U, t10);
goto LAB15;
}
extern void work_a_1466808984_3212880686_init()
{
static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
xsi_register_didat("work_a_1466808984_3212880686", "isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
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BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o
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288
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.c
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@ -1,288 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd";
static void work_a_2533693612_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(82, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(83, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(84, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(85, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_2533693612_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(93, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(94, ng0);
t2 = (t0 + 2128U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 3160);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(95, ng0);
t2 = (t0 + 3800);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(96, ng0);
t2 = (t0 + 6536);
t6 = (t0 + 3864);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(97, ng0);
t2 = (t0 + 6544);
t6 = (t0 + 3928);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(98, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(99, ng0);
t2 = (t0 + 6552);
t6 = (t0 + 3864);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(100, ng0);
t2 = (t0 + 6560);
t6 = (t0 + 3928);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(102, ng0);
t2 = (t0 + 3992);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(103, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: xsi_set_current_line(104, ng0);
t2 = (t0 + 6568);
t6 = (t0 + 3864);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(105, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB22: *((char **)t1) = &&LAB23;
goto LAB1;
LAB17: goto LAB16;
LAB19: goto LAB17;
LAB20: xsi_set_current_line(106, ng0);
t2 = (t0 + 6576);
t6 = (t0 + 3864);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(108, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB26: *((char **)t1) = &&LAB27;
goto LAB1;
LAB21: goto LAB20;
LAB23: goto LAB21;
LAB24: xsi_set_current_line(109, ng0);
t2 = (t0 + 3800);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(111, ng0);
LAB30: *((char **)t1) = &&LAB31;
goto LAB1;
LAB25: goto LAB24;
LAB27: goto LAB25;
LAB28: goto LAB2;
LAB29: goto LAB28;
LAB31: goto LAB29;
}
extern void work_a_2533693612_2372691052_init()
{
static char *pe[] = {(void *)work_a_2533693612_2372691052_p_0,(void *)work_a_2533693612_2372691052_p_1};
xsi_register_didat("work_a_2533693612_2372691052", "isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat
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xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.lin64.o
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BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe Plik wykonywalny
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0
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log
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29
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log Normal file
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@ -0,0 +1,29 @@
Command line:
bm_instr_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 58939
Tue May 4 13:10:22 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 187.593 Meg
Total Signals : 7
Total Nets : 8233
Total Signal Drivers : 3
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 3
Total Traceable Variables : 16
Total Scalar Nets and Variables : 8735
Total Line Count : 11
Total Simulation Time: 0.03 sec
Current Memory Usage: 263.094 Meg
Tue May 4 13:11:03 2021

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat Normal file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 Normal file
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84
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c Normal file
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@ -0,0 +1,84 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd";
extern char *IEEE_P_1242562249;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
static void work_a_1802466774_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
int t4;
int t5;
unsigned int t6;
unsigned int t7;
unsigned int t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
LAB0: xsi_set_current_line(39, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t1 = (t0 + 1032U);
t3 = *((char **)t1);
t1 = (t0 + 5224U);
t4 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t3, t1);
t5 = (t4 - 0);
t6 = (t5 * 1);
xsi_vhdl_check_range_of_index(0, 255, 1, t4);
t7 = (32U * t6);
t8 = (0 + t7);
t9 = (t2 + t8);
t10 = (t0 + 3064);
t11 = (t10 + 56U);
t12 = *((char **)t11);
t13 = (t12 + 56U);
t14 = *((char **)t13);
memcpy(t14, t9, 32U);
xsi_driver_first_trans_fast_port(t10);
LAB2: t15 = (t0 + 2984);
*((int *)t15) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1802466774_3212880686_init()
{
static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat Normal file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o Normal file
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192
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c Normal file
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@ -0,0 +1,192 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
static void work_a_4060154216_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2624U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(73, ng0);
t2 = (t0 + 3256);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(74, ng0);
t2 = (t0 + 1648U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(75, ng0);
t2 = (t0 + 3256);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(76, ng0);
t2 = (t0 + 1648U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_4060154216_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 2872U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(84, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(86, ng0);
t2 = (t0 + 1648U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2680);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(88, ng0);
t2 = (t0 + 5568);
t6 = (t0 + 3320);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(89, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
xsi_process_wait(t2, t3);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(91, ng0);
t2 = (t0 + 5576);
t6 = (t0 + 3320);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(94, ng0);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: goto LAB2;
LAB17: goto LAB16;
LAB19: goto LAB17;
}
extern void work_a_4060154216_2372691052_init()
{
static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat Normal file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o Normal file
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6
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.c → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c
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@ -31,11 +31,11 @@ int main(int argc, char **argv)
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_1466808984_3212880686_init();
work_a_2533693612_2372691052_init();
work_a_1802466774_3212880686_init();
work_a_4060154216_2372691052_init();
xsi_register_tops("work_a_2533693612_2372691052");
xsi_register_tops("work_a_4060154216_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.lin64.o → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o
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xilinx/ALU/isim/br_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe
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0
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimcrash.log
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29
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log
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@ -1,29 +0,0 @@
Command line:
br_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 44223
Fri Apr 16 13:26:05 2021
Elaboration Time: 0 sec
Current Memory Usage: 181.682 Meg
Total Signals : 19
Total Nets : 167
Total Signal Drivers : 10
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 5
Total Traceable Variables : 16
Total Scalar Nets and Variables : 669
Total Line Count : 33
Total Simulation Time: 0.01 sec
Current Memory Usage: 257.184 Meg
Fri Apr 16 13:26:10 2021

BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat
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xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1
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345
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.c
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@ -1,345 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd";
static void work_a_3692836482_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3584U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(91, ng0);
t2 = (t0 + 4216);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(92, ng0);
t2 = (t0 + 2608U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 3392);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(93, ng0);
t2 = (t0 + 4216);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(94, ng0);
t2 = (t0 + 2608U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 3392);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_3692836482_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 3832U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(102, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(104, ng0);
t2 = (t0 + 2608U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 3640);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(106, ng0);
t2 = (t0 + 4280);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(108, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(109, ng0);
t2 = (t0 + 7400);
t6 = (t0 + 4344);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(110, ng0);
t2 = (t0 + 7408);
t6 = (t0 + 4408);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 4U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(111, ng0);
t2 = (t0 + 4472);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(112, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: xsi_set_current_line(113, ng0);
t2 = (t0 + 7412);
t6 = (t0 + 4408);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 4U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(114, ng0);
t2 = (t0 + 7416);
t6 = (t0 + 4344);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(115, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB22: *((char **)t1) = &&LAB23;
goto LAB1;
LAB17: goto LAB16;
LAB19: goto LAB17;
LAB20: xsi_set_current_line(117, ng0);
t2 = (t0 + 4472);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(118, ng0);
t2 = (t0 + 7424);
t6 = (t0 + 4536);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 4U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(119, ng0);
t2 = (t0 + 7428);
t6 = (t0 + 4600);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 4U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(120, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB26: *((char **)t1) = &&LAB27;
goto LAB1;
LAB21: goto LAB20;
LAB23: goto LAB21;
LAB24: xsi_set_current_line(122, ng0);
t2 = (t0 + 7432);
t6 = (t0 + 4344);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(123, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB30: *((char **)t1) = &&LAB31;
goto LAB1;
LAB25: goto LAB24;
LAB27: goto LAB25;
LAB28: xsi_set_current_line(124, ng0);
t2 = (t0 + 4472);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(125, ng0);
t3 = (30 * 1000LL);
t2 = (t0 + 3640);
xsi_process_wait(t2, t3);
LAB34: *((char **)t1) = &&LAB35;
goto LAB1;
LAB29: goto LAB28;
LAB31: goto LAB29;
LAB32: xsi_set_current_line(126, ng0);
t2 = (t0 + 4472);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(127, ng0);
t2 = (t0 + 4280);
t4 = (t2 + 56U);
t6 = *((char **)t4);
t7 = (t6 + 56U);
t8 = *((char **)t7);
*((unsigned char *)t8) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(128, ng0);
LAB38: *((char **)t1) = &&LAB39;
goto LAB1;
LAB33: goto LAB32;
LAB35: goto LAB33;
LAB36: goto LAB2;
LAB37: goto LAB36;
LAB39: goto LAB37;
}
extern void work_a_3692836482_2372691052_init()
{
static char *pe[] = {(void *)work_a_3692836482_2372691052_p_0,(void *)work_a_3692836482_2372691052_p_1};
xsi_register_didat("work_a_3692836482_2372691052", "isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat
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xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.lin64.o
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343
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c
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@ -1,343 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_1242562249;
extern char *IEEE_P_3620187407;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
static void work_a_3998322972_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
unsigned char t6;
char *t7;
int t8;
int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
unsigned char t18;
char *t19;
LAB0: t1 = (t0 + 3624U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(47, ng0);
LAB6: t2 = (t0 + 4440);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 4440);
*((int *)t5) = 0;
xsi_set_current_line(48, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)3);
if (t6 != 0)
goto LAB8;
LAB10:
LAB9: xsi_set_current_line(51, ng0);
t2 = (t0 + 1832U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t6 = (t4 == (unsigned char)2);
if (t6 != 0)
goto LAB11;
LAB13:
LAB12: goto LAB2;
LAB5: t3 = (t0 + 1952U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(49, ng0);
t2 = (t0 + 1672U);
t5 = *((char **)t2);
t2 = (t0 + 1352U);
t7 = *((char **)t2);
t2 = (t0 + 7424U);
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
t9 = (t8 - 0);
t10 = (t9 * 1);
t11 = (8U * t10);
t12 = (0U + t11);
t13 = (t0 + 4552);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t5, 8U);
xsi_driver_first_trans_delta(t13, t12, 8U, 0LL);
goto LAB9;
LAB11: xsi_set_current_line(52, ng0);
t2 = xsi_get_transient_memory(128U);
memset(t2, 0, 128U);
t5 = t2;
t7 = (t0 + 7679);
t18 = (8U != 0);
if (t18 == 1)
goto LAB14;
LAB15: t14 = (t0 + 4552);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t19 = *((char **)t17);
memcpy(t19, t2, 128U);
xsi_driver_first_trans_fast(t14);
goto LAB12;
LAB14: t10 = (128U / 8U);
xsi_mem_set_data(t5, t7, 8U, t10);
goto LAB15;
}
static void work_a_3998322972_3212880686_p_1(char *t0)
{
unsigned char t1;
char *t2;
char *t3;
unsigned char t4;
unsigned char t5;
char *t6;
char *t7;
char *t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
int t13;
int t14;
unsigned int t15;
unsigned int t16;
unsigned int t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
LAB0: xsi_set_current_line(55, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t5 = (t4 == (unsigned char)2);
if (t5 == 1)
goto LAB5;
LAB6: t2 = (t0 + 1032U);
t6 = *((char **)t2);
t2 = (t0 + 7392U);
t7 = (t0 + 1352U);
t8 = *((char **)t7);
t7 = (t0 + 7424U);
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
t1 = t9;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 1672U);
t25 = *((char **)t24);
t24 = (t0 + 4616);
t26 = (t24 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
memcpy(t29, t25, 8U);
xsi_driver_first_trans_fast_port(t24);
LAB2: t30 = (t0 + 4456);
*((int *)t30) = 1;
LAB1: return;
LAB3: t10 = (t0 + 2472U);
t11 = *((char **)t10);
t10 = (t0 + 1032U);
t12 = *((char **)t10);
t10 = (t0 + 7392U);
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
t14 = (t13 - 0);
t15 = (t14 * 1);
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
t16 = (8U * t15);
t17 = (0 + t16);
t18 = (t11 + t17);
t19 = (t0 + 4616);
t20 = (t19 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
memcpy(t23, t18, 8U);
xsi_driver_first_trans_fast_port(t19);
goto LAB2;
LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_3998322972_3212880686_p_2(char *t0)
{
unsigned char t1;
char *t2;
char *t3;
unsigned char t4;
unsigned char t5;
char *t6;
char *t7;
char *t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
int t13;
int t14;
unsigned int t15;
unsigned int t16;
unsigned int t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
LAB0: xsi_set_current_line(57, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t4 = *((unsigned char *)t3);
t5 = (t4 == (unsigned char)2);
if (t5 == 1)
goto LAB5;
LAB6: t2 = (t0 + 1192U);
t6 = *((char **)t2);
t2 = (t0 + 7408U);
t7 = (t0 + 1352U);
t8 = *((char **)t7);
t7 = (t0 + 7424U);
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
t1 = t9;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 1672U);
t25 = *((char **)t24);
t24 = (t0 + 4680);
t26 = (t24 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
memcpy(t29, t25, 8U);
xsi_driver_first_trans_fast_port(t24);
LAB2: t30 = (t0 + 4472);
*((int *)t30) = 1;
LAB1: return;
LAB3: t10 = (t0 + 2472U);
t11 = *((char **)t10);
t10 = (t0 + 1192U);
t12 = *((char **)t10);
t10 = (t0 + 7408U);
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
t14 = (t13 - 0);
t15 = (t14 * 1);
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
t16 = (8U * t15);
t17 = (0 + t16);
t18 = (t11 + t17);
t19 = (t0 + 4680);
t20 = (t19 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
memcpy(t23, t18, 8U);
xsi_driver_first_trans_fast_port(t19);
goto LAB2;
LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
}
extern void work_a_3998322972_3212880686_init()
{
static char *pe[] = {(void *)work_a_3998322972_3212880686_p_0,(void *)work_a_3998322972_3212880686_p_1,(void *)work_a_3998322972_3212880686_p_2};
xsi_register_didat("work_a_3998322972_3212880686", "isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
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xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o
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49
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/br_test_isim_beh.exe_main.c
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@ -1,49 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
char *IEEE_P_3620187407;
char *IEEE_P_3499444699;
char *IEEE_P_1242562249;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_3998322972_3212880686_init();
work_a_3692836482_2372691052_init();
xsi_register_tops("work_a_3692836482_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
return xsi_run_simulation(argc, argv);
}

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xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/br_test_isim_beh.exe_main.lin64.o
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8
xilinx/ALU/isim/isim_usage_statistics.html
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@ -2,14 +2,14 @@
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1722956 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>840 ms, 1722812 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>13</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>2075</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>8233</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 257495 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 262041 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>

0
xilinx/ALU/isim/lockfile1
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
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xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
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xilinx/ALU/isim/work/bm_data.vdb
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xilinx/ALU/isim/work/bm_data_test.vdb
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5
xilinx/ALU/pepExtractor.prj
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@ -1 +1,6 @@
work "alu.vhd"
work "bm.vhd"
work "bm_instr.vhd"
work "br.vhd"
work "pipeline.vhd"
work "processeur.vhd"

1
xilinx/ALU/pipeline.vhd
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@ -34,6 +34,7 @@ entity pipeline is
A_IN : in STD_LOGIC_VECTOR (7 downto 0);
B_IN : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
B_OUT : out STD_LOGIC_VECTOR (7 downto 0);

274
xilinx/ALU/processeur.vhd Normal file
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@ -0,0 +1,274 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:52:06 05/04/2021
-- Design Name:
-- Module Name: processeur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity processeur is
Port ( CLK: in STD_LOGIC ;
RST : in STD_LOGIC);
end processeur;
architecture Behavioral of processeur is
COMPONENT bm_instr
PORT(
IN_addr : IN std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(7 downto 0);
CLK : IN std_logic
);
END COMPONENT;
COMPONENT pipeline
PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0);
A_IN : in STD_LOGIC_VECTOR (7 downto 0);
B_IN : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC_VECTOR (7 downto 0);
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
C_OUT : out STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT;
COMPONENT br
PORT(
A_addr : IN std_logic_vector(3 downto 0);
B_addr : IN std_logic_vector(3 downto 0);
W_addr : IN std_logic_vector(3 downto 0);
W : IN std_logic;
Data : IN std_logic_vector(7 downto 0);
RST : IN std_logic;
CLK : IN std_logic;
QA : OUT std_logic_vector(7 downto 0);
QB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT alu
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Ctrl_Alu : IN std_logic_vector(2 downto 0);
N : OUT std_logic;
O : OUT std_logic;
Z : OUT std_logic;
C : OUT std_logic;
S : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT bm_data
PORT(
IN_addr : IN std_logic_vector(7 downto 0);
IN_data : IN std_logic_vector(7 downto 0);
RW : IN std_logic;
RST : IN std_logic;
CLK : IN std_logic;
OUT_data : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal RST : std_logic := '0';
signal CLK : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
--Inputs
signal IP : std_logic_vector(7 downto 0) := (others => '0');
signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OUT_data : std_logic_vector(7 downto 0);
signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
signal A_LIDI_OUT : std_logic_vector(7 downto 0);
signal B_LIDI_OUT : std_logic_vector(7 downto 0);
signal C_LIDI_OUT : std_logic_vector(7 downto 0);
signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
signal A_DIEX_OUT : std_logic_vector(7 downto 0);
signal B_DIEX_OUT : std_logic_vector(7 downto 0);
signal C_DIEX_OUT : std_logic_vector(7 downto 0);
signal O_ALU_OUT : std_logic;
signal N_ALU_OUT : std_logic;
signal Z_ALU_OUT : std_logic;
signal C_ALU_OUT : std_logic;
signal A_EXMem_OUT : std_logic_vector(7 downto 0);
signal B_EXMem_OUT : std_logic_vector(7 downto 0);
signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
signal A_MemRE_OUT : std_logic_vector(7 downto 0);
signal B_MemRE_OUT : std_logic_vector(7 downto 0);
signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
--AUX
signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
signal RW_LC : std_logic;
signal addr_dm_MUX : std_logic_vector(7 downto 0);
signal in_dm_MUX : std_logic_vector(7 downto 0);
signal out_dm_MUX : std_logic_vector(7 downto 0);
signal W_br_LC : std_logic;
begin
-- Instantiate adresse des instructions
addr_instructions: bm_instr PORT MAP (
IP => IN_addr,
OUT_data => OUT_data,
CLK => CLK
);
-- Instantiate pipeline LI_LD
LI_LD : pipeline PORT MAP (
OP_IN <= OUT_data(31 downto 24),
A_IN <= OUT_data(23 downto 16),
B_IN <= OUT_data(15 downto 8),
C_IN <= OUT_data(7 downto 0),
CLK => CLK,
A_OUT => A_LIDI_OUT,
B_OUT => B_LIDI_OUT,
C_OUT => C_LIDI_OUT,
OP_OUT => OP_LIDI_OUT
);
W_br_LC <= '1' when OP_MemRE_OUT = x"07" else
'0';
-- Instanciate banc de registre
banc_registres : br PORT MAP (
B_LIDI_OUT => A_addr,
C_LIDI_OUT => B_addr,
A_MemRE_OUT => W_addr,
W_br_LC => W, --ATTENTION LC
B_MemRE_OUT => Data,
RST => RST,
CLK => CLK,
QA => QA_IN_MUX,
QB => C_DIEX_IN
);
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" else B_LIDI_OUT ;
-- Instantiate pipeline DI_EX
DI_EX : pipeline PORT MAP (
OP_IN <= OP_LIDI_OUT,
A_IN <= A_LIDI_OUT,
B_IN <= B_DIEX_IN,
C_IN <= C_DIEX_IN,
CLK => CLK,
A_OUT => A_DIEX_OUT,
B_OUT => B_DIEX_OUT,
C_OUT => C_DIEX_OUT,
OP_OUT => OP_DIEX_OUT
);
Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else
"010" when OP_DIEX_OUT = x"03" else
"011" when OP_DIEX_OUT = x"02" else
"000";
-- Instantiate alu
UAL : alu PORT MAP (
A <= B_DIEX_OUT,
B <= C_DIEX_OUT,
Ctrl_Alu <= Ctr_AlU_LC,
N => N_ALU_OUT,
O => O_ALU_OUT,
Z => Z_ALU_OUT,
C => C_ALU_OUT,
S => S_IN_MUX
);
B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else
B_DIEX_OUT ;
-- Instantiate pipeline EX_Mem
EX_Mem : pipeline PORT MAP (
OP_IN <= OP_DIEX_OUT,
A_IN <= A_DIEX_OUT,
B_IN <= B_EXMem_IN,
C_IN <= x"00",
CLK => CLK,
A_OUT => A_EXMem_OUT,
B_OUT => B_EXMem_OUT,
C_OUT => open,
OP_OUT => OP_EXMem_OUT
);
RW_LC <= '0' when OP_EXMem_OUT = x"08" else
'1';
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
A_EXMem_OUT;
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
B_EXMem_OUT;
-- Instantiate banc de données
data_memory: bm_data PORT MAP (
addr_dm_MUX => IN_addr,
B_MemRE_IN => IN_data,
RW_LC => RW,
RST => RST,
CLK => CLK,
OUT_data => out_dm_MUX
);
-- Instantiate pipeline Mem_RE
Mem_RE : pipeline PORT MAP (
OP_IN <= OP_EXMem_OUT,
A_IN <= A_EXMem_OUT,
B_IN <= OUT_data(15 downto 8),
C_IN <= x"00",
CLK => CLK,
A_OUT => A_MemRE_OUT,
B_OUT => B_MemRE_OUT,
C_OUT => open,
OP_OUT => OP_MemRE_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
IP <= IP + "00000001";
end Behavioral;

6
xilinx/ALU/processeur_beh.prj Normal file
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@ -0,0 +1,6 @@
vhdl work "pipeline.vhd"
vhdl work "br.vhd"
vhdl work "bm_instr.vhd"
vhdl work "bm.vhd"
vhdl work "alu.vhd"
vhdl work "processeur.vhd"

80
xilinx/ALU/processeur_summary.html Normal file
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@ -0,0 +1,80 @@
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>alu Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ALU.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>processeur</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-3csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. mai 4 13:11:04 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 05/04/2021 - 15:22:09</center>
</BODY></HTML>

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xilinx/ALU/processeur_test.vhd Normal file
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-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;