66 lines
4.8 KiB
XML
66 lines
4.8 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 96: <<arg fmt="%s" index="1">rst</arg>> is already declared in this region.
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</msg>
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<msg type="error" file="HDLCompiler" num="32" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 97: <<arg fmt="%s" index="1">clk</arg>> is already declared in this region.
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</msg>
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<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 148: Formal port/generic <<arg fmt="%s" index="1">ip</arg>> is not declared in <<arg fmt="%s" index="2">bm_instr</arg>>
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</msg>
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<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 147: Formal <<arg fmt="%s" index="1">in_addr</arg>> has no actual or default value.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 155: <<arg fmt="%s" index="1">op_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 156: <<arg fmt="%s" index="1">a_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 157: <<arg fmt="%s" index="1">b_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 158: <<arg fmt="%s" index="1">c_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 159: Formal port/generic <<arg fmt="%s" index="1">clk</arg>> is not declared in <<arg fmt="%s" index="2">pipeline</arg>>
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</msg>
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<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 169: Formal port/generic <<arg fmt="%s" index="1">b_lidi_out</arg>> is not declared in <<arg fmt="%s" index="2">br</arg>>
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</msg>
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<msg type="error" file="HDLCompiler" num="432" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 168: Formal <<arg fmt="%s" index="1">a_addr</arg>> has no actual or default value.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 185: <<arg fmt="%s" index="1">op_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 186: <<arg fmt="%s" index="1">a_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 187: <<arg fmt="%s" index="1">b_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 188: <<arg fmt="%s" index="1">c_in</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="1314" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 189: Formal port/generic <<arg fmt="%s" index="1">clk</arg>> is not declared in <<arg fmt="%s" index="2">pipeline</arg>>
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 203: <<arg fmt="%s" index="1">a</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 204: <<arg fmt="%s" index="1">b</arg>> is not declared.
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</msg>
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<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" Line 205: <<arg fmt="%s" index="1">ctrl_alu</arg>> is not declared.
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</msg>
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</messages>
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