74 lines
2 KiB
VHDL
74 lines
2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:12:38 04/13/2021
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-- Design Name:
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-- Module Name: alu - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity alu is
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
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B : in STD_LOGIC_VECTOR (7 downto 0);
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Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC;
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S : out STD_LOGIC_VECTOR (7 downto 0));
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end alu;
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architecture Behavioral of alu is
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signal A9: STD_LOGIC_VECTOR(8 downto 0);
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signal B9: STD_LOGIC_VECTOR(8 downto 0);
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signal ADD: STD_LOGIC_VECTOR(8 downto 0);
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signal SUB: STD_LOGIC_VECTOR(8 downto 0);
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signal MUL: STD_LOGIC_VECTOR(15 downto 0);
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signal SBIS: STD_LOGIC_VECTOR(7 downto 0);
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begin
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A9 <= "0"& A;
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B9 <= "0"& B;
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ADD <= A9 + B9;
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SUB <= A9 - B9;
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MUL <= A * B;
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SBIS <= ADD(7 downto 0) when Ctrl_Alu = "001" else
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SUB(7 downto 0) when Ctrl_Alu = "010" else
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MUL(7 downto 0) when Ctrl_Alu = "011" else
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(others => '0');
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O <= '1' when MUL(15 downto 8) /= "00000000" and Ctrl_Alu = "011" else
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'0';
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C <= '1' when ADD(8) = '1' and Ctrl_Alu = "001" else
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'0';
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N <= '1' when SUB(8) = '1' and Ctrl_Alu = "010" else
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'0';
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Z <= '1' when SBIS = "00000000" and Ctrl_Alu /= "000" else
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'0';
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S <= SBIS;
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end Behavioral;
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