Browse Source

else ok + tests et pipeline ok

Foussats Morgane 7 months ago
parent
commit
bc2a2ee47d
78 changed files with 2138 additions and 969 deletions
  1. BIN
      a.out
  2. 383
    371
      analyse_syntaxique.output
  3. 171
    160
      analyse_syntaxique.tab.c
  4. 5
    4
      analyse_syntaxique.y
  5. 5
    5
      gen_assembleur.c
  6. 1
    1
      gen_assembleur.h
  7. 21
    14
      instructions.txt
  8. 7
    4
      script.sh
  9. 17
    26
      xilinx/ALU/ALU.gise
  10. 13
    7
      xilinx/ALU/ALU.xise
  11. 1
    1
      xilinx/ALU/_xmsgs/pn_parser.xmsgs
  12. 6
    6
      xilinx/ALU/alu.vhd
  13. 1
    1
      xilinx/ALU/alu_summary.html
  14. 32
    6
      xilinx/ALU/alu_test.vhd
  15. 2
    1
      xilinx/ALU/bm.vhd
  16. BIN
      xilinx/ALU/bm_data_isim_beh.exe
  17. 114
    0
      xilinx/ALU/bm_data_test.vhd
  18. 2
    0
      xilinx/ALU/bm_data_test_beh.prj
  19. BIN
      xilinx/ALU/bm_data_test_isim_beh.exe
  20. BIN
      xilinx/ALU/bm_data_test_isim_beh.wdb
  21. BIN
      xilinx/ALU/bm_data_test_isim_beh1.wdb
  22. 0
    2
      xilinx/ALU/bm_instr_test_beh.prj
  23. BIN
      xilinx/ALU/bm_instr_test_isim_beh.wdb
  24. 15
    10
      xilinx/ALU/br_test.vhd
  25. 12
    12
      xilinx/ALU/fuse.log
  26. 1
    1
      xilinx/ALU/fuseRelaunch.cmd
  27. 1
    1
      xilinx/ALU/iseconfig/alu.xreport
  28. 1
    1
      xilinx/ALU/isim.log
  29. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  30. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe
  31. 0
    0
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimcrash.log
  32. 29
    0
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log
  33. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat
  34. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1
  35. 181
    0
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c
  36. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat
  37. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o
  38. 288
    0
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.c
  39. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat
  40. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.lin64.o
  41. 3
    3
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.c
  42. BIN
      xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.lin64.o
  43. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  44. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe
  45. 0
    29
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log
  46. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat
  47. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1
  48. 0
    106
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
  49. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
  50. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
  51. 0
    192
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c
  52. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat
  53. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o
  54. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  55. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe
  56. 0
    0
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimcrash.log
  57. 29
    0
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log
  58. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat
  59. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1
  60. 345
    0
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.c
  61. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat
  62. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.lin64.o
  63. 343
    0
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.c
  64. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
  65. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.lin64.o
  66. 49
    0
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/br_test_isim_beh.exe_main.c
  67. BIN
      xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/br_test_isim_beh.exe_main.lin64.o
  68. 4
    4
      xilinx/ALU/isim/isim_usage_statistics.html
  69. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
  70. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
  71. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
  72. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
  73. BIN
      xilinx/ALU/isim/work/bm_data.vdb
  74. BIN
      xilinx/ALU/isim/work/bm_data_test.vdb
  75. BIN
      xilinx/ALU/isim/work/bm_instr.vdb
  76. BIN
      xilinx/ALU/isim/work/bm_instr_test.vdb
  77. 1
    1
      xilinx/ALU/pepExtractor.prj
  78. 55
    0
      xilinx/ALU/pipeline.vhd

BIN
a.out View File


+ 383
- 371
analyse_syntaxique.output
File diff suppressed because it is too large
View File


+ 171
- 160
analyse_syntaxique.tab.c View File

@@ -413,16 +413,16 @@ union yyalloc
413 413
 /* YYFINAL -- State number of the termination state.  */
414 414
 #define YYFINAL  4
415 415
 /* YYLAST -- Last index in YYTABLE.  */
416
-#define YYLAST   137
416
+#define YYLAST   140
417 417
 
418 418
 /* YYNTOKENS -- Number of terminals.  */
419 419
 #define YYNTOKENS  35
420 420
 /* YYNNTS -- Number of nonterminals.  */
421
-#define YYNNTS  27
421
+#define YYNNTS  28
422 422
 /* YYNRULES -- Number of rules.  */
423
-#define YYNRULES  59
423
+#define YYNRULES  60
424 424
 /* YYNSTATES -- Number of states.  */
425
-#define YYNSTATES  129
425
+#define YYNSTATES  130
426 426
 
427 427
 /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
428 428
    by yylex, with out-of-bounds checking.  */
@@ -473,10 +473,11 @@ static const yytype_uint8 yyrline[] =
473 473
 {
474 474
        0,    78,    78,    80,    81,    83,    86,    87,    90,    92,
475 475
       93,    95,    96,    97,    98,    99,   100,   102,   104,   105,
476
-     107,   108,   110,   111,   114,   117,   119,   121,   122,   123,
477
-     124,   125,   126,   127,   130,   131,   133,   134,   136,   143,
478
-     136,   149,   150,   151,   153,   155,   153,   169,   170,   171,
479
-     172,   173,   174,   175,   176,   177,   178,   182,   185,   188
476
+     107,   108,   110,   110,   111,   114,   117,   119,   121,   122,
477
+     123,   124,   125,   126,   127,   130,   131,   133,   134,   136,
478
+     143,   136,   149,   150,   151,   153,   155,   153,   169,   170,
479
+     171,   172,   173,   174,   175,   176,   177,   178,   183,   186,
480
+     189
480 481
 };
481 482
 #endif
482 483
 
@@ -491,8 +492,8 @@ static const char *const yytname[] =
491 492
   "tINT", "tPRINT", "tRETURN", "tOR", "tAND", "tIF", "tELSE", "tWHILE",
492 493
   "tCONST", "tVAR", "tNOT", "$accept", "Main", "Params", "Param",
493 494
   "SuiteParams", "Body", "Instructions", "Instruction", "Decl",
494
-  "SuiteDecl", "Type", "Valeur", "Aff", "E", "Args", "SuiteArgs", "If",
495
-  "$@1", "$@2", "Else", "While", "$@3", "$@4", "Cond", "Invocation",
495
+  "SuiteDecl", "Type", "Valeur", "$@1", "Aff", "E", "Args", "SuiteArgs",
496
+  "If", "$@2", "$@3", "Else", "While", "$@4", "$@5", "Cond", "Invocation",
496 497
   "Print", "Return", YY_NULLPTR
497 498
 };
498 499
 #endif
@@ -514,7 +515,7 @@ static const yytype_uint16 yytoknum[] =
514 515
 #define yypact_value_is_default(Yystate) \
515 516
   (!!((Yystate) == (-50)))
516 517
 
517
-#define YYTABLE_NINF -1
518
+#define YYTABLE_NINF -23
518 519
 
519 520
 #define yytable_value_is_error(Yytable_value) \
520 521
   0
@@ -523,19 +524,19 @@ static const yytype_uint16 yytoknum[] =
523 524
      STATE-NUM.  */
524 525
 static const yytype_int8 yypact[] =
525 526
 {
526
-     -20,   -16,    11,    10,   -50,    -8,    -6,    30,    46,   -50,
527
-      66,    -8,   -50,    49,   -50,    46,   -50,    54,    70,    74,
528
-      60,    55,    71,    49,   -50,    73,   -50,   -50,   -50,    90,
527
+     -20,   -16,    11,    10,   -50,    -8,    -6,    25,    47,   -50,
528
+      30,    -8,   -50,    56,   -50,    47,   -50,    63,    65,    73,
529
+      59,    55,    58,    56,   -50,    72,   -50,   -50,   -50,    84,
529 530
      -50,    93,    19,    17,   -50,   -50,    75,    19,    19,    97,
530
-     -50,    95,    98,   -50,   -50,   -50,    19,    19,   101,    52,
531
-     -50,    17,    48,   104,    17,   100,   106,     7,    27,   -50,
532
-      19,    73,   103,    22,    85,    19,    19,    19,    19,   105,
531
+     -50,    94,    96,   -50,   -50,   -50,    19,    19,   103,    53,
532
+     -50,    17,    48,   104,    17,   100,   106,     7,    26,   -50,
533
+     101,    72,   105,    22,    86,    19,    19,    19,    19,   107,
533 534
      -50,    19,    19,    19,    19,    19,    19,    19,    19,   -50,
534
-     108,    87,   -50,   -50,   -50,   -50,    94,    98,   -50,   -50,
535
-      80,    22,   113,   -50,   -50,    94,    94,    94,    94,    94,
536
-      94,    94,    94,   111,   -50,   100,   -50,    49,   112,   -50,
537
-     114,    49,   -50,   115,    99,   -50,    -5,   -50,    49,   116,
538
-     118,    17,   -50,   121,   117,    49,   120,    99,   -50
535
+     108,    87,   -50,   -50,   -50,   -50,    19,    96,   -50,   -50,
536
+      71,    22,   114,   -50,   -50,    95,    95,    95,    95,    95,
537
+      95,    95,    95,   112,   -50,   100,    95,   -50,    56,   113,
538
+     -50,   115,    56,   -50,   116,    99,   -50,    -5,   -50,    56,
539
+     117,   118,    17,   -50,   121,   122,    56,   120,    99,   -50
539 540
 };
540 541
 
541 542
   /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
@@ -546,71 +547,73 @@ static const yytype_uint8 yydefact[] =
546 547
        0,     0,     0,     0,     1,     3,     0,     0,     7,     5,
547 548
        0,     0,     4,    10,     2,     7,    20,     0,     0,     0,
548 549
        0,     0,     0,    10,    15,     0,    11,    12,    13,     0,
549
-      14,     0,     0,     0,    44,    21,    35,     0,     0,     0,
550
-       9,    23,    19,    16,     6,    25,     0,     0,    26,     0,
551
-      32,     0,    56,     0,     0,    37,     0,     0,     0,     8,
552
-       0,     0,     0,    31,     0,     0,     0,     0,     0,     0,
553
-      55,     0,     0,     0,     0,     0,     0,     0,     0,    38,
554
-       0,     0,    34,    57,    24,    59,    22,    19,    17,    33,
555
-      27,    29,    28,    30,    58,    47,    48,    49,    50,    52,
556
-      51,    54,    53,     0,    45,    37,    18,    10,     0,    36,
557
-       0,    10,    39,     0,    42,    46,     0,    40,    10,     0,
558
-       0,     0,    41,     0,     0,    10,     0,    42,    43
550
+      14,     0,     0,     0,    45,    21,    36,     0,     0,     0,
551
+       9,    24,    19,    16,     6,    26,     0,     0,    27,     0,
552
+      33,     0,    57,     0,     0,    38,     0,     0,     0,     8,
553
+       0,     0,     0,    32,     0,     0,     0,     0,     0,     0,
554
+      56,     0,     0,     0,     0,     0,     0,     0,     0,    39,
555
+       0,     0,    35,    58,    25,    60,     0,    19,    17,    34,
556
+      28,    30,    29,    31,    59,    48,    49,    50,    51,    53,
557
+      52,    55,    54,     0,    46,    38,    23,    18,    10,     0,
558
+      37,     0,    10,    40,     0,    43,    47,     0,    41,    10,
559
+       0,     0,     0,    42,     0,     0,    10,     0,    43,    44
559 560
 };
560 561
 
561 562
   /* YYPGOTO[NTERM-NUM].  */
562 563
 static const yytype_int8 yypgoto[] =
563 564
 {
564
-     -50,   -50,   -50,   122,   109,   -50,   -22,   -50,   -50,    47,
565
-     -50,    76,   -50,   -29,   -50,    31,   -50,   -50,   -50,     8,
566
-     -50,   -50,   -50,   -49,   -13,   -50,   -50
565
+     -50,   -50,   -50,   123,   110,   -50,   -22,   -50,   -50,    49,
566
+     -50,    74,   -50,   -50,   -29,   -50,    32,   -50,   -50,   -50,
567
+      12,   -50,   -50,   -50,   -49,   -13,   -50,   -50
567 568
 };
568 569
 
569 570
   /* YYDEFGOTO[NTERM-NUM].  */
570 571
 static const yytype_int8 yydefgoto[] =
571 572
 {
572 573
       -1,     2,     7,     8,    12,    14,    22,    23,    24,    62,
573
-      25,    42,    26,    52,    56,    82,    27,   103,   114,   117,
574
-      28,    54,   108,    53,    50,    30,    39
574
+      25,    42,    60,    26,    52,    56,    82,    27,   103,   115,
575
+     118,    28,    54,   109,    53,    50,    30,    39
575 576
 };
576 577
 
577 578
   /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM.  If
578 579
      positive, shift that token.  If negative, reduce the rule whose
579 580
      number is the opposite.  If YYTABLE_NINF, syntax error.  */
580
-static const yytype_uint8 yytable[] =
581
+static const yytype_int16 yytable[] =
581 582
 {
582
-      29,    40,    70,    49,     1,    80,   118,     3,    57,    58,
583
+      29,    40,    70,    49,     1,    80,   119,     3,    57,    58,
583 584
       29,     4,    65,    66,    67,    68,     6,    63,    64,     5,
584
-      45,    84,    45,    46,   119,    46,    47,     9,    47,    67,
585
-      68,    86,    65,    66,    67,    68,    90,    91,    92,    93,
586
-      10,    85,    95,    96,    97,    98,    99,   100,   101,   102,
587
-      48,    51,    48,    65,    66,    67,    68,    65,    66,    67,
588
-      68,    11,    69,    32,    36,    71,    72,    73,    74,    75,
589
-      76,    37,   123,    16,    17,    77,    78,    13,    18,    33,
590
-      19,    20,    21,    34,    35,   110,    66,    67,    68,   113,
591
-      65,    66,    67,    68,    29,    89,   120,    38,    29,    65,
592
-      66,    67,    68,   126,    43,    29,    41,    44,    55,    59,
593
-      36,    60,    29,    61,    79,    81,    83,    88,   104,    94,
594
-     105,    68,   107,   111,    31,   121,   112,   115,   125,   116,
595
-     122,   124,   127,    15,   106,   128,   109,    87
585
+      45,    84,    45,    46,   120,    46,    47,     9,    47,    67,
586
+      68,    65,    66,    67,    68,    10,    90,    91,    92,    93,
587
+      85,    13,    95,    96,    97,    98,    99,   100,   101,   102,
588
+      48,    51,    48,    65,    66,    67,    68,   106,    65,    66,
589
+      67,    68,    11,    69,    36,    71,    72,    73,    74,    75,
590
+      76,    37,    32,   124,    33,    77,    78,    66,    67,    68,
591
+      16,    17,    34,    35,    38,    18,   111,    19,    20,    21,
592
+     114,    65,    66,    67,    68,    29,    89,   121,    43,    29,
593
+      65,    66,    67,    68,   127,    41,    29,    44,    55,    59,
594
+     -22,    61,    36,    29,    79,    81,    83,    86,   104,    88,
595
+     105,    94,    68,   108,   112,    31,   122,   113,   116,   117,
596
+     123,   125,   128,   126,    15,    87,   107,   110,     0,     0,
597
+     129
596 598
 };
597 599
 
598
-static const yytype_uint8 yycheck[] =
600
+static const yytype_int16 yycheck[] =
599 601
 {
600 602
       13,    23,    51,    32,    24,    54,    11,    23,    37,    38,
601 603
       23,     0,     5,     6,     7,     8,    24,    46,    47,     9,
602 604
        3,    14,     3,     6,    29,     6,     9,    33,     9,     7,
603
-       8,    60,     5,     6,     7,     8,    65,    66,    67,    68,
604
-      10,    14,    71,    72,    73,    74,    75,    76,    77,    78,
605
-      33,    34,    33,     5,     6,     7,     8,     5,     6,     7,
606
-       8,    15,    10,     9,     9,    17,    18,    19,    20,    21,
607
-      22,    16,   121,    24,    25,    27,    28,    11,    29,     9,
608
-      31,    32,    33,     9,    24,   107,     6,     7,     8,   111,
609
-       5,     6,     7,     8,   107,    10,   118,    26,   111,     5,
610
-       6,     7,     8,   125,    14,   118,    33,    14,    33,    12,
611
-       9,    16,   125,    15,    10,    15,    10,    14,    10,    14,
612
-      33,     8,    11,    11,    15,     9,    12,    12,    11,    30,
613
-      12,    10,    12,    11,    87,   127,   105,    61
605
+       8,     5,     6,     7,     8,    10,    65,    66,    67,    68,
606
+      14,    11,    71,    72,    73,    74,    75,    76,    77,    78,
607
+      33,    34,    33,     5,     6,     7,     8,    86,     5,     6,
608
+       7,     8,    15,    10,     9,    17,    18,    19,    20,    21,
609
+      22,    16,     9,   122,     9,    27,    28,     6,     7,     8,
610
+      24,    25,     9,    24,    26,    29,   108,    31,    32,    33,
611
+     112,     5,     6,     7,     8,   108,    10,   119,    14,   112,
612
+       5,     6,     7,     8,   126,    33,   119,    14,    33,    12,
613
+      16,    15,     9,   126,    10,    15,    10,    16,    10,    14,
614
+      33,    14,     8,    11,    11,    15,     9,    12,    12,    30,
615
+      12,    10,    12,    11,    11,    61,    87,   105,    -1,    -1,
616
+     128
614 617
 };
615 618
 
616 619
   /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
@@ -619,17 +622,17 @@ static const yytype_uint8 yystos[] =
619 622
 {
620 623
        0,    24,    36,    23,     0,     9,    24,    37,    38,    33,
621 624
       10,    15,    39,    11,    40,    38,    24,    25,    29,    31,
622
-      32,    33,    41,    42,    43,    45,    47,    51,    55,    59,
623
-      60,    39,     9,     9,     9,    24,     9,    16,    26,    61,
624
-      41,    33,    46,    14,    14,     3,     6,     9,    33,    48,
625
-      59,    34,    48,    58,    56,    33,    49,    48,    48,    12,
626
-      16,    15,    44,    48,    48,     5,     6,     7,     8,    10,
627
-      58,    17,    18,    19,    20,    21,    22,    27,    28,    10,
628
-      58,    15,    50,    10,    14,    14,    48,    46,    14,    10,
629
-      48,    48,    48,    48,    14,    48,    48,    48,    48,    48,
630
-      48,    48,    48,    52,    10,    33,    44,    11,    57,    50,
631
-      41,    11,    12,    41,    53,    12,    30,    54,    11,    29,
632
-      41,     9,    12,    58,    10,    11,    41,    12,    54
625
+      32,    33,    41,    42,    43,    45,    48,    52,    56,    60,
626
+      61,    39,     9,     9,     9,    24,     9,    16,    26,    62,
627
+      41,    33,    46,    14,    14,     3,     6,     9,    33,    49,
628
+      60,    34,    49,    59,    57,    33,    50,    49,    49,    12,
629
+      47,    15,    44,    49,    49,     5,     6,     7,     8,    10,
630
+      59,    17,    18,    19,    20,    21,    22,    27,    28,    10,
631
+      59,    15,    51,    10,    14,    14,    16,    46,    14,    10,
632
+      49,    49,    49,    49,    14,    49,    49,    49,    49,    49,
633
+      49,    49,    49,    53,    10,    33,    49,    44,    11,    58,
634
+      51,    41,    11,    12,    41,    54,    12,    30,    55,    11,
635
+      29,    41,     9,    12,    59,    10,    11,    41,    12,    55
633 636
 };
634 637
 
635 638
   /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
@@ -637,10 +640,11 @@ static const yytype_uint8 yyr1[] =
637 640
 {
638 641
        0,    35,    36,    37,    37,    38,    39,    39,    40,    41,
639 642
       41,    42,    42,    42,    42,    42,    42,    43,    44,    44,
640
-      45,    45,    46,    46,    47,    48,    48,    48,    48,    48,
641
-      48,    48,    48,    48,    49,    49,    50,    50,    52,    53,
642
-      51,    54,    54,    54,    56,    57,    55,    58,    58,    58,
643
-      58,    58,    58,    58,    58,    58,    58,    59,    60,    61
643
+      45,    45,    47,    46,    46,    48,    49,    49,    49,    49,
644
+      49,    49,    49,    49,    49,    50,    50,    51,    51,    53,
645
+      54,    52,    55,    55,    55,    57,    58,    56,    59,    59,
646
+      59,    59,    59,    59,    59,    59,    59,    59,    60,    61,
647
+      62
644 648
 };
645 649
 
646 650
   /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN.  */
@@ -648,10 +652,11 @@ static const yytype_uint8 yyr2[] =
648 652
 {
649 653
        0,     2,     6,     0,     2,     2,     4,     0,     4,     2,
650 654
        0,     1,     1,     1,     1,     1,     2,     4,     3,     0,
651
-       1,     2,     3,     1,     4,     1,     1,     3,     3,     3,
652
-       3,     2,     1,     3,     2,     0,     3,     0,     0,     0,
653
-      10,     4,     0,     9,     0,     0,     9,     3,     3,     3,
654
-       3,     3,     3,     3,     3,     2,     1,     4,     5,     3
655
+       1,     2,     0,     4,     1,     4,     1,     1,     3,     3,
656
+       3,     3,     2,     1,     3,     2,     0,     3,     0,     0,
657
+       0,    10,     4,     0,     9,     0,     0,     9,     3,     3,
658
+       3,     3,     3,     3,     3,     3,     2,     1,     4,     5,
659
+       3
655 660
 };
656 661
 
657 662
 
@@ -1330,112 +1335,118 @@ yyreduce:
1330 1335
         case 2:
1331 1336
 #line 78 "analyse_syntaxique.y" /* yacc.c:1646  */
1332 1337
     {}
1333
-#line 1334 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1338
+#line 1339 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1334 1339
     break;
1335 1340
 
1336 1341
   case 3:
1337 1342
 #line 80 "analyse_syntaxique.y" /* yacc.c:1646  */
1338 1343
     {printf("Sans params\n");}
1339
-#line 1340 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1344
+#line 1345 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1340 1345
     break;
1341 1346
 
1342 1347
   case 5:
1343 1348
 #line 83 "analyse_syntaxique.y" /* yacc.c:1646  */
1344 1349
     {printf("Parametre : %s\n", (yyvsp[0].id));}
1345
-#line 1346 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1350
+#line 1351 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1346 1351
     break;
1347 1352
 
1348 1353
   case 8:
1349 1354
 #line 90 "analyse_syntaxique.y" /* yacc.c:1646  */
1350 1355
     {printf("Dans body\n");}
1351
-#line 1352 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1356
+#line 1357 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1352 1357
     break;
1353 1358
 
1354 1359
   case 20:
1355 1360
 #line 107 "analyse_syntaxique.y" /* yacc.c:1646  */
1356 1361
     {type = TYPE_INT;}
1357
-#line 1358 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1362
+#line 1363 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1358 1363
     break;
1359 1364
 
1360 1365
   case 21:
1361 1366
 #line 108 "analyse_syntaxique.y" /* yacc.c:1646  */
1362 1367
     {type = TYPE_CONST_INT;}
1363
-#line 1364 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1368
+#line 1369 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1364 1369
     break;
1365 1370
 
1366 1371
   case 22:
1367 1372
 #line 110 "analyse_syntaxique.y" /* yacc.c:1646  */
1368
-    {add_symbole_top(&table, (yyvsp[-2].id), type, INITIALISED, table.depth); free_temp(&table);}
1369
-#line 1370 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1373
+    {add_symbole_top(&table, (yyvsp[0].id), type, INITIALISED, table.depth);}
1374
+#line 1375 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1370 1375
     break;
1371 1376
 
1372 1377
   case 23:
1378
+#line 110 "analyse_syntaxique.y" /* yacc.c:1646  */
1379
+    {int varAddr = variable_exists(&table, (yyvsp[-3].id)); generate_instruction_2(&array, COP, (yyvsp[0].nombre), varAddr); free_temp(&table);}
1380
+#line 1381 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1381
+    break;
1382
+
1383
+  case 24:
1373 1384
 #line 111 "analyse_syntaxique.y" /* yacc.c:1646  */
1374 1385
     {add_symbole_top(&table, (yyvsp[0].id), type, NOT_INITIALISED, table.depth);}
1375
-#line 1376 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1386
+#line 1387 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1376 1387
     break;
1377 1388
 
1378
-  case 24:
1389
+  case 25:
1379 1390
 #line 114 "analyse_syntaxique.y" /* yacc.c:1646  */
1380
-    {printf("Affectation : %s\n", (yyvsp[-3].id)); free_temp(&table);}
1381
-#line 1382 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1391
+    {int varAddr = variable_exists(&table, (yyvsp[-3].id)); generate_instruction_2(&array, COP, (yyvsp[-1].nombre), varAddr); free_temp(&table);}
1392
+#line 1393 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1382 1393
     break;
1383 1394
 
1384
-  case 25:
1395
+  case 26:
1385 1396
 #line 117 "analyse_syntaxique.y" /* yacc.c:1646  */
1386 1397
     {int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, (yyvsp[0].nombre)); (yyval.nombre) = vt;}
1387
-#line 1388 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1398
+#line 1399 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1388 1399
     break;
1389 1400
 
1390
-  case 26:
1401
+  case 27:
1391 1402
 #line 119 "analyse_syntaxique.y" /* yacc.c:1646  */
1392
-    {int vt = new_temp(&table); int varAddr = variable_exists(&table, (yyvsp[0].id)); generate_instruction_2(&array, CPY, vt, varAddr); (yyval.nombre) = vt;}
1393
-#line 1394 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1403
+    {int vt = new_temp(&table); int varAddr = variable_exists(&table, (yyvsp[0].id)); generate_instruction_2(&array, COP, varAddr, vt); (yyval.nombre) = vt;}
1404
+#line 1405 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1394 1405
     break;
1395 1406
 
1396
-  case 27:
1407
+  case 28:
1397 1408
 #line 121 "analyse_syntaxique.y" /* yacc.c:1646  */
1398 1409
     {generate_instruction_3(&array, ADD, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
1399
-#line 1400 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1410
+#line 1411 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1400 1411
     break;
1401 1412
 
1402
-  case 28:
1413
+  case 29:
1403 1414
 #line 122 "analyse_syntaxique.y" /* yacc.c:1646  */
1404 1415
     {generate_instruction_3(&array, MUL, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
1405
-#line 1406 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1416
+#line 1417 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1406 1417
     break;
1407 1418
 
1408
-  case 29:
1419
+  case 30:
1409 1420
 #line 123 "analyse_syntaxique.y" /* yacc.c:1646  */
1410 1421
     {generate_instruction_3(&array, SOU, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
1411
-#line 1412 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1422
+#line 1423 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1412 1423
     break;
1413 1424
 
1414
-  case 30:
1425
+  case 31:
1415 1426
 #line 124 "analyse_syntaxique.y" /* yacc.c:1646  */
1416 1427
     {generate_instruction_3(&array, DIV, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
1417
-#line 1418 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1428
+#line 1429 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1418 1429
     break;
1419 1430
 
1420
-  case 31:
1431
+  case 32:
1421 1432
 #line 125 "analyse_syntaxique.y" /* yacc.c:1646  */
1422 1433
     {printf("Variable negative\n");}
1423
-#line 1424 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1434
+#line 1435 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1424 1435
     break;
1425 1436
 
1426
-  case 32:
1437
+  case 33:
1427 1438
 #line 126 "analyse_syntaxique.y" /* yacc.c:1646  */
1428 1439
     {(yyval.nombre) = 1234;}
1429
-#line 1430 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1440
+#line 1441 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1430 1441
     break;
1431 1442
 
1432
-  case 33:
1443
+  case 34:
1433 1444
 #line 127 "analyse_syntaxique.y" /* yacc.c:1646  */
1434 1445
     {printf("Parenthèse\n"); (yyval.nombre) = (yyvsp[-1].nombre); }
1435
-#line 1436 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1446
+#line 1447 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1436 1447
     break;
1437 1448
 
1438
-  case 38:
1449
+  case 39:
1439 1450
 #line 136 "analyse_syntaxique.y" /* yacc.c:1646  */
1440 1451
     {
1441 1452
     //gen_jmpf(&table, &array, $3, -1);
@@ -1443,45 +1454,45 @@ yyreduce:
1443 1454
     free_temp(&table);
1444 1455
     (yyvsp[-3].nombre) = array.index;
1445 1456
 }
1446
-#line 1447 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1457
+#line 1458 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1447 1458
     break;
1448 1459
 
1449
-  case 39:
1460
+  case 40:
1450 1461
 #line 143 "analyse_syntaxique.y" /* yacc.c:1646  */
1451 1462
     {
1452 1463
     int adr_jmp = array.index;
1453 1464
     update_jmf(&array, (yyvsp[-7].nombre), adr_jmp);
1454 1465
 }
1455
-#line 1456 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1466
+#line 1467 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1456 1467
     break;
1457 1468
 
1458
-  case 40:
1469
+  case 41:
1459 1470
 #line 147 "analyse_syntaxique.y" /* yacc.c:1646  */
1460 1471
     {}
1461
-#line 1462 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1472
+#line 1473 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1462 1473
     break;
1463 1474
 
1464
-  case 41:
1475
+  case 42:
1465 1476
 #line 149 "analyse_syntaxique.y" /* yacc.c:1646  */
1466 1477
     {printf("else\n");}
1467
-#line 1468 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1478
+#line 1479 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1468 1479
     break;
1469 1480
 
1470
-  case 43:
1481
+  case 44:
1471 1482
 #line 151 "analyse_syntaxique.y" /* yacc.c:1646  */
1472 1483
     {printf("elsif\n");}
1473
-#line 1474 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1484
+#line 1485 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1474 1485
     break;
1475 1486
 
1476
-  case 44:
1487
+  case 45:
1477 1488
 #line 153 "analyse_syntaxique.y" /* yacc.c:1646  */
1478 1489
     {
1479 1490
 	(yyvsp[0].nombre) = array.index ;
1480 1491
 }
1481
-#line 1482 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1492
+#line 1493 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1482 1493
     break;
1483 1494
 
1484
-  case 45:
1495
+  case 46:
1485 1496
 #line 155 "analyse_syntaxique.y" /* yacc.c:1646  */
1486 1497
     {
1487 1498
 	//gen_jmpf(&table, &array, $4, -1);
@@ -1489,10 +1500,10 @@ yyreduce:
1489 1500
 	free_temp(&table);
1490 1501
 	(yyvsp[-4].nombre) = array.index;
1491 1502
 }
1492
-#line 1493 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1503
+#line 1504 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1493 1504
     break;
1494 1505
 
1495
-  case 46:
1506
+  case 47:
1496 1507
 #line 161 "analyse_syntaxique.y" /* yacc.c:1646  */
1497 1508
     {
1498 1509
 	int adr_jmp = array.index;
@@ -1500,89 +1511,89 @@ yyreduce:
1500 1511
 	//gen_jmpf(&table, &array, $1, $2);
1501 1512
 	generate_instruction_1(&array, JMP, (yyvsp[-7].nombre));
1502 1513
 }
1503
-#line 1504 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1514
+#line 1515 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1504 1515
     break;
1505 1516
 
1506
-  case 47:
1517
+  case 48:
1507 1518
 #line 169 "analyse_syntaxique.y" /* yacc.c:1646  */
1508 1519
     {generate_instruction_3(&array, EQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1509
-#line 1510 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1520
+#line 1521 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1510 1521
     break;
1511 1522
 
1512
-  case 48:
1523
+  case 49:
1513 1524
 #line 170 "analyse_syntaxique.y" /* yacc.c:1646  */
1514 1525
     {generate_instruction_3(&array, NEQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1515
-#line 1516 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1526
+#line 1527 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1516 1527
     break;
1517 1528
 
1518
-  case 49:
1529
+  case 50:
1519 1530
 #line 171 "analyse_syntaxique.y" /* yacc.c:1646  */
1520 1531
     {generate_instruction_3(&array, LT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1521
-#line 1522 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1532
+#line 1533 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1522 1533
     break;
1523 1534
 
1524
-  case 50:
1535
+  case 51:
1525 1536
 #line 172 "analyse_syntaxique.y" /* yacc.c:1646  */
1526 1537
     {generate_instruction_3(&array, GT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1527
-#line 1528 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1538
+#line 1539 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1528 1539
     break;
1529 1540
 
1530
-  case 51:
1541
+  case 52:
1531 1542
 #line 173 "analyse_syntaxique.y" /* yacc.c:1646  */
1532 1543
     {generate_instruction_3(&array, LTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1533
-#line 1534 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1544
+#line 1545 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1534 1545
     break;
1535 1546
 
1536
-  case 52:
1547
+  case 53:
1537 1548
 #line 174 "analyse_syntaxique.y" /* yacc.c:1646  */
1538 1549
     {generate_instruction_3(&array, GTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1539
-#line 1540 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1550
+#line 1551 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1540 1551
     break;
1541 1552
 
1542
-  case 53:
1553
+  case 54:
1543 1554
 #line 175 "analyse_syntaxique.y" /* yacc.c:1646  */
1544 1555
     {generate_instruction_3(&array, AND, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1545
-#line 1546 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1556
+#line 1557 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1546 1557
     break;
1547 1558
 
1548
-  case 54:
1559
+  case 55:
1549 1560
 #line 176 "analyse_syntaxique.y" /* yacc.c:1646  */
1550 1561
     {generate_instruction_3(&array, OR, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
1551
-#line 1552 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1562
+#line 1563 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1552 1563
     break;
1553 1564
 
1554
-  case 55:
1565
+  case 56:
1555 1566
 #line 177 "analyse_syntaxique.y" /* yacc.c:1646  */
1556 1567
     {generate_instruction_2(&array, NOT, (yyvsp[0].nombre), (yyvsp[0].nombre)); (yyval.nombre) = (yyvsp[0].nombre);}
1557
-#line 1558 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1568
+#line 1569 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1558 1569
     break;
1559 1570
 
1560
-  case 56:
1571
+  case 57:
1561 1572
 #line 178 "analyse_syntaxique.y" /* yacc.c:1646  */
1562 1573
     {(yyval.nombre) = (yyvsp[0].nombre); }
1563
-#line 1564 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1574
+#line 1575 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1564 1575
     break;
1565 1576
 
1566
-  case 57:
1567
-#line 182 "analyse_syntaxique.y" /* yacc.c:1646  */
1577
+  case 58:
1578
+#line 183 "analyse_syntaxique.y" /* yacc.c:1646  */
1568 1579
     {printf("Dans invocation\n");}
1569
-#line 1570 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1580
+#line 1581 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1570 1581
     break;
1571 1582
 
1572
-  case 58:
1573
-#line 185 "analyse_syntaxique.y" /* yacc.c:1646  */
1583
+  case 59:
1584
+#line 186 "analyse_syntaxique.y" /* yacc.c:1646  */
1574 1585
     {generate_instruction_1(&array, PRI, (yyvsp[-2].nombre)); free_temp(&table);}
1575
-#line 1576 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1586
+#line 1587 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1576 1587
     break;
1577 1588
 
1578
-  case 59:
1579
-#line 188 "analyse_syntaxique.y" /* yacc.c:1646  */
1589
+  case 60:
1590
+#line 189 "analyse_syntaxique.y" /* yacc.c:1646  */
1580 1591
     {(yyval.nombre) = generate_instruction_1(&array, RET, (yyvsp[-1].nombre)); free_temp(&table);}
1581
-#line 1582 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1592
+#line 1593 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1582 1593
     break;
1583 1594
 
1584 1595
 
1585
-#line 1586 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1596
+#line 1597 "analyse_syntaxique.tab.c" /* yacc.c:1646  */
1586 1597
       default: break;
1587 1598
     }
1588 1599
   /* User semantic actions sometimes alter yychar, and that requires
@@ -1810,7 +1821,7 @@ yyreturn:
1810 1821
 #endif
1811 1822
   return yyresult;
1812 1823
 }
1813
-#line 190 "analyse_syntaxique.y" /* yacc.c:1906  */
1824
+#line 191 "analyse_syntaxique.y" /* yacc.c:1906  */
1814 1825
 
1815 1826
 #include <stdio.h>
1816 1827
 void main(void){

+ 5
- 4
analyse_syntaxique.y View File

@@ -107,16 +107,16 @@ SuiteDecl: ;
107 107
 Type : tINT {type = TYPE_INT;} ; 
108 108
 Type : tCONST tINT {type = TYPE_CONST_INT;} ;
109 109
 
110
-Valeur : tVAR tAFFECTATION E {add_symbole_top(&table, $1, type, INITIALISED, table.depth); free_temp(&table);};
110
+Valeur : tVAR {add_symbole_top(&table, $1, type, INITIALISED, table.depth);} tAFFECTATION E {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, $4, varAddr); free_temp(&table);};
111 111
 Valeur : tVAR {add_symbole_top(&table, $1, type, NOT_INITIALISED, table.depth);};
112 112
 
113 113
 
114
-Aff : tVAR tAFFECTATION E tPV {printf("Affectation : %s\n", $1); free_temp(&table);};
114
+Aff : tVAR tAFFECTATION E tPV {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, $3, varAddr); free_temp(&table);};
115 115
 
116 116
 //E : tENTIER {int vt = gen_entier(&table, &array, $1); $$ = vt;};
117 117
 E : tENTIER {int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, $1); $$ = vt;};
118
-//E : tVAR {int vt = gen_var(&table, &array, $1); $$ = vt;};
119
-E : tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, CPY, vt, varAddr); $$ = vt;};
118
+//E : tVAR {int vt = gen_var(&table, &array, $1);  $$ = vt;};
119
+E : tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, varAddr, vt); $$ = vt;};
120 120
 //E : E tADD E {gen_arithmetique(&array, ADD, $1, $3); free_temp(&table); $$ = $1;} ;
121 121
 E : E tADD E {generate_instruction_3(&array, ADD, $1, $1, $3); free_temp(&table); $$ = $1;} ;
122 122
 E : E tMUL E {generate_instruction_3(&array, MUL, $1, $1, $3); free_temp(&table); $$ = $1;}  ;
@@ -179,6 +179,7 @@ Cond : E {$$ = $1; };
179 179
 
180 180
 
181 181
 
182
+
182 183
 Invocation : tVAR tPO  Args  tPF {printf("Dans invocation\n");};
183 184
 
184 185
 //Print : tPRINT tPO E tPF tPV {gen_print(&table, &array, $3);};

+ 5
- 5
gen_assembleur.c View File

@@ -24,8 +24,8 @@ char * operationName(enum operation op){
24 24
             return "DIV";
25 25
         case MUL:
26 26
             return "MUL";
27
-        case CPY:
28
-            return "CPY";
27
+        case COP:
28
+            return "COP";
29 29
         case AFC:
30 30
             return "AFC";
31 31
         case RET:
@@ -150,7 +150,7 @@ void exportInstructions(instructions_array * array){
150 150
             case JMF:
151 151
             case NOT:
152 152
             case AFC:
153
-            case CPY:
153
+            case COP:
154 154
                 fprintf(file, "%d\t %s %d %d\n", i, operationName(op), instru.reg1, instru.reg2);
155 155
                 break;
156 156
             //3 parameters
@@ -213,11 +213,11 @@ int gen_var(Table_Symboles * table, instructions_array * array, char * varName){
213 213
 
214 214
     //vérifier que non null
215 215
     instruction instru;
216
-    instru.operation = CPY;
216
+    instru.operation = COP;
217 217
     instru.reg1 = vt;
218 218
     instru.reg2 = varAddr;
219 219
 
220
-    printf("%d\t CPY %d %d\n",  array->index, vt, varAddr);
220
+    printf("%d\t COP %d %d\n",  array->index, vt, varAddr);
221 221
 
222 222
     if (array->index < INSTRUCTION_TABLE_SIZE){
223 223
         array->array[array->index] = instru;

+ 1
- 1
gen_assembleur.h View File

@@ -5,7 +5,7 @@
5 5
 
6 6
 #include "table_symboles.h"
7 7
 
8
-enum operation{ADD, SOU, MUL, DIV, CPY, AFC, RET, JMF, JMP, EQ, NEQ, LT, GT, LTE, GTE, AND, OR, NOT, PRI};
8
+enum operation{ADD, SOU, MUL, DIV, COP, AFC, RET, JMF, JMP, EQ, NEQ, LT, GT, LTE, GTE, AND, OR, NOT, PRI};
9 9
 
10 10
 typedef struct instruction{
11 11
     enum operation operation;

+ 21
- 14
instructions.txt View File

@@ -1,15 +1,22 @@
1 1
 0	 AFC 49 1
2
-1	 AFC 49 2
3
-2	 AFC 48 3
4
-3	 ADD 49 49 48
5
-4	 AFC 49 4
6
-5	 CPY 49 1
7
-6	 NOT 49 49
8
-7	 JPF 49 10
9
-8	 AFC 49 1
10
-9	 AFC 49 4
11
-10	 JPM 5
12
-11	 CPY 49 1
13
-12	 PRI 49
14
-13	 AFC 49 5
15
-14	 RET 49
2
+1	 COP 49 0
3
+2	 AFC 49 2
4
+3	 COP 49 1
5
+4	 AFC 49 2
6
+5	 AFC 48 3
7
+6	 ADD 49 49 48
8
+7	 COP 49 1
9
+8	 COP 1 49
10
+9	 NOT 49 49
11
+10	 JPF 49 15
12
+11	 AFC 49 1
13
+12	 COP 49 1
14
+13	 AFC 49 4
15
+14	 COP 49 2
16
+15	 AFC 49 4
17
+16	 AFC 48 2
18
+17	 COP 48 0
19
+18	 COP 1 48
20
+19	 PRI 48
21
+20	 AFC 48 5
22
+21	 RET 48

+ 7
- 4
script.sh View File

@@ -3,12 +3,15 @@ flex analyse_lexicale.lex
3 3
 gcc -w *.c -ly
4 4
 echo "
5 5
     int main(){
6
-        const int var1 = 1, var2;
7
-        int var2 = 2 + 3;
8
-        int var3, var4 = 4;
9
-        while (!var2){
6
+        int var1 = 1;
7
+        int var2 = 2;
8
+        var2 = 2 + 3;
9
+        int var3;
10
+        if (!var2){
10 11
             var2 = 1;
11 12
             var3 = 4;
13
+        } else {
14
+            var1 = 2;
12 15
         }
13 16
         printf(var2);
14 17
         return 5;

+ 17
- 26
xilinx/ALU/ALU.gise View File

@@ -24,9 +24,11 @@
24 24
   <files xmlns="http://www.xilinx.com/XMLSchema">
25 25
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
26 26
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
27
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
27
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
28
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_data_test_beh.prj"/>
29
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
30
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_data_test_isim_beh.wdb"/>
28 31
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
29
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
30 32
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
31 33
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
32 34
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
@@ -43,26 +45,23 @@
43 45
       <status xil_pn:value="SuccessfullyRun"/>
44 46
       <status xil_pn:value="ReadyToRun"/>
45 47
     </transform>
46
-    <transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618476857">
48
+    <transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618572938">
47 49
       <status xil_pn:value="SuccessfullyRun"/>
48 50
       <status xil_pn:value="ReadyToRun"/>
49
-      <status xil_pn:value="OutOfDateForInputs"/>
50
-      <status xil_pn:value="OutOfDateForOutputs"/>
51
-      <status xil_pn:value="InputChanged"/>
52
-      <status xil_pn:value="OutputChanged"/>
53 51
       <outfile xil_pn:name="alu.vhd"/>
54 52
       <outfile xil_pn:name="alu_test.vhd"/>
55 53
       <outfile xil_pn:name="bm.vhd"/>
54
+      <outfile xil_pn:name="bm_data_test.vhd"/>
56 55
       <outfile xil_pn:name="bm_instr.vhd"/>
57 56
       <outfile xil_pn:name="bm_instr_test.vhd"/>
58 57
       <outfile xil_pn:name="br.vhd"/>
59 58
       <outfile xil_pn:name="br_test.vhd"/>
60 59
     </transform>
61
-    <transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3025547276878941811" xil_pn:start_ts="1618476689">
60
+    <transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8940589992921887805" xil_pn:start_ts="1618572911">
62 61
       <status xil_pn:value="SuccessfullyRun"/>
63 62
       <status xil_pn:value="ReadyToRun"/>
64 63
     </transform>
65
-    <transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-323741304737568527" xil_pn:start_ts="1618476689">
64
+    <transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1570780385922884283" xil_pn:start_ts="1618572911">
66 65
       <status xil_pn:value="SuccessfullyRun"/>
67 66
       <status xil_pn:value="ReadyToRun"/>
68 67
     </transform>
@@ -70,43 +69,35 @@
70 69
       <status xil_pn:value="SuccessfullyRun"/>
71 70
       <status xil_pn:value="ReadyToRun"/>
72 71
     </transform>
73
-    <transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618476857">
72
+    <transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618572938">
74 73
       <status xil_pn:value="SuccessfullyRun"/>
75 74
       <status xil_pn:value="ReadyToRun"/>
76
-      <status xil_pn:value="OutOfDateForInputs"/>
77
-      <status xil_pn:value="OutOfDateForPredecessor"/>
78
-      <status xil_pn:value="OutOfDateForOutputs"/>
79
-      <status xil_pn:value="InputChanged"/>
80
-      <status xil_pn:value="OutputChanged"/>
81 75
       <outfile xil_pn:name="alu.vhd"/>
82 76
       <outfile xil_pn:name="alu_test.vhd"/>
83 77
       <outfile xil_pn:name="bm.vhd"/>
78
+      <outfile xil_pn:name="bm_data_test.vhd"/>
84 79
       <outfile xil_pn:name="bm_instr.vhd"/>
85 80
       <outfile xil_pn:name="bm_instr_test.vhd"/>
86 81
       <outfile xil_pn:name="br.vhd"/>
87 82
       <outfile xil_pn:name="br_test.vhd"/>
88 83
     </transform>
89
-    <transform xil_pn:end_ts="1618476859" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6397320030221382938" xil_pn:start_ts="1618476857">
84
+    <transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2732656885201204134" xil_pn:start_ts="1618572938">
90 85
       <status xil_pn:value="SuccessfullyRun"/>
91 86
       <status xil_pn:value="ReadyToRun"/>
92
-      <status xil_pn:value="OutOfDateForInputs"/>
93
-      <status xil_pn:value="OutOfDateForProperties"/>
94
-      <status xil_pn:value="OutOfDateForPredecessor"/>
95
-      <status xil_pn:value="InputChanged"/>
96
-      <outfile xil_pn:name="bm_instr_test_beh.prj"/>
97
-      <outfile xil_pn:name="bm_instr_test_isim_beh.exe"/>
87
+      <status xil_pn:value="OutOfDateForOutputs"/>
88
+      <status xil_pn:value="OutputChanged"/>
89
+      <outfile xil_pn:name="bm_data_test_beh.prj"/>
90
+      <outfile xil_pn:name="bm_data_test_isim_beh.exe"/>
98 91
       <outfile xil_pn:name="fuse.log"/>
99 92
       <outfile xil_pn:name="isim"/>
100 93
       <outfile xil_pn:name="xilinxsim.ini"/>
101 94
     </transform>
102
-    <transform xil_pn:end_ts="1618476860" xil_pn:in_ck="-6291911114616255345" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1618476859">
95
+    <transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5666824002871888647" xil_pn:start_ts="1618572940">
103 96
       <status xil_pn:value="SuccessfullyRun"/>
104 97
       <status xil_pn:value="ReadyToRun"/>
105
-      <status xil_pn:value="OutOfDateForProperties"/>
106
-      <status xil_pn:value="OutOfDateForPredecessor"/>
107 98
       <status xil_pn:value="OutOfDateForOutputs"/>
108 99
       <status xil_pn:value="OutputChanged"/>
109
-      <outfile xil_pn:name="bm_instr_test_isim_beh.wdb"/>
100
+      <outfile xil_pn:name="bm_data_test_isim_beh.wdb"/>
110 101
       <outfile xil_pn:name="isim.cmd"/>
111 102
     </transform>
112 103
   </transforms>

+ 13
- 7
xilinx/ALU/ALU.xise View File

@@ -36,19 +36,25 @@
36 36
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
37 37
     </file>
38 38
     <file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
39
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
39
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
40 40
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
41 41
     </file>
42 42
     <file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
43
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
43
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
44 44
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
45 45
     </file>
46 46
     <file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
47
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
47
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
48 48
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
49 49
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
50 50
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
51 51
     </file>
52
+    <file xil_pn:name="bm_data_test.vhd" xil_pn:type="FILE_VHDL">
53
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
54
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
55
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
56
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
57
+    </file>
52 58
   </files>
53 59
 
54 60
   <properties>
@@ -291,8 +297,8 @@
291 297
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
292 298
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
293 299
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
294
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
295
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="non-default"/>
300
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/bm_data_test" xil_pn:valueState="non-default"/>
301
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="non-default"/>
296 302
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
297 303
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
298 304
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -310,7 +316,7 @@
310 316
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
311 317
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
312 318
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
313
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="default"/>
319
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="default"/>
314 320
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
315 321
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
316 322
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -360,7 +366,7 @@
360 366
     <!--                                                                                  -->
361 367
     <!-- The following properties are for internal use only. These should not be modified.-->
362 368
     <!--                                                                                  -->
363
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_instr_test|behavior" xil_pn:valueState="non-default"/>
369
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_data_test|behavior" xil_pn:valueState="non-default"/>
364 370
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
365 371
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
366 372
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

+ 1
- 1
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File

@@ -8,7 +8,7 @@
8 8
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9 9
 
10 10
 <messages>
11
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
11
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd&quot; into library work</arg>
12 12
 </msg>
13 13
 
14 14
 </messages>

+ 6
- 6
xilinx/ALU/alu.vhd View File

@@ -57,17 +57,17 @@ begin
57 57
 		SUB <= A9 - B9;
58 58
 		MUL <= A * B;
59 59
 		
60
-		SBIS <= ADD(7 downto 0) when Ctrl_Alu = "01" else
61
-			  SUB(7 downto 0) when Ctrl_Alu = "10" else
62
-			  MUL(7 downto 0) when Ctrl_Alu = "11" else
60
+		SBIS <= ADD(7 downto 0) when Ctrl_Alu = "001" else
61
+			  SUB(7 downto 0) when Ctrl_Alu = "010" else
62
+			  MUL(7 downto 0) when Ctrl_Alu = "011" else
63 63
 			  (others => '0');
64 64
 		O <= '1' when MUL(15 downto 8) /= "00000000" and Ctrl_Alu = "011" else
65 65
 			  '0';
66
-		C <= '1' when ADD(8) = '1' and Ctrl_Alu = "01" else
66
+		C <= '1' when ADD(8) = '1' and Ctrl_Alu = "001" else
67 67
 			  '0';
68
-		N <= '1' when SUB(8) = '1' and Ctrl_Alu = "10" else
68
+		N <= '1' when SUB(8) = '1' and Ctrl_Alu = "010" else
69 69
 			  '0';
70
-		Z <= '1' when SBIS = "00000000" else
70
+		Z <= '1' when SBIS = "00000000" and Ctrl_Alu /= "000" else
71 71
 			  '0';
72 72
 		S <= SBIS;
73 73
 end Behavioral;

+ 1
- 1
xilinx/ALU/alu_summary.html View File

@@ -76,5 +76,5 @@
76 76
 </TABLE>
77 77
 
78 78
 
79
-<br><center><b>Date Generated:</b> 04/15/2021 - 10:56:37</center>
79
+<br><center><b>Date Generated:</b> 04/16/2021 - 12:24:04</center>
80 80
 </BODY></HTML>

+ 32
- 6
xilinx/ALU/alu_test.vhd View File

@@ -88,12 +88,38 @@ BEGIN
88 88
    stim_proc: process
89 89
    begin		
90 90
       -- hold reset state for 100 ns.
91
-      wait for 100 ns;	
92
-			B<="11111111";
93
-			A<="11111111";
94
-			Ctrl_Alu<="001" after 4 ns;
95
-			Ctrl_Alu<="010" after 8 ns;
96
-			Ctrl_Alu<="011" after 12 ns;
91
+      -- 3 op on random numbers
92
+		wait for 100 ns;
93
+		A<="00000111";		
94
+		B<="00000011";
95
+		wait for 100 ns;
96
+		Ctrl_Alu<="001";
97
+		wait for 30 ns;
98
+		Ctrl_Alu<="010";
99
+		wait for 30 ns;
100
+		Ctrl_Alu<="011";
101
+		wait for 30 ns;
102
+		Ctrl_Alu<="000";
103
+		wait for 30 ns;
104
+		A<="11111111";		
105
+		B<="11111111";
106
+		-- test carry
107
+		wait for 100 ns;
108
+		Ctrl_Alu<="001";
109
+		-- test multiply
110
+		wait for 30 ns;
111
+		Ctrl_Alu<="011";
112
+		--test null
113
+		wait for 30 ns;
114
+		Ctrl_Alu<="010";
115
+		wait for 30 ns;
116
+		Ctrl_Alu<="000";
117
+		wait for 30 ns;
118
+		-- test less than 0
119
+		A<="00000001";
120
+		wait for 30 ns;
121
+		Ctrl_Alu<="010";		
122
+		
97 123
       wait;
98 124
    end process;
99 125
 

+ 2
- 1
xilinx/ALU/bm.vhd View File

@@ -46,7 +46,8 @@ begin
46 46
 				data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
47 47
 			end if;
48 48
 			if RST='0' then 
49
-				registres <= (others => "00000000");
49
+				data_memory <= (others => "00000000");
50
+				OUT_data <= (others => '0');
50 51
 			end if;	
51 52
 	end process;
52 53
 

BIN
xilinx/ALU/bm_data_isim_beh.exe View File


+ 114
- 0
xilinx/ALU/bm_data_test.vhd View File

@@ -0,0 +1,114 @@
1
+--------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer:
4
+--
5
+-- Create Date:   13:17:22 04/16/2021
6
+-- Design Name:   
7
+-- Module Name:   /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd
8
+-- Project Name:  ALU
9
+-- Target Device:  
10
+-- Tool versions:  
11
+-- Description:   
12
+-- 
13
+-- VHDL Test Bench Created by ISE for module: bm_data
14
+-- 
15
+-- Dependencies:
16
+-- 
17
+-- Revision:
18
+-- Revision 0.01 - File Created
19
+-- Additional Comments:
20
+--
21
+-- Notes: 
22
+-- This testbench has been automatically generated using types std_logic and
23
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
+-- that these types always be used for the top-level I/O of a design in order
25
+-- to guarantee that the testbench will bind correctly to the post-implementation 
26
+-- simulation model.
27
+--------------------------------------------------------------------------------
28
+LIBRARY ieee;
29
+USE ieee.std_logic_1164.ALL;
30
+ 
31
+-- Uncomment the following library declaration if using
32
+-- arithmetic functions with Signed or Unsigned values
33
+--USE ieee.numeric_std.ALL;
34
+ 
35
+ENTITY bm_data_test IS
36
+END bm_data_test;
37
+ 
38
+ARCHITECTURE behavior OF bm_data_test IS 
39
+ 
40
+    -- Component Declaration for the Unit Under Test (UUT)
41
+ 
42
+    COMPONENT bm_data
43
+    PORT(
44
+         IN_addr : IN  std_logic_vector(7 downto 0);
45
+         IN_data : IN  std_logic_vector(7 downto 0);
46
+         RW : IN  std_logic;
47
+         RST : IN  std_logic;
48
+         CLK : IN  std_logic;
49
+         OUT_data : OUT  std_logic_vector(7 downto 0)
50
+        );
51
+    END COMPONENT;
52
+    
53
+
54
+   --Inputs
55
+   signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
56
+   signal IN_data : std_logic_vector(7 downto 0) := (others => '0');
57
+   signal RW : std_logic := '0';
58
+   signal RST : std_logic := '0';
59
+   signal CLK : std_logic := '0';
60
+
61
+ 	--Outputs
62
+   signal OUT_data : std_logic_vector(7 downto 0);
63
+
64
+   -- Clock period definitions
65
+   constant CLK_period : time := 10 ns;
66
+ 
67
+BEGIN
68
+ 
69
+	-- Instantiate the Unit Under Test (UUT)
70
+   uut: bm_data PORT MAP (
71
+          IN_addr => IN_addr,
72
+          IN_data => IN_data,
73
+          RW => RW,
74
+          RST => RST,
75
+          CLK => CLK,
76
+          OUT_data => OUT_data
77
+        );
78
+
79
+   -- Clock process definitions
80
+   CLK_process :process
81
+   begin
82
+		CLK <= '0';
83
+		wait for CLK_period/2;
84
+		CLK <= '1';
85
+		wait for CLK_period/2;
86
+   end process;
87
+ 
88
+
89
+   -- Stimulus process
90
+   stim_proc: process
91
+   begin		
92
+      -- hold reset state for 100 ns.
93
+      wait for 100 ns;	
94
+      wait for CLK_period*10;
95
+		RST <= '1';
96
+		IN_addr <= "00000001";
97
+		IN_data <= "00000001";
98
+		wait for 30 ns;
99
+		IN_addr <= "00000010";
100
+		IN_data <= "00000010";
101
+		
102
+		RW <= '1';
103
+		wait for 30 ns;
104
+		IN_addr <= "00000001";
105
+		wait for 30 ns;
106
+		IN_addr <= "00000000";
107
+		
108
+		wait for 30 ns;
109
+		RST <= '0';
110
+		
111
+      wait;
112
+   end process;
113
+
114
+END;

+ 2
- 0
xilinx/ALU/bm_data_test_beh.prj View File

@@ -0,0 +1,2 @@
1
+vhdl work "bm.vhd"
2
+vhdl work "bm_data_test.vhd"

BIN
xilinx/ALU/bm_data_test_isim_beh.exe View File


BIN
xilinx/ALU/bm_data_test_isim_beh.wdb View File


BIN
xilinx/ALU/bm_data_test_isim_beh1.wdb View File


+ 0
- 2
xilinx/ALU/bm_instr_test_beh.prj View File

@@ -1,2 +0,0 @@
1
-vhdl work "bm_instr.vhd"
2
-vhdl work "bm_instr_test.vhd"

BIN
xilinx/ALU/bm_instr_test_isim_beh.wdb View File


+ 15
- 10
xilinx/ALU/br_test.vhd View File

@@ -104,22 +104,27 @@ BEGIN
104 104
       wait for CLK_period*10;
105 105
 
106 106
       RST <= '1';
107
-		wait for 100 ns ;
107
+		--Write only
108
+		wait for 30 ns ;
108 109
 		DATA <= "10000000";
109
-		wait for 100 ns ;
110 110
 		W_addr <= "0000";
111
-		wait for 100 ns ;
112 111
 		W <= '1';
113
-		wait for 100 ns ;
114
-		
112
+		wait for 30 ns;
113
+		W_addr <= "0001";
114
+		DATA <= "10000100";
115
+		wait for 30 ns ;
116
+		-- Read only
115 117
 		W <= '0';
116
-		wait for 100 ns ;
117
-		
118 118
 		A_addr <= "0000" ;
119 119
 		B_addr <= "0001" ;
120
-		
121
-		
122
-
120
+		wait for 30 ns;
121
+		--Bypass for B and writting and reading at different addr for A
122
+		DATA <= "10000001";
123
+		wait for 30 ns;
124
+		W <= '1';
125
+		wait for 30 ns;
126
+		W <= '0';
127
+		RST <= '0';
123 128
       wait;
124 129
    end process;
125 130
 

+ 12
- 12
xilinx/ALU/fuse.log View File

@@ -1,25 +1,25 @@
1
-Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj work.bm_instr_test 
1
+Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj work.bm_data_test 
2 2
 ISim O.87xd (signature 0x8ddf5b5d)
3
-Number of CPUs detected in this system: 6
4
-Turning on mult-threading, number of parallel sub-compilation jobs: 12 
3
+Number of CPUs detected in this system: 12
4
+Turning on mult-threading, number of parallel sub-compilation jobs: 24 
5 5
 Determining compilation order of HDL files
6
-Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
7
-Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd" into library work
6
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
7
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd" into library work
8 8
 Starting static elaboration
9 9
 Completed static elaboration
10
-Fuse Memory Usage: 98500 KB
11
-Fuse CPU Usage: 750 ms
10
+Fuse Memory Usage: 98496 KB
11
+Fuse CPU Usage: 730 ms
12 12
 Compiling package standard
13 13
 Compiling package std_logic_1164
14 14
 Compiling package std_logic_arith
15 15
 Compiling package std_logic_unsigned
16 16
 Compiling package numeric_std
17
-Compiling architecture behavioral of entity bm_instr [bm_instr_default]
18
-Compiling architecture behavior of entity bm_instr_test
17
+Compiling architecture behavioral of entity bm_data [bm_data_default]
18
+Compiling architecture behavior of entity bm_data_test
19 19
 Time Resolution for simulation is 1ps.
20 20
 Waiting for 1 sub-compilation(s) to finish...
21 21
 Compiled 8 VHDL Units
22
-Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe
23
-Fuse Memory Usage: 936380 KB
24
-Fuse CPU Usage: 840 ms
22
+Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe
23
+Fuse Memory Usage: 1722956 KB
24
+Fuse CPU Usage: 850 ms
25 25
 GCC CPU Usage: 1640 ms

+ 1
- 1
xilinx/ALU/fuseRelaunch.cmd View File

@@ -1 +1 @@
1
--intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj" "work.bm_instr_test" 
1
+-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj" "work.bm_data_test" 

+ 1
- 1
xilinx/ALU/iseconfig/alu.xreport View File

@@ -1,7 +1,7 @@
1 1
 <?xml version='1.0' encoding='UTF-8'?>
2 2
 <report-views version="2.0" >
3 3
  <header>
4
-  <DateModified>2021-04-15T10:56:37</DateModified>
4
+  <DateModified>2021-04-16T12:24:04</DateModified>
5 5
   <ModuleName>alu</ModuleName>
6 6
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>

+ 1
- 1
xilinx/ALU/isim.log View File

@@ -1,5 +1,5 @@
1 1
 ISim log file
2
-Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb 
2
+Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.wdb 
3 3
 ISim O.87xd (signature 0x8ddf5b5d)
4 4
 WARNING: A WEBPACK license was found.
5 5
 WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe View File


xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimcrash.log View File


+ 29
- 0
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log View File

@@ -0,0 +1,29 @@
1
+Command line:
2
+   bm_data_test_isim_beh.exe
3
+     -simmode  gui
4
+     -simrunnum  0
5
+     -socket  53487
6
+
7
+Fri Apr 16 13:35:42 2021
8
+
9
+
10
+ Elaboration Time: 0.01 sec
11
+
12
+ Current Memory Usage: 183.046 Meg
13
+
14
+ Total Signals          : 13
15
+ Total Nets             : 2075
16
+ Total Signal Drivers   : 7
17
+ Total Blocks           : 6
18
+ Total Primitive Blocks : 5
19
+ Total Processes        : 3
20
+ Total Traceable Variables  : 16
21
+ Total Scalar Nets and Variables : 2577
22
+Total Line Count : 27
23
+
24
+ Total Simulation Time: 0.1 sec
25
+
26
+ Current Memory Usage: 258.548 Meg
27
+
28
+Fri Apr 16 13:37:04 2021
29
+

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 181
- 0
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.c View File

@@ -0,0 +1,181 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
25
+extern char *IEEE_P_2592010699;
26
+extern char *IEEE_P_1242562249;
27
+
28
+int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
29
+unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
30
+
31
+
32
+static void work_a_1466808984_3212880686_p_0(char *t0)
33
+{
34
+    char *t1;
35
+    char *t2;
36
+    char *t3;
37
+    unsigned char t4;
38
+    char *t5;
39
+    unsigned char t6;
40
+    char *t7;
41
+    int t8;
42
+    int t9;
43
+    unsigned int t10;
44
+    unsigned int t11;
45
+    unsigned int t12;
46
+    char *t13;
47
+    char *t14;
48
+    char *t15;
49
+    char *t16;
50
+    char *t17;
51
+    char *t18;
52
+    unsigned char t19;
53
+
54
+LAB0:    t1 = (t0 + 3144U);
55
+    t2 = *((char **)t1);
56
+    if (t2 == 0)
57
+        goto LAB2;
58
+
59
+LAB3:    goto *t2;
60
+
61
+LAB2:    xsi_set_current_line(42, ng0);
62
+
63
+LAB6:    t2 = (t0 + 3464);
64
+    *((int *)t2) = 1;
65
+    *((char **)t1) = &&LAB7;
66
+
67
+LAB1:    return;
68
+LAB4:    t5 = (t0 + 3464);
69
+    *((int *)t5) = 0;
70
+    xsi_set_current_line(43, ng0);
71
+    t2 = (t0 + 1352U);
72
+    t3 = *((char **)t2);
73
+    t4 = *((unsigned char *)t3);
74
+    t6 = (t4 == (unsigned char)3);
75
+    if (t6 != 0)
76
+        goto LAB8;
77
+
78
+LAB10:    xsi_set_current_line(46, ng0);
79
+    t2 = (t0 + 1192U);
80
+    t3 = *((char **)t2);
81
+    t2 = (t0 + 1032U);
82
+    t5 = *((char **)t2);
83
+    t2 = (t0 + 5968U);
84
+    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
85
+    t9 = (t8 - 0);
86
+    t10 = (t9 * 1);
87
+    t11 = (8U * t10);
88
+    t12 = (0U + t11);
89
+    t7 = (t0 + 3608);
90
+    t13 = (t7 + 56U);
91
+    t14 = *((char **)t13);
92
+    t15 = (t14 + 56U);
93
+    t16 = *((char **)t15);
94
+    memcpy(t16, t3, 8U);
95
+    xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
96
+
97
+LAB9:    xsi_set_current_line(48, ng0);
98
+    t2 = (t0 + 1512U);
99
+    t3 = *((char **)t2);
100
+    t4 = *((unsigned char *)t3);
101
+    t6 = (t4 == (unsigned char)2);
102
+    if (t6 != 0)
103
+        goto LAB11;
104
+
105
+LAB13:
106
+LAB12:    goto LAB2;
107
+
108
+LAB5:    t3 = (t0 + 1632U);
109
+    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
110
+    if (t4 == 1)
111
+        goto LAB4;
112
+    else
113
+        goto LAB6;
114
+
115
+LAB7:    goto LAB5;
116
+
117
+LAB8:    xsi_set_current_line(44, ng0);
118
+    t2 = (t0 + 1992U);
119
+    t5 = *((char **)t2);
120
+    t2 = (t0 + 1032U);
121
+    t7 = *((char **)t2);
122
+    t2 = (t0 + 5968U);
123
+    t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
124
+    t9 = (t8 - 0);
125
+    t10 = (t9 * 1);
126
+    xsi_vhdl_check_range_of_index(0, 255, 1, t8);
127
+    t11 = (8U * t10);
128
+    t12 = (0 + t11);
129
+    t13 = (t5 + t12);
130
+    t14 = (t0 + 3544);
131
+    t15 = (t14 + 56U);
132
+    t16 = *((char **)t15);
133
+    t17 = (t16 + 56U);
134
+    t18 = *((char **)t17);
135
+    memcpy(t18, t13, 8U);
136
+    xsi_driver_first_trans_fast_port(t14);
137
+    goto LAB9;
138
+
139
+LAB11:    xsi_set_current_line(49, ng0);
140
+    t2 = xsi_get_transient_memory(2048U);
141
+    memset(t2, 0, 2048U);
142
+    t5 = t2;
143
+    t7 = (t0 + 8123);
144
+    t19 = (8U != 0);
145
+    if (t19 == 1)
146
+        goto LAB14;
147
+
148
+LAB15:    t14 = (t0 + 3608);
149
+    t15 = (t14 + 56U);
150
+    t16 = *((char **)t15);
151
+    t17 = (t16 + 56U);
152
+    t18 = *((char **)t17);
153
+    memcpy(t18, t2, 2048U);
154
+    xsi_driver_first_trans_fast(t14);
155
+    xsi_set_current_line(50, ng0);
156
+    t2 = xsi_get_transient_memory(8U);
157
+    memset(t2, 0, 8U);
158
+    t3 = t2;
159
+    memset(t3, (unsigned char)2, 8U);
160
+    t5 = (t0 + 3544);
161
+    t7 = (t5 + 56U);
162
+    t13 = *((char **)t7);
163
+    t14 = (t13 + 56U);
164
+    t15 = *((char **)t14);
165
+    memcpy(t15, t2, 8U);
166
+    xsi_driver_first_trans_fast_port(t5);
167
+    goto LAB12;
168
+
169
+LAB14:    t10 = (2048U / 8U);
170
+    xsi_mem_set_data(t5, t7, 8U, t10);
171
+    goto LAB15;
172
+
173
+}
174
+
175
+
176
+extern void work_a_1466808984_3212880686_init()
177
+{
178
+	static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
179
+	xsi_register_didat("work_a_1466808984_3212880686", "isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
180
+	xsi_register_executes(pe);
181
+}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.lin64.o View File


+ 288
- 0
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.c View File

@@ -0,0 +1,288 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd";
25
+
26
+
27
+
28
+static void work_a_2533693612_2372691052_p_0(char *t0)
29
+{
30
+    char *t1;
31
+    char *t2;
32
+    char *t3;
33
+    char *t4;
34
+    char *t5;
35
+    char *t6;
36
+    int64 t7;
37
+    int64 t8;
38
+
39
+LAB0:    t1 = (t0 + 3104U);
40
+    t2 = *((char **)t1);
41
+    if (t2 == 0)
42
+        goto LAB2;
43
+
44
+LAB3:    goto *t2;
45
+
46
+LAB2:    xsi_set_current_line(82, ng0);
47
+    t2 = (t0 + 3736);
48
+    t3 = (t2 + 56U);
49
+    t4 = *((char **)t3);
50
+    t5 = (t4 + 56U);
51
+    t6 = *((char **)t5);
52
+    *((unsigned char *)t6) = (unsigned char)2;
53
+    xsi_driver_first_trans_fast(t2);
54
+    xsi_set_current_line(83, ng0);
55
+    t2 = (t0 + 2128U);
56
+    t3 = *((char **)t2);
57
+    t7 = *((int64 *)t3);
58
+    t8 = (t7 / 2);
59
+    t2 = (t0 + 2912);
60
+    xsi_process_wait(t2, t8);
61
+
62
+LAB6:    *((char **)t1) = &&LAB7;
63
+
64
+LAB1:    return;
65
+LAB4:    xsi_set_current_line(84, ng0);
66
+    t2 = (t0 + 3736);
67
+    t3 = (t2 + 56U);
68
+    t4 = *((char **)t3);
69
+    t5 = (t4 + 56U);
70
+    t6 = *((char **)t5);
71
+    *((unsigned char *)t6) = (unsigned char)3;
72
+    xsi_driver_first_trans_fast(t2);
73
+    xsi_set_current_line(85, ng0);
74
+    t2 = (t0 + 2128U);
75
+    t3 = *((char **)t2);
76
+    t7 = *((int64 *)t3);
77
+    t8 = (t7 / 2);
78
+    t2 = (t0 + 2912);
79
+    xsi_process_wait(t2, t8);
80
+
81
+LAB10:    *((char **)t1) = &&LAB11;
82
+    goto LAB1;
83
+
84
+LAB5:    goto LAB4;
85
+
86
+LAB7:    goto LAB5;
87
+
88
+LAB8:    goto LAB2;
89
+
90
+LAB9:    goto LAB8;
91
+
92
+LAB11:    goto LAB9;
93
+
94
+}
95
+
96
+static void work_a_2533693612_2372691052_p_1(char *t0)
97
+{
98
+    char *t1;
99
+    char *t2;
100
+    int64 t3;
101
+    char *t4;
102
+    int64 t5;
103
+    char *t6;
104
+    char *t7;
105
+    char *t8;
106
+    char *t9;
107
+    char *t10;
108
+
109
+LAB0:    t1 = (t0 + 3352U);
110
+    t2 = *((char **)t1);
111
+    if (t2 == 0)
112
+        goto LAB2;
113
+
114
+LAB3:    goto *t2;
115
+
116
+LAB2:    xsi_set_current_line(93, ng0);
117
+    t3 = (100 * 1000LL);
118
+    t2 = (t0 + 3160);
119
+    xsi_process_wait(t2, t3);
120
+
121
+LAB6:    *((char **)t1) = &&LAB7;
122
+
123
+LAB1:    return;
124
+LAB4:    xsi_set_current_line(94, ng0);
125
+    t2 = (t0 + 2128U);
126
+    t4 = *((char **)t2);
127
+    t3 = *((int64 *)t4);
128
+    t5 = (t3 * 10);
129
+    t2 = (t0 + 3160);
130
+    xsi_process_wait(t2, t5);
131
+
132
+LAB10:    *((char **)t1) = &&LAB11;
133
+    goto LAB1;
134
+
135
+LAB5:    goto LAB4;
136
+
137
+LAB7:    goto LAB5;
138
+
139
+LAB8:    xsi_set_current_line(95, ng0);
140
+    t2 = (t0 + 3800);
141
+    t4 = (t2 + 56U);
142
+    t6 = *((char **)t4);
143
+    t7 = (t6 + 56U);
144
+    t8 = *((char **)t7);
145
+    *((unsigned char *)t8) = (unsigned char)3;
146
+    xsi_driver_first_trans_fast(t2);
147
+    xsi_set_current_line(96, ng0);
148
+    t2 = (t0 + 6536);
149
+    t6 = (t0 + 3864);
150
+    t7 = (t6 + 56U);
151
+    t8 = *((char **)t7);
152
+    t9 = (t8 + 56U);
153
+    t10 = *((char **)t9);
154
+    memcpy(t10, t2, 8U);
155
+    xsi_driver_first_trans_fast(t6);
156
+    xsi_set_current_line(97, ng0);
157
+    t2 = (t0 + 6544);
158
+    t6 = (t0 + 3928);
159
+    t7 = (t6 + 56U);
160
+    t8 = *((char **)t7);
161
+    t9 = (t8 + 56U);
162
+    t10 = *((char **)t9);
163
+    memcpy(t10, t2, 8U);
164
+    xsi_driver_first_trans_fast(t6);
165
+    xsi_set_current_line(98, ng0);
166
+    t3 = (30 * 1000LL);
167
+    t2 = (t0 + 3160);
168
+    xsi_process_wait(t2, t3);
169
+
170
+LAB14:    *((char **)t1) = &&LAB15;
171
+    goto LAB1;
172
+
173
+LAB9:    goto LAB8;
174
+
175
+LAB11:    goto LAB9;
176
+
177
+LAB12:    xsi_set_current_line(99, ng0);
178
+    t2 = (t0 + 6552);
179
+    t6 = (t0 + 3864);
180
+    t7 = (t6 + 56U);
181
+    t8 = *((char **)t7);
182
+    t9 = (t8 + 56U);
183
+    t10 = *((char **)t9);
184
+    memcpy(t10, t2, 8U);
185
+    xsi_driver_first_trans_fast(t6);
186
+    xsi_set_current_line(100, ng0);
187
+    t2 = (t0 + 6560);
188
+    t6 = (t0 + 3928);
189
+    t7 = (t6 + 56U);
190
+    t8 = *((char **)t7);
191
+    t9 = (t8 + 56U);
192
+    t10 = *((char **)t9);
193
+    memcpy(t10, t2, 8U);
194
+    xsi_driver_first_trans_fast(t6);
195
+    xsi_set_current_line(102, ng0);
196
+    t2 = (t0 + 3992);
197
+    t4 = (t2 + 56U);
198
+    t6 = *((char **)t4);
199
+    t7 = (t6 + 56U);
200
+    t8 = *((char **)t7);
201
+    *((unsigned char *)t8) = (unsigned char)3;
202
+    xsi_driver_first_trans_fast(t2);
203
+    xsi_set_current_line(103, ng0);
204
+    t3 = (30 * 1000LL);
205
+    t2 = (t0 + 3160);
206
+    xsi_process_wait(t2, t3);
207
+
208
+LAB18:    *((char **)t1) = &&LAB19;
209
+    goto LAB1;
210
+
211
+LAB13:    goto LAB12;
212
+
213
+LAB15:    goto LAB13;
214
+
215
+LAB16:    xsi_set_current_line(104, ng0);
216
+    t2 = (t0 + 6568);
217
+    t6 = (t0 + 3864);
218
+    t7 = (t6 + 56U);
219
+    t8 = *((char **)t7);
220
+    t9 = (t8 + 56U);
221
+    t10 = *((char **)t9);
222
+    memcpy(t10, t2, 8U);
223
+    xsi_driver_first_trans_fast(t6);
224
+    xsi_set_current_line(105, ng0);
225
+    t3 = (30 * 1000LL);
226
+    t2 = (t0 + 3160);
227
+    xsi_process_wait(t2, t3);
228
+
229
+LAB22:    *((char **)t1) = &&LAB23;
230
+    goto LAB1;
231
+
232
+LAB17:    goto LAB16;
233
+
234
+LAB19:    goto LAB17;
235
+
236
+LAB20:    xsi_set_current_line(106, ng0);
237
+    t2 = (t0 + 6576);
238
+    t6 = (t0 + 3864);
239
+    t7 = (t6 + 56U);
240
+    t8 = *((char **)t7);
241
+    t9 = (t8 + 56U);
242
+    t10 = *((char **)t9);
243
+    memcpy(t10, t2, 8U);
244
+    xsi_driver_first_trans_fast(t6);
245
+    xsi_set_current_line(108, ng0);
246
+    t3 = (30 * 1000LL);
247
+    t2 = (t0 + 3160);
248
+    xsi_process_wait(t2, t3);
249
+
250
+LAB26:    *((char **)t1) = &&LAB27;
251
+    goto LAB1;
252
+
253
+LAB21:    goto LAB20;
254
+
255
+LAB23:    goto LAB21;
256
+
257
+LAB24:    xsi_set_current_line(109, ng0);
258
+    t2 = (t0 + 3800);
259
+    t4 = (t2 + 56U);
260
+    t6 = *((char **)t4);
261
+    t7 = (t6 + 56U);
262
+    t8 = *((char **)t7);
263
+    *((unsigned char *)t8) = (unsigned char)2;
264
+    xsi_driver_first_trans_fast(t2);
265
+    xsi_set_current_line(111, ng0);
266
+
267
+LAB30:    *((char **)t1) = &&LAB31;
268
+    goto LAB1;
269
+
270
+LAB25:    goto LAB24;
271
+
272
+LAB27:    goto LAB25;
273
+
274
+LAB28:    goto LAB2;
275
+
276
+LAB29:    goto LAB28;
277
+
278
+LAB31:    goto LAB29;
279
+
280
+}
281
+
282
+
283
+extern void work_a_2533693612_2372691052_init()
284
+{
285
+	static char *pe[] = {(void *)work_a_2533693612_2372691052_p_0,(void *)work_a_2533693612_2372691052_p_1};
286
+	xsi_register_didat("work_a_2533693612_2372691052", "isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat");
287
+	xsi_register_executes(pe);
288
+}

BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat View File


BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.lin64.o View File


xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c → xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.c View File

@@ -31,11 +31,11 @@ int main(int argc, char **argv)
31 31
     ieee_p_3499444699_init();
32 32
     ieee_p_3620187407_init();
33 33
     ieee_p_1242562249_init();
34
-    work_a_1802466774_3212880686_init();
35
-    work_a_4060154216_2372691052_init();
34
+    work_a_1466808984_3212880686_init();
35
+    work_a_2533693612_2372691052_init();
36 36
 
37 37
 
38
-    xsi_register_tops("work_a_4060154216_2372691052");
38
+    xsi_register_tops("work_a_2533693612_2372691052");
39 39
 
40 40
     IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
41 41
     xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o → xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/work/bm_data_test_isim_beh.exe_main.lin64.o View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe View File


+ 0
- 29
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   bm_instr_test_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  0
5
-     -socket  58139
6
-
7
-Thu Apr 15 10:54:21 2021
8
-
9
-
10
- Elaboration Time: 0 sec
11
-
12
- Current Memory Usage: 182.768 Meg
13
-
14
- Total Signals          : 7
15
- Total Nets             : 2065
16
- Total Signal Drivers   : 3
17
- Total Blocks           : 6
18
- Total Primitive Blocks : 5
19
- Total Processes        : 3
20
- Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 2567
22
-Total Line Count : 12
23
-
24
- Total Simulation Time: 0.02 sec
25
-
26
- Current Memory Usage: 258.269 Meg
27
-
28
-Thu Apr 15 10:54:49 2021
29
-

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 0
- 106
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File

@@ -1,106 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd";
25
-extern char *IEEE_P_2592010699;
26
-extern char *IEEE_P_1242562249;
27
-
28
-int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
29
-unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
30
-
31
-
32
-static void work_a_1802466774_3212880686_p_0(char *t0)
33
-{
34
-    char *t1;
35
-    char *t2;
36
-    char *t3;
37
-    unsigned char t4;
38
-    char *t5;
39
-    int t6;
40
-    int t7;
41
-    unsigned int t8;
42
-    unsigned int t9;
43
-    unsigned int t10;
44
-    char *t11;
45
-    char *t12;
46
-    char *t13;
47
-    char *t14;
48
-    char *t15;
49
-    char *t16;
50
-
51
-LAB0:    t1 = (t0 + 2664U);
52
-    t2 = *((char **)t1);
53
-    if (t2 == 0)
54
-        goto LAB2;
55
-
56
-LAB3:    goto *t2;
57
-
58
-LAB2:    xsi_set_current_line(40, ng0);
59
-
60
-LAB6:    t2 = (t0 + 2984);
61
-    *((int *)t2) = 1;
62
-    *((char **)t1) = &&LAB7;
63
-
64
-LAB1:    return;
65
-LAB4:    t5 = (t0 + 2984);
66
-    *((int *)t5) = 0;
67
-    xsi_set_current_line(41, ng0);
68
-    t2 = (t0 + 1512U);
69
-    t3 = *((char **)t2);
70
-    t2 = (t0 + 1032U);
71
-    t5 = *((char **)t2);
72
-    t2 = (t0 + 5232U);
73
-    t6 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
74
-    t7 = (t6 - 0);
75
-    t8 = (t7 * 1);
76
-    xsi_vhdl_check_range_of_index(0, 255, 1, t6);
77
-    t9 = (8U * t8);
78
-    t10 = (0 + t9);
79
-    t11 = (t3 + t10);
80
-    t12 = (t0 + 3064);
81
-    t13 = (t12 + 56U);
82
-    t14 = *((char **)t13);
83
-    t15 = (t14 + 56U);
84
-    t16 = *((char **)t15);
85
-    memcpy(t16, t11, 8U);
86
-    xsi_driver_first_trans_fast_port(t12);
87
-    goto LAB2;
88
-
89
-LAB5:    t3 = (t0 + 1312U);
90
-    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
91
-    if (t4 == 1)
92
-        goto LAB4;
93
-    else
94
-        goto LAB6;
95
-
96
-LAB7:    goto LAB5;
97
-
98
-}
99
-
100
-
101
-extern void work_a_1802466774_3212880686_init()
102
-{
103
-	static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
104
-	xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
105
-	xsi_register_executes(pe);
106
-}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o View File


+ 0
- 192
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c View File

@@ -1,192 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
25
-
26
-
27
-
28
-static void work_a_4060154216_2372691052_p_0(char *t0)
29
-{
30
-    char *t1;
31
-    char *t2;
32
-    char *t3;
33
-    char *t4;
34
-    char *t5;
35
-    char *t6;
36
-    int64 t7;
37
-    int64 t8;
38
-
39
-LAB0:    t1 = (t0 + 2624U);
40
-    t2 = *((char **)t1);
41
-    if (t2 == 0)
42
-        goto LAB2;
43
-
44
-LAB3:    goto *t2;
45
-
46
-LAB2:    xsi_set_current_line(73, ng0);
47
-    t2 = (t0 + 3256);
48
-    t3 = (t2 + 56U);
49
-    t4 = *((char **)t3);
50
-    t5 = (t4 + 56U);
51
-    t6 = *((char **)t5);
52
-    *((unsigned char *)t6) = (unsigned char)2;
53
-    xsi_driver_first_trans_fast(t2);
54
-    xsi_set_current_line(74, ng0);
55
-    t2 = (t0 + 1648U);
56
-    t3 = *((char **)t2);
57
-    t7 = *((int64 *)t3);
58
-    t8 = (t7 / 2);
59
-    t2 = (t0 + 2432);
60
-    xsi_process_wait(t2, t8);
61
-
62
-LAB6:    *((char **)t1) = &&LAB7;
63
-
64
-LAB1:    return;
65
-LAB4:    xsi_set_current_line(75, ng0);
66
-    t2 = (t0 + 3256);
67
-    t3 = (t2 + 56U);
68
-    t4 = *((char **)t3);
69
-    t5 = (t4 + 56U);
70
-    t6 = *((char **)t5);
71
-    *((unsigned char *)t6) = (unsigned char)3;
72
-    xsi_driver_first_trans_fast(t2);
73
-    xsi_set_current_line(76, ng0);
74
-    t2 = (t0 + 1648U);
75
-    t3 = *((char **)t2);
76
-    t7 = *((int64 *)t3);
77
-    t8 = (t7 / 2);
78
-    t2 = (t0 + 2432);
79
-    xsi_process_wait(t2, t8);
80
-
81
-LAB10:    *((char **)t1) = &&LAB11;
82
-    goto LAB1;
83
-
84
-LAB5:    goto LAB4;
85
-
86
-LAB7:    goto LAB5;
87
-
88
-LAB8:    goto LAB2;
89
-
90
-LAB9:    goto LAB8;
91
-
92
-LAB11:    goto LAB9;
93
-
94
-}
95
-
96
-static void work_a_4060154216_2372691052_p_1(char *t0)
97
-{
98
-    char *t1;
99
-    char *t2;
100
-    int64 t3;
101
-    char *t4;
102
-    int64 t5;
103
-    char *t6;
104
-    char *t7;
105
-    char *t8;
106
-    char *t9;
107
-    char *t10;
108
-
109
-LAB0:    t1 = (t0 + 2872U);
110
-    t2 = *((char **)t1);
111
-    if (t2 == 0)
112
-        goto LAB2;
113
-
114
-LAB3:    goto *t2;
115
-
116
-LAB2:    xsi_set_current_line(84, ng0);
117
-    t3 = (100 * 1000LL);
118
-    t2 = (t0 + 2680);
119
-    xsi_process_wait(t2, t3);
120
-
121
-LAB6:    *((char **)t1) = &&LAB7;
122
-
123
-LAB1:    return;
124
-LAB4:    xsi_set_current_line(86, ng0);
125
-    t2 = (t0 + 1648U);
126
-    t4 = *((char **)t2);
127
-    t3 = *((int64 *)t4);
128
-    t5 = (t3 * 10);
129
-    t2 = (t0 + 2680);
130
-    xsi_process_wait(t2, t5);
131
-
132
-LAB10:    *((char **)t1) = &&LAB11;
133
-    goto LAB1;
134
-
135
-LAB5:    goto LAB4;
136
-
137
-LAB7:    goto LAB5;
138
-
139
-LAB8:    xsi_set_current_line(88, ng0);
140
-    t2 = (t0 + 5544);
141
-    t6 = (t0 + 3320);
142
-    t7 = (t6 + 56U);
143
-    t8 = *((char **)t7);
144
-    t9 = (t8 + 56U);
145
-    t10 = *((char **)t9);
146
-    memcpy(t10, t2, 8U);
147
-    xsi_driver_first_trans_fast(t6);
148
-    xsi_set_current_line(89, ng0);
149
-    t3 = (100 * 1000LL);
150
-    t2 = (t0 + 2680);
151
-    xsi_process_wait(t2, t3);
152
-
153
-LAB14:    *((char **)t1) = &&LAB15;
154
-    goto LAB1;
155
-
156
-LAB9:    goto LAB8;
157
-
158
-LAB11:    goto LAB9;
159
-
160
-LAB12:    xsi_set_current_line(91, ng0);
161
-    t2 = (t0 + 5552);
162
-    t6 = (t0 + 3320);
163
-    t7 = (t6 + 56U);
164
-    t8 = *((char **)t7);
165
-    t9 = (t8 + 56U);
166
-    t10 = *((char **)t9);
167
-    memcpy(t10, t2, 8U);
168
-    xsi_driver_first_trans_fast(t6);
169
-    xsi_set_current_line(94, ng0);
170
-
171
-LAB18:    *((char **)t1) = &&LAB19;
172
-    goto LAB1;
173
-
174
-LAB13:    goto LAB12;
175
-
176
-LAB15:    goto LAB13;
177
-
178
-LAB16:    goto LAB2;
179
-
180
-LAB17:    goto LAB16;
181
-
182
-LAB19:    goto LAB17;
183
-
184
-}
185
-
186
-
187
-extern void work_a_4060154216_2372691052_init()
188
-{
189
-	static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
190
-	xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
191
-	xsi_register_executes(pe);
192
-}

BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat View File


BIN
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe View File


xilinx/ALU/isim/lockfile2 → xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimcrash.log View File


+ 29
- 0
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log View File

@@ -0,0 +1,29 @@
1
+Command line:
2
+   br_test_isim_beh.exe
3
+     -simmode  gui
4
+     -simrunnum  0
5
+     -socket  44223
6
+
7
+Fri Apr 16 13:26:05 2021
8
+
9
+
10
+ Elaboration Time: 0 sec
11
+
12
+ Current Memory Usage: 181.682 Meg
13
+
14
+ Total Signals          : 19
15
+ Total Nets             : 167
16
+ Total Signal Drivers   : 10
17
+ Total Blocks           : 6
18
+ Total Primitive Blocks : 5
19
+ Total Processes        : 5
20
+ Total Traceable Variables  : 16
21
+ Total Scalar Nets and Variables : 669
22
+Total Line Count : 33
23
+
24
+ Total Simulation Time: 0.01 sec
25
+
26
+ Current Memory Usage: 257.184 Meg
27
+
28
+Fri Apr 16 13:26:10 2021
29
+

BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 345
- 0
xilinx/ALU/isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.c View File

@@ -0,0 +1,345 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd";
25
+
26
+
27
+
28
+static void work_a_3692836482_2372691052_p_0(char *t0)
29
+{
30
+    char *t1;
31
+    char *t2;
32
+    char *t3;
33
+    char *t4;
34
+    char *t5;
35
+    char *t6;
36
+    int64 t7;
37
+    int64 t8;
38
+
39
+LAB0:    t1 = (t0 + 3584U);
40
+    t2 = *((char **)t1);
41
+    if (t2 == 0)
42
+        goto LAB2;
43
+
44
+LAB3:    goto *t2;
45
+
46
+LAB2:    xsi_set_current_line(91, ng0);
47
+    t2 = (t0 + 4216);
48
+    t3 = (t2 + 56U);
49
+    t4 = *((char **)t3);
50
+    t5 = (t4 + 56U);
51
+    t6 = *((char **)t5);
52
+    *((unsigned char *)t6) = (unsigned char)2;
53
+    xsi_driver_first_trans_fast(t2);
54
+    xsi_set_current_line(92, ng0);
55
+    t2 = (t0 + 2608U);
56
+    t3 = *((char **)t2);
57
+    t7 = *((int64 *)t3);
58
+    t8 = (t7 / 2);
59
+    t2 = (t0 + 3392);
60
+    xsi_process_wait(t2, t8);
61
+
62
+LAB6:    *((char **)t1) = &&LAB7;
63
+
64
+LAB1:    return;
65
+LAB4:    xsi_set_current_line(93, ng0);
66
+    t2 = (t0 + 4216);
67
+    t3 = (t2 + 56U);
68
+    t4 = *((char **)t3);
69
+    t5 = (t4 + 56U);
70
+    t6 = *((char **)t5);
71
+    *((unsigned char *)t6) = (unsigned char)3;
72
+    xsi_driver_first_trans_fast(t2);
73
+    xsi_set_current_line(94, ng0);
74
+    t2 = (t0 + 2608U);
75
+    t3 = *((char **)t2);
76
+    t7 = *((int64 *)t3);
77
+    t8 = (t7 / 2);
78
+    t2 = (t0 + 3392);
79
+    xsi_process_wait(t2, t8);
80
+
81
+LAB10:    *((char **)t1) = &&LAB11;
82
+    goto LAB1;
83
+
84
+LAB5:    goto LAB4;
85
+
86
+LAB7:    goto LAB5;
87
+
88
+LAB8:    goto LAB2;
89
+
90
+LAB9:    goto LAB8;
91
+
92
+LAB11:    goto LAB9;
93
+
94
+}
95
+
96
+static void work_a_3692836482_2372691052_p_1(char *t0)
97
+{
98
+    char *t1;
99
+    char *t2;
100
+    int64 t3;
101
+    char *t4;
102
+    int64 t5;
103
+    char *t6;
104
+    char *t7;
105
+    char *t8;
106
+    char *t9;
107
+    char *t10;
108
+
109
+LAB0:    t1 = (t0 + 3832U);
110
+    t2 = *((char **)t1);
111
+    if (t2 == 0)
112
+        goto LAB2;
113
+
114
+LAB3:    goto *t2;
115
+
116
+LAB2:    xsi_set_current_line(102, ng0);
117
+    t3 = (100 * 1000LL);
118
+    t2 = (t0 + 3640);
119
+    xsi_process_wait(t2, t3);
120
+
121
+LAB6:    *((char **)t1) = &&LAB7;
122
+
123
+LAB1:    return;
124
+LAB4:    xsi_set_current_line(104, ng0);
125
+    t2 = (t0 + 2608U);
126
+    t4 = *((char **)t2);
127
+    t3 = *((int64 *)t4);
128
+    t5 = (t3 * 10);
129
+    t2 = (t0 + 3640);
130
+    xsi_process_wait(t2, t5);
131
+
132
+LAB10:    *((char **)t1) = &&LAB11;
133
+    goto LAB1;
134
+
135
+LAB5:    goto LAB4;
136
+
137
+LAB7:    goto LAB5;
138
+
139
+LAB8:    xsi_set_current_line(106, ng0);
140
+    t2 = (t0 + 4280);
141
+    t4 = (t2 + 56U);
142
+    t6 = *((char **)t4);
143
+    t7 = (t6 + 56U);
144
+    t8 = *((char **)t7);
145
+    *((unsigned char *)t8) = (unsigned char)3;
146
+    xsi_driver_first_trans_fast(t2);
147
+    xsi_set_current_line(108, ng0);
148
+    t3 = (30 * 1000LL);
149
+    t2 = (t0 + 3640);
150
+    xsi_process_wait(t2, t3);
151
+
152
+LAB14:    *((char **)t1) = &&LAB15;
153
+    goto LAB1;
154
+
155
+LAB9:    goto LAB8;
156
+
157
+LAB11:    goto LAB9;
158
+
159
+LAB12:    xsi_set_current_line(109, ng0);
160
+    t2 = (t0 + 7400);
161
+    t6 = (t0 + 4344);
162
+    t7 = (t6 + 56U);
163
+    t8 = *((char **)t7);
164
+    t9 = (t8 + 56U);
165
+    t10 = *((char **)t9);
166
+    memcpy(t10, t2, 8U);
167
+    xsi_driver_first_trans_fast(t6);
168
+    xsi_set_current_line(110, ng0);
169
+    t2 = (t0 + 7408);
170
+    t6 = (t0 + 4408);
171
+    t7 = (t6 + 56U);
172
+    t8 = *((char **)t7);
173
+    t9 = (t8 + 56U);
174
+    t10 = *((char **)t9);
175
+    memcpy(t10, t2, 4U);
176
+    xsi_driver_first_trans_fast(t6);
177
+    xsi_set_current_line(111, ng0);
178
+    t2 = (t0 + 4472);
179
+    t4 = (t2 + 56U);
180
+    t6 = *((char **)t4);
181
+    t7 = (t6 + 56U);
182
+    t8 = *((char **)t7);
183
+    *((unsigned char *)t8) = (unsigned char)3;
184
+    xsi_driver_first_trans_fast(t2);
185
+    xsi_set_current_line(112, ng0);
186
+    t3 = (30 * 1000LL);
187
+    t2 = (t0 + 3640);
188
+    xsi_process_wait(t2, t3);
189
+
190
+LAB18:    *((char **)t1) = &&LAB19;
191
+    goto LAB1;
192
+
193
+LAB13:    goto LAB12;
194
+
195
+LAB15:    goto LAB13;
196
+
197
+LAB16:    xsi_set_current_line(113, ng0);
198
+    t2 = (t0 + 7412);
199
+    t6 = (t0 + 4408);
200
+    t7 = (t6 + 56U);
201
+    t8 = *((char **)t7);
202
+    t9 = (t8 + 56U);
203
+    t10 = *((char **)t9);
204
+    memcpy(t10, t2, 4U);
205
+    xsi_driver_first_trans_fast(t6);
206
+    xsi_set_current_line(114, ng0);
207
+    t2 = (t0 + 7416);
208
+    t6 = (t0 + 4344);
209
+    t7 = (t6 + 56U);
210
+    t8 = *((char **)t7);
211
+    t9 = (t8 + 56U);
212
+    t10 = *((char **)t9);
213
+    memcpy(t10, t2, 8U);
214
+    xsi_driver_first_trans_fast(t6);
215
+    xsi_set_current_line(115, ng0);
216
+    t3 = (30 * 1000LL);
217
+    t2 = (t0 + 3640);
218
+    xsi_process_wait(t2, t3);
219
+
220
+LAB22:    *((char **)t1) = &&LAB23;
221
+    goto LAB1;
222
+
223
+LAB17:    goto LAB16;
224
+
225
+LAB19:    goto LAB17;
226
+
227
+LAB20:    xsi_set_current_line(117, ng0);
228
+    t2 = (t0 + 4472);
229
+    t4 = (t2 + 56U);
230
+    t6 = *((char **)t4);
231
+    t7 = (t6 + 56U);
232
+    t8 = *((char **)t7);
233
+    *((unsigned char *)t8) = (unsigned char)2;
234
+    xsi_driver_first_trans_fast(t2);
235
+    xsi_set_current_line(118, ng0);
236
+    t2 = (t0 + 7424);
237
+    t6 = (t0 + 4536);
238
+    t7 = (t6 + 56U);
239
+    t8 = *((char **)t7);
240
+    t9 = (t8 + 56U);
241
+    t10 = *((char **)t9);
242
+    memcpy(t10, t2, 4U);
243
+    xsi_driver_first_trans_fast(t6);
244
+    xsi_set_current_line(119, ng0);
245
+    t2 = (t0 + 7428);
246
+    t6 = (t0 + 4600);
247
+    t7 = (t6 + 56U);
248