else ok + tests et pipeline ok
This commit is contained in:
Foussats Morgane
parent
344eba4dde
commit
bc2a2ee47d
78 changed files with 2254 additions and 1085 deletions
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a.out
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a.out
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@ -413,16 +413,16 @@ union yyalloc
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/* YYFINAL -- State number of the termination state. */
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#define YYFINAL 4
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/* YYLAST -- Last index in YYTABLE. */
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#define YYLAST 137
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#define YYLAST 140
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/* YYNTOKENS -- Number of terminals. */
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#define YYNTOKENS 35
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/* YYNNTS -- Number of nonterminals. */
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#define YYNNTS 27
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#define YYNNTS 28
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/* YYNRULES -- Number of rules. */
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#define YYNRULES 59
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#define YYNRULES 60
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/* YYNSTATES -- Number of states. */
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#define YYNSTATES 129
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#define YYNSTATES 130
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/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
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by yylex, with out-of-bounds checking. */
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@ -473,10 +473,11 @@ static const yytype_uint8 yyrline[] =
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{
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0, 78, 78, 80, 81, 83, 86, 87, 90, 92,
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93, 95, 96, 97, 98, 99, 100, 102, 104, 105,
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107, 108, 110, 111, 114, 117, 119, 121, 122, 123,
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124, 125, 126, 127, 130, 131, 133, 134, 136, 143,
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136, 149, 150, 151, 153, 155, 153, 169, 170, 171,
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172, 173, 174, 175, 176, 177, 178, 182, 185, 188
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107, 108, 110, 110, 111, 114, 117, 119, 121, 122,
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123, 124, 125, 126, 127, 130, 131, 133, 134, 136,
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143, 136, 149, 150, 151, 153, 155, 153, 169, 170,
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171, 172, 173, 174, 175, 176, 177, 178, 183, 186,
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189
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};
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#endif
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@ -491,8 +492,8 @@ static const char *const yytname[] =
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"tINT", "tPRINT", "tRETURN", "tOR", "tAND", "tIF", "tELSE", "tWHILE",
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"tCONST", "tVAR", "tNOT", "$accept", "Main", "Params", "Param",
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"SuiteParams", "Body", "Instructions", "Instruction", "Decl",
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"SuiteDecl", "Type", "Valeur", "Aff", "E", "Args", "SuiteArgs", "If",
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"$@1", "$@2", "Else", "While", "$@3", "$@4", "Cond", "Invocation",
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"SuiteDecl", "Type", "Valeur", "$@1", "Aff", "E", "Args", "SuiteArgs",
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"If", "$@2", "$@3", "Else", "While", "$@4", "$@5", "Cond", "Invocation",
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"Print", "Return", YY_NULLPTR
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};
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#endif
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@ -514,7 +515,7 @@ static const yytype_uint16 yytoknum[] =
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#define yypact_value_is_default(Yystate) \
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(!!((Yystate) == (-50)))
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#define YYTABLE_NINF -1
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#define YYTABLE_NINF -23
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#define yytable_value_is_error(Yytable_value) \
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0
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@ -523,19 +524,19 @@ static const yytype_uint16 yytoknum[] =
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STATE-NUM. */
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static const yytype_int8 yypact[] =
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{
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-20, -16, 11, 10, -50, -8, -6, 30, 46, -50,
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66, -8, -50, 49, -50, 46, -50, 54, 70, 74,
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60, 55, 71, 49, -50, 73, -50, -50, -50, 90,
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-20, -16, 11, 10, -50, -8, -6, 25, 47, -50,
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30, -8, -50, 56, -50, 47, -50, 63, 65, 73,
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59, 55, 58, 56, -50, 72, -50, -50, -50, 84,
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-50, 93, 19, 17, -50, -50, 75, 19, 19, 97,
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-50, 95, 98, -50, -50, -50, 19, 19, 101, 52,
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-50, 17, 48, 104, 17, 100, 106, 7, 27, -50,
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19, 73, 103, 22, 85, 19, 19, 19, 19, 105,
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-50, 94, 96, -50, -50, -50, 19, 19, 103, 53,
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-50, 17, 48, 104, 17, 100, 106, 7, 26, -50,
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101, 72, 105, 22, 86, 19, 19, 19, 19, 107,
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-50, 19, 19, 19, 19, 19, 19, 19, 19, -50,
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108, 87, -50, -50, -50, -50, 94, 98, -50, -50,
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80, 22, 113, -50, -50, 94, 94, 94, 94, 94,
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94, 94, 94, 111, -50, 100, -50, 49, 112, -50,
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114, 49, -50, 115, 99, -50, -5, -50, 49, 116,
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118, 17, -50, 121, 117, 49, 120, 99, -50
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108, 87, -50, -50, -50, -50, 19, 96, -50, -50,
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71, 22, 114, -50, -50, 95, 95, 95, 95, 95,
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95, 95, 95, 112, -50, 100, 95, -50, 56, 113,
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-50, 115, 56, -50, 116, 99, -50, -5, -50, 56,
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117, 118, 17, -50, 121, 122, 56, 120, 99, -50
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};
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/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
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@ -546,71 +547,73 @@ static const yytype_uint8 yydefact[] =
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0, 0, 0, 0, 1, 3, 0, 0, 7, 5,
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0, 0, 4, 10, 2, 7, 20, 0, 0, 0,
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0, 0, 0, 10, 15, 0, 11, 12, 13, 0,
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14, 0, 0, 0, 44, 21, 35, 0, 0, 0,
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9, 23, 19, 16, 6, 25, 0, 0, 26, 0,
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32, 0, 56, 0, 0, 37, 0, 0, 0, 8,
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0, 0, 0, 31, 0, 0, 0, 0, 0, 0,
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55, 0, 0, 0, 0, 0, 0, 0, 0, 38,
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0, 0, 34, 57, 24, 59, 22, 19, 17, 33,
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27, 29, 28, 30, 58, 47, 48, 49, 50, 52,
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51, 54, 53, 0, 45, 37, 18, 10, 0, 36,
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0, 10, 39, 0, 42, 46, 0, 40, 10, 0,
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0, 0, 41, 0, 0, 10, 0, 42, 43
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14, 0, 0, 0, 45, 21, 36, 0, 0, 0,
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9, 24, 19, 16, 6, 26, 0, 0, 27, 0,
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33, 0, 57, 0, 0, 38, 0, 0, 0, 8,
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0, 0, 0, 32, 0, 0, 0, 0, 0, 0,
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56, 0, 0, 0, 0, 0, 0, 0, 0, 39,
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0, 0, 35, 58, 25, 60, 0, 19, 17, 34,
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28, 30, 29, 31, 59, 48, 49, 50, 51, 53,
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52, 55, 54, 0, 46, 38, 23, 18, 10, 0,
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37, 0, 10, 40, 0, 43, 47, 0, 41, 10,
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0, 0, 0, 42, 0, 0, 10, 0, 43, 44
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};
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/* YYPGOTO[NTERM-NUM]. */
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static const yytype_int8 yypgoto[] =
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{
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-50, -50, -50, 122, 109, -50, -22, -50, -50, 47,
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-50, 76, -50, -29, -50, 31, -50, -50, -50, 8,
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-50, -50, -50, -49, -13, -50, -50
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-50, -50, -50, 123, 110, -50, -22, -50, -50, 49,
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-50, 74, -50, -50, -29, -50, 32, -50, -50, -50,
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12, -50, -50, -50, -49, -13, -50, -50
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};
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/* YYDEFGOTO[NTERM-NUM]. */
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static const yytype_int8 yydefgoto[] =
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{
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-1, 2, 7, 8, 12, 14, 22, 23, 24, 62,
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25, 42, 26, 52, 56, 82, 27, 103, 114, 117,
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28, 54, 108, 53, 50, 30, 39
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25, 42, 60, 26, 52, 56, 82, 27, 103, 115,
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118, 28, 54, 109, 53, 50, 30, 39
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};
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/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
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positive, shift that token. If negative, reduce the rule whose
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number is the opposite. If YYTABLE_NINF, syntax error. */
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static const yytype_uint8 yytable[] =
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static const yytype_int16 yytable[] =
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{
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29, 40, 70, 49, 1, 80, 118, 3, 57, 58,
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29, 40, 70, 49, 1, 80, 119, 3, 57, 58,
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29, 4, 65, 66, 67, 68, 6, 63, 64, 5,
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45, 84, 45, 46, 119, 46, 47, 9, 47, 67,
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68, 86, 65, 66, 67, 68, 90, 91, 92, 93,
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10, 85, 95, 96, 97, 98, 99, 100, 101, 102,
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48, 51, 48, 65, 66, 67, 68, 65, 66, 67,
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68, 11, 69, 32, 36, 71, 72, 73, 74, 75,
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76, 37, 123, 16, 17, 77, 78, 13, 18, 33,
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19, 20, 21, 34, 35, 110, 66, 67, 68, 113,
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65, 66, 67, 68, 29, 89, 120, 38, 29, 65,
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66, 67, 68, 126, 43, 29, 41, 44, 55, 59,
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36, 60, 29, 61, 79, 81, 83, 88, 104, 94,
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105, 68, 107, 111, 31, 121, 112, 115, 125, 116,
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122, 124, 127, 15, 106, 128, 109, 87
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45, 84, 45, 46, 120, 46, 47, 9, 47, 67,
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68, 65, 66, 67, 68, 10, 90, 91, 92, 93,
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85, 13, 95, 96, 97, 98, 99, 100, 101, 102,
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48, 51, 48, 65, 66, 67, 68, 106, 65, 66,
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67, 68, 11, 69, 36, 71, 72, 73, 74, 75,
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76, 37, 32, 124, 33, 77, 78, 66, 67, 68,
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16, 17, 34, 35, 38, 18, 111, 19, 20, 21,
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114, 65, 66, 67, 68, 29, 89, 121, 43, 29,
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65, 66, 67, 68, 127, 41, 29, 44, 55, 59,
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-22, 61, 36, 29, 79, 81, 83, 86, 104, 88,
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105, 94, 68, 108, 112, 31, 122, 113, 116, 117,
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123, 125, 128, 126, 15, 87, 107, 110, 0, 0,
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129
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};
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static const yytype_uint8 yycheck[] =
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static const yytype_int16 yycheck[] =
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{
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13, 23, 51, 32, 24, 54, 11, 23, 37, 38,
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23, 0, 5, 6, 7, 8, 24, 46, 47, 9,
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3, 14, 3, 6, 29, 6, 9, 33, 9, 7,
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8, 60, 5, 6, 7, 8, 65, 66, 67, 68,
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10, 14, 71, 72, 73, 74, 75, 76, 77, 78,
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33, 34, 33, 5, 6, 7, 8, 5, 6, 7,
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8, 15, 10, 9, 9, 17, 18, 19, 20, 21,
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22, 16, 121, 24, 25, 27, 28, 11, 29, 9,
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31, 32, 33, 9, 24, 107, 6, 7, 8, 111,
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5, 6, 7, 8, 107, 10, 118, 26, 111, 5,
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6, 7, 8, 125, 14, 118, 33, 14, 33, 12,
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9, 16, 125, 15, 10, 15, 10, 14, 10, 14,
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33, 8, 11, 11, 15, 9, 12, 12, 11, 30,
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12, 10, 12, 11, 87, 127, 105, 61
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8, 5, 6, 7, 8, 10, 65, 66, 67, 68,
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14, 11, 71, 72, 73, 74, 75, 76, 77, 78,
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33, 34, 33, 5, 6, 7, 8, 86, 5, 6,
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7, 8, 15, 10, 9, 17, 18, 19, 20, 21,
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22, 16, 9, 122, 9, 27, 28, 6, 7, 8,
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24, 25, 9, 24, 26, 29, 108, 31, 32, 33,
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112, 5, 6, 7, 8, 108, 10, 119, 14, 112,
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5, 6, 7, 8, 126, 33, 119, 14, 33, 12,
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16, 15, 9, 126, 10, 15, 10, 16, 10, 14,
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33, 14, 8, 11, 11, 15, 9, 12, 12, 30,
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12, 10, 12, 11, 11, 61, 87, 105, -1, -1,
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128
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};
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/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
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@ -619,17 +622,17 @@ static const yytype_uint8 yystos[] =
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{
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0, 24, 36, 23, 0, 9, 24, 37, 38, 33,
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10, 15, 39, 11, 40, 38, 24, 25, 29, 31,
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32, 33, 41, 42, 43, 45, 47, 51, 55, 59,
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60, 39, 9, 9, 9, 24, 9, 16, 26, 61,
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41, 33, 46, 14, 14, 3, 6, 9, 33, 48,
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59, 34, 48, 58, 56, 33, 49, 48, 48, 12,
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16, 15, 44, 48, 48, 5, 6, 7, 8, 10,
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58, 17, 18, 19, 20, 21, 22, 27, 28, 10,
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58, 15, 50, 10, 14, 14, 48, 46, 14, 10,
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48, 48, 48, 48, 14, 48, 48, 48, 48, 48,
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48, 48, 48, 52, 10, 33, 44, 11, 57, 50,
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41, 11, 12, 41, 53, 12, 30, 54, 11, 29,
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41, 9, 12, 58, 10, 11, 41, 12, 54
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32, 33, 41, 42, 43, 45, 48, 52, 56, 60,
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61, 39, 9, 9, 9, 24, 9, 16, 26, 62,
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41, 33, 46, 14, 14, 3, 6, 9, 33, 49,
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60, 34, 49, 59, 57, 33, 50, 49, 49, 12,
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47, 15, 44, 49, 49, 5, 6, 7, 8, 10,
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59, 17, 18, 19, 20, 21, 22, 27, 28, 10,
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59, 15, 51, 10, 14, 14, 16, 46, 14, 10,
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49, 49, 49, 49, 14, 49, 49, 49, 49, 49,
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49, 49, 49, 53, 10, 33, 49, 44, 11, 58,
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51, 41, 11, 12, 41, 54, 12, 30, 55, 11,
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29, 41, 9, 12, 59, 10, 11, 41, 12, 55
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};
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/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
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@ -637,10 +640,11 @@ static const yytype_uint8 yyr1[] =
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{
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0, 35, 36, 37, 37, 38, 39, 39, 40, 41,
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41, 42, 42, 42, 42, 42, 42, 43, 44, 44,
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45, 45, 46, 46, 47, 48, 48, 48, 48, 48,
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48, 48, 48, 48, 49, 49, 50, 50, 52, 53,
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51, 54, 54, 54, 56, 57, 55, 58, 58, 58,
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58, 58, 58, 58, 58, 58, 58, 59, 60, 61
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45, 45, 47, 46, 46, 48, 49, 49, 49, 49,
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49, 49, 49, 49, 49, 50, 50, 51, 51, 53,
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54, 52, 55, 55, 55, 57, 58, 56, 59, 59,
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59, 59, 59, 59, 59, 59, 59, 59, 60, 61,
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62
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};
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/* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
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@ -648,10 +652,11 @@ static const yytype_uint8 yyr2[] =
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{
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0, 2, 6, 0, 2, 2, 4, 0, 4, 2,
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0, 1, 1, 1, 1, 1, 2, 4, 3, 0,
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1, 2, 3, 1, 4, 1, 1, 3, 3, 3,
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3, 2, 1, 3, 2, 0, 3, 0, 0, 0,
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10, 4, 0, 9, 0, 0, 9, 3, 3, 3,
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3, 3, 3, 3, 3, 2, 1, 4, 5, 3
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1, 2, 0, 4, 1, 4, 1, 1, 3, 3,
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3, 3, 2, 1, 3, 2, 0, 3, 0, 0,
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0, 10, 4, 0, 9, 0, 0, 9, 3, 3,
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3, 3, 3, 3, 3, 3, 2, 1, 4, 5,
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3
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};
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@ -1330,112 +1335,118 @@ yyreduce:
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case 2:
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#line 78 "analyse_syntaxique.y" /* yacc.c:1646 */
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{}
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#line 1334 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1339 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 3:
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#line 80 "analyse_syntaxique.y" /* yacc.c:1646 */
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{printf("Sans params\n");}
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#line 1340 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1345 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 5:
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#line 83 "analyse_syntaxique.y" /* yacc.c:1646 */
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{printf("Parametre : %s\n", (yyvsp[0].id));}
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#line 1346 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1351 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 8:
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#line 90 "analyse_syntaxique.y" /* yacc.c:1646 */
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{printf("Dans body\n");}
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#line 1352 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1357 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 20:
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#line 107 "analyse_syntaxique.y" /* yacc.c:1646 */
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{type = TYPE_INT;}
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#line 1358 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1363 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 21:
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#line 108 "analyse_syntaxique.y" /* yacc.c:1646 */
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{type = TYPE_CONST_INT;}
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#line 1364 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 1369 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 22:
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#line 110 "analyse_syntaxique.y" /* yacc.c:1646 */
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{add_symbole_top(&table, (yyvsp[-2].id), type, INITIALISED, table.depth); free_temp(&table);}
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#line 1370 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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{add_symbole_top(&table, (yyvsp[0].id), type, INITIALISED, table.depth);}
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#line 1375 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 23:
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#line 111 "analyse_syntaxique.y" /* yacc.c:1646 */
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{add_symbole_top(&table, (yyvsp[0].id), type, NOT_INITIALISED, table.depth);}
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#line 1376 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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#line 110 "analyse_syntaxique.y" /* yacc.c:1646 */
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{int varAddr = variable_exists(&table, (yyvsp[-3].id)); generate_instruction_2(&array, COP, (yyvsp[0].nombre), varAddr); free_temp(&table);}
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#line 1381 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
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break;
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case 24:
|
||||
#line 114 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Affectation : %s\n", (yyvsp[-3].id)); free_temp(&table);}
|
||||
#line 1382 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 111 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{add_symbole_top(&table, (yyvsp[0].id), type, NOT_INITIALISED, table.depth);}
|
||||
#line 1387 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 25:
|
||||
#line 117 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, (yyvsp[0].nombre)); (yyval.nombre) = vt;}
|
||||
#line 1388 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 114 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{int varAddr = variable_exists(&table, (yyvsp[-3].id)); generate_instruction_2(&array, COP, (yyvsp[-1].nombre), varAddr); free_temp(&table);}
|
||||
#line 1393 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 26:
|
||||
#line 119 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{int vt = new_temp(&table); int varAddr = variable_exists(&table, (yyvsp[0].id)); generate_instruction_2(&array, CPY, vt, varAddr); (yyval.nombre) = vt;}
|
||||
#line 1394 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 117 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, (yyvsp[0].nombre)); (yyval.nombre) = vt;}
|
||||
#line 1399 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 27:
|
||||
#line 121 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, ADD, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1400 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 119 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{int vt = new_temp(&table); int varAddr = variable_exists(&table, (yyvsp[0].id)); generate_instruction_2(&array, COP, varAddr, vt); (yyval.nombre) = vt;}
|
||||
#line 1405 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 28:
|
||||
#line 122 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, MUL, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1406 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 121 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, ADD, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1411 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 29:
|
||||
#line 123 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, SOU, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1412 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 122 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, MUL, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1417 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 30:
|
||||
#line 124 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, DIV, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1418 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 123 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, SOU, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1423 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 31:
|
||||
#line 125 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Variable negative\n");}
|
||||
#line 1424 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 124 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, DIV, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[-2].nombre);}
|
||||
#line 1429 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 32:
|
||||
#line 126 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{(yyval.nombre) = 1234;}
|
||||
#line 1430 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 125 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Variable negative\n");}
|
||||
#line 1435 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 33:
|
||||
#line 127 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Parenthèse\n"); (yyval.nombre) = (yyvsp[-1].nombre); }
|
||||
#line 1436 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 126 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{(yyval.nombre) = 1234;}
|
||||
#line 1441 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 38:
|
||||
case 34:
|
||||
#line 127 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Parenthèse\n"); (yyval.nombre) = (yyvsp[-1].nombre); }
|
||||
#line 1447 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 39:
|
||||
#line 136 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{
|
||||
//gen_jmpf(&table, &array, $3, -1);
|
||||
|
|
@ -1443,45 +1454,45 @@ yyreduce:
|
|||
free_temp(&table);
|
||||
(yyvsp[-3].nombre) = array.index;
|
||||
}
|
||||
#line 1447 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1458 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 39:
|
||||
case 40:
|
||||
#line 143 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{
|
||||
int adr_jmp = array.index;
|
||||
update_jmf(&array, (yyvsp[-7].nombre), adr_jmp);
|
||||
}
|
||||
#line 1456 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 40:
|
||||
#line 147 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{}
|
||||
#line 1462 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1467 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 41:
|
||||
#line 149 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("else\n");}
|
||||
#line 1468 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 147 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{}
|
||||
#line 1473 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 43:
|
||||
#line 151 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("elsif\n");}
|
||||
#line 1474 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
case 42:
|
||||
#line 149 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("else\n");}
|
||||
#line 1479 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 44:
|
||||
#line 151 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("elsif\n");}
|
||||
#line 1485 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 45:
|
||||
#line 153 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{
|
||||
(yyvsp[0].nombre) = array.index ;
|
||||
}
|
||||
#line 1482 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1493 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 45:
|
||||
case 46:
|
||||
#line 155 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{
|
||||
//gen_jmpf(&table, &array, $4, -1);
|
||||
|
|
@ -1489,10 +1500,10 @@ yyreduce:
|
|||
free_temp(&table);
|
||||
(yyvsp[-4].nombre) = array.index;
|
||||
}
|
||||
#line 1493 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1504 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 46:
|
||||
case 47:
|
||||
#line 161 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{
|
||||
int adr_jmp = array.index;
|
||||
|
|
@ -1500,89 +1511,89 @@ yyreduce:
|
|||
//gen_jmpf(&table, &array, $1, $2);
|
||||
generate_instruction_1(&array, JMP, (yyvsp[-7].nombre));
|
||||
}
|
||||
#line 1504 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 47:
|
||||
#line 169 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, EQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1510 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1515 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 48:
|
||||
#line 170 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, NEQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1516 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 169 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, EQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1521 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 49:
|
||||
#line 171 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, LT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1522 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 170 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, NEQ, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1527 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 50:
|
||||
#line 172 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, GT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1528 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 171 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, LT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1533 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 51:
|
||||
#line 173 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, LTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1534 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 172 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, GT, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1539 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 52:
|
||||
#line 174 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, GTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1540 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 173 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, LTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1545 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 53:
|
||||
#line 175 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, AND, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1546 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 174 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, GTE, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1551 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 54:
|
||||
#line 176 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, OR, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1552 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 175 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, AND, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1557 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 55:
|
||||
#line 177 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_2(&array, NOT, (yyvsp[0].nombre), (yyvsp[0].nombre)); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1558 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 176 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_3(&array, OR, (yyvsp[-2].nombre), (yyvsp[-2].nombre), (yyvsp[0].nombre)); free_temp(&table); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1563 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 56:
|
||||
#line 178 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{(yyval.nombre) = (yyvsp[0].nombre); }
|
||||
#line 1564 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 177 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_2(&array, NOT, (yyvsp[0].nombre), (yyvsp[0].nombre)); (yyval.nombre) = (yyvsp[0].nombre);}
|
||||
#line 1569 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 57:
|
||||
#line 182 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Dans invocation\n");}
|
||||
#line 1570 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 178 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{(yyval.nombre) = (yyvsp[0].nombre); }
|
||||
#line 1575 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 58:
|
||||
#line 185 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_1(&array, PRI, (yyvsp[-2].nombre)); free_temp(&table);}
|
||||
#line 1576 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 183 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{printf("Dans invocation\n");}
|
||||
#line 1581 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 59:
|
||||
#line 188 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
#line 186 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{generate_instruction_1(&array, PRI, (yyvsp[-2].nombre)); free_temp(&table);}
|
||||
#line 1587 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
case 60:
|
||||
#line 189 "analyse_syntaxique.y" /* yacc.c:1646 */
|
||||
{(yyval.nombre) = generate_instruction_1(&array, RET, (yyvsp[-1].nombre)); free_temp(&table);}
|
||||
#line 1582 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1593 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
break;
|
||||
|
||||
|
||||
#line 1586 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
#line 1597 "analyse_syntaxique.tab.c" /* yacc.c:1646 */
|
||||
default: break;
|
||||
}
|
||||
/* User semantic actions sometimes alter yychar, and that requires
|
||||
|
|
@ -1810,7 +1821,7 @@ yyreturn:
|
|||
#endif
|
||||
return yyresult;
|
||||
}
|
||||
#line 190 "analyse_syntaxique.y" /* yacc.c:1906 */
|
||||
#line 191 "analyse_syntaxique.y" /* yacc.c:1906 */
|
||||
|
||||
#include <stdio.h>
|
||||
void main(void){
|
||||
|
|
|
|||
|
|
@ -107,16 +107,16 @@ SuiteDecl: ;
|
|||
Type : tINT {type = TYPE_INT;} ;
|
||||
Type : tCONST tINT {type = TYPE_CONST_INT;} ;
|
||||
|
||||
Valeur : tVAR tAFFECTATION E {add_symbole_top(&table, $1, type, INITIALISED, table.depth); free_temp(&table);};
|
||||
Valeur : tVAR {add_symbole_top(&table, $1, type, INITIALISED, table.depth);} tAFFECTATION E {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, $4, varAddr); free_temp(&table);};
|
||||
Valeur : tVAR {add_symbole_top(&table, $1, type, NOT_INITIALISED, table.depth);};
|
||||
|
||||
|
||||
Aff : tVAR tAFFECTATION E tPV {printf("Affectation : %s\n", $1); free_temp(&table);};
|
||||
Aff : tVAR tAFFECTATION E tPV {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, $3, varAddr); free_temp(&table);};
|
||||
|
||||
//E : tENTIER {int vt = gen_entier(&table, &array, $1); $$ = vt;};
|
||||
E : tENTIER {int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, $1); $$ = vt;};
|
||||
//E : tVAR {int vt = gen_var(&table, &array, $1); $$ = vt;};
|
||||
E : tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, CPY, vt, varAddr); $$ = vt;};
|
||||
//E : tVAR {int vt = gen_var(&table, &array, $1); $$ = vt;};
|
||||
E : tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, varAddr, vt); $$ = vt;};
|
||||
//E : E tADD E {gen_arithmetique(&array, ADD, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
E : E tADD E {generate_instruction_3(&array, ADD, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
E : E tMUL E {generate_instruction_3(&array, MUL, $1, $1, $3); free_temp(&table); $$ = $1;} ;
|
||||
|
|
@ -179,6 +179,7 @@ Cond : E {$$ = $1; };
|
|||
|
||||
|
||||
|
||||
|
||||
Invocation : tVAR tPO Args tPF {printf("Dans invocation\n");};
|
||||
|
||||
//Print : tPRINT tPO E tPF tPV {gen_print(&table, &array, $3);};
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@ char * operationName(enum operation op){
|
|||
return "DIV";
|
||||
case MUL:
|
||||
return "MUL";
|
||||
case CPY:
|
||||
return "CPY";
|
||||
case COP:
|
||||
return "COP";
|
||||
case AFC:
|
||||
return "AFC";
|
||||
case RET:
|
||||
|
|
@ -150,7 +150,7 @@ void exportInstructions(instructions_array * array){
|
|||
case JMF:
|
||||
case NOT:
|
||||
case AFC:
|
||||
case CPY:
|
||||
case COP:
|
||||
fprintf(file, "%d\t %s %d %d\n", i, operationName(op), instru.reg1, instru.reg2);
|
||||
break;
|
||||
//3 parameters
|
||||
|
|
@ -213,11 +213,11 @@ int gen_var(Table_Symboles * table, instructions_array * array, char * varName){
|
|||
|
||||
//vérifier que non null
|
||||
instruction instru;
|
||||
instru.operation = CPY;
|
||||
instru.operation = COP;
|
||||
instru.reg1 = vt;
|
||||
instru.reg2 = varAddr;
|
||||
|
||||
printf("%d\t CPY %d %d\n", array->index, vt, varAddr);
|
||||
printf("%d\t COP %d %d\n", array->index, vt, varAddr);
|
||||
|
||||
if (array->index < INSTRUCTION_TABLE_SIZE){
|
||||
array->array[array->index] = instru;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
#include "table_symboles.h"
|
||||
|
||||
enum operation{ADD, SOU, MUL, DIV, CPY, AFC, RET, JMF, JMP, EQ, NEQ, LT, GT, LTE, GTE, AND, OR, NOT, PRI};
|
||||
enum operation{ADD, SOU, MUL, DIV, COP, AFC, RET, JMF, JMP, EQ, NEQ, LT, GT, LTE, GTE, AND, OR, NOT, PRI};
|
||||
|
||||
typedef struct instruction{
|
||||
enum operation operation;
|
||||
|
|
|
|||
|
|
@ -1,15 +1,22 @@
|
|||
0 AFC 49 1
|
||||
1 AFC 49 2
|
||||
2 AFC 48 3
|
||||
3 ADD 49 49 48
|
||||
4 AFC 49 4
|
||||
5 CPY 49 1
|
||||
6 NOT 49 49
|
||||
7 JPF 49 10
|
||||
8 AFC 49 1
|
||||
9 AFC 49 4
|
||||
10 JPM 5
|
||||
11 CPY 49 1
|
||||
12 PRI 49
|
||||
13 AFC 49 5
|
||||
14 RET 49
|
||||
1 COP 49 0
|
||||
2 AFC 49 2
|
||||
3 COP 49 1
|
||||
4 AFC 49 2
|
||||
5 AFC 48 3
|
||||
6 ADD 49 49 48
|
||||
7 COP 49 1
|
||||
8 COP 1 49
|
||||
9 NOT 49 49
|
||||
10 JPF 49 15
|
||||
11 AFC 49 1
|
||||
12 COP 49 1
|
||||
13 AFC 49 4
|
||||
14 COP 49 2
|
||||
15 AFC 49 4
|
||||
16 AFC 48 2
|
||||
17 COP 48 0
|
||||
18 COP 1 48
|
||||
19 PRI 48
|
||||
20 AFC 48 5
|
||||
21 RET 48
|
||||
|
|
|
|||
11
script.sh
11
script.sh
|
|
@ -3,12 +3,15 @@ flex analyse_lexicale.lex
|
|||
gcc -w *.c -ly
|
||||
echo "
|
||||
int main(){
|
||||
const int var1 = 1, var2;
|
||||
int var2 = 2 + 3;
|
||||
int var3, var4 = 4;
|
||||
while (!var2){
|
||||
int var1 = 1;
|
||||
int var2 = 2;
|
||||
var2 = 2 + 3;
|
||||
int var3;
|
||||
if (!var2){
|
||||
var2 = 1;
|
||||
var3 = 4;
|
||||
} else {
|
||||
var1 = 2;
|
||||
}
|
||||
printf(var2);
|
||||
return 5;
|
||||
|
|
|
|||
|
|
@ -24,9 +24,11 @@
|
|||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_data_test_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_data_test_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
|
||||
|
|
@ -43,26 +45,23 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618476857">
|
||||
<transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618572938">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="alu.vhd"/>
|
||||
<outfile xil_pn:name="alu_test.vhd"/>
|
||||
<outfile xil_pn:name="bm.vhd"/>
|
||||
<outfile xil_pn:name="bm_data_test.vhd"/>
|
||||
<outfile xil_pn:name="bm_instr.vhd"/>
|
||||
<outfile xil_pn:name="bm_instr_test.vhd"/>
|
||||
<outfile xil_pn:name="br.vhd"/>
|
||||
<outfile xil_pn:name="br_test.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3025547276878941811" xil_pn:start_ts="1618476689">
|
||||
<transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8940589992921887805" xil_pn:start_ts="1618572911">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-323741304737568527" xil_pn:start_ts="1618476689">
|
||||
<transform xil_pn:end_ts="1618572911" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1570780385922884283" xil_pn:start_ts="1618572911">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
|
@ -70,43 +69,35 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618476857">
|
||||
<transform xil_pn:end_ts="1618572938" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618572938">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="alu.vhd"/>
|
||||
<outfile xil_pn:name="alu_test.vhd"/>
|
||||
<outfile xil_pn:name="bm.vhd"/>
|
||||
<outfile xil_pn:name="bm_data_test.vhd"/>
|
||||
<outfile xil_pn:name="bm_instr.vhd"/>
|
||||
<outfile xil_pn:name="bm_instr_test.vhd"/>
|
||||
<outfile xil_pn:name="br.vhd"/>
|
||||
<outfile xil_pn:name="br_test.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476859" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6397320030221382938" xil_pn:start_ts="1618476857">
|
||||
<transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7705911264551896315" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2732656885201204134" xil_pn:start_ts="1618572938">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="bm_instr_test_beh.prj"/>
|
||||
<outfile xil_pn:name="bm_instr_test_isim_beh.exe"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="bm_data_test_beh.prj"/>
|
||||
<outfile xil_pn:name="bm_data_test_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1618476860" xil_pn:in_ck="-6291911114616255345" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1618476859">
|
||||
<transform xil_pn:end_ts="1618572940" xil_pn:in_ck="7979285750144170844" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5666824002871888647" xil_pn:start_ts="1618572940">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="bm_instr_test_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="bm_data_test_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
|
|
|||
|
|
@ -36,19 +36,25 @@
|
|||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
|
||||
</file>
|
||||
<file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
|
||||
</file>
|
||||
<file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
|
||||
</file>
|
||||
<file xil_pn:name="bm_data_test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
|
|
@ -291,8 +297,8 @@
|
|||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/bm_data_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -310,7 +316,7 @@
|
|||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data_test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
|
@ -360,7 +366,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_instr_test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_data_test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
|
|
|||
|
|
@ -57,17 +57,17 @@ begin
|
|||
SUB <= A9 - B9;
|
||||
MUL <= A * B;
|
||||
|
||||
SBIS <= ADD(7 downto 0) when Ctrl_Alu = "01" else
|
||||
SUB(7 downto 0) when Ctrl_Alu = "10" else
|
||||
MUL(7 downto 0) when Ctrl_Alu = "11" else
|
||||
SBIS <= ADD(7 downto 0) when Ctrl_Alu = "001" else
|
||||
SUB(7 downto 0) when Ctrl_Alu = "010" else
|
||||
MUL(7 downto 0) when Ctrl_Alu = "011" else
|
||||
(others => '0');
|
||||
O <= '1' when MUL(15 downto 8) /= "00000000" and Ctrl_Alu = "011" else
|
||||
'0';
|
||||
C <= '1' when ADD(8) = '1' and Ctrl_Alu = "01" else
|
||||
C <= '1' when ADD(8) = '1' and Ctrl_Alu = "001" else
|
||||
'0';
|
||||
N <= '1' when SUB(8) = '1' and Ctrl_Alu = "10" else
|
||||
N <= '1' when SUB(8) = '1' and Ctrl_Alu = "010" else
|
||||
'0';
|
||||
Z <= '1' when SBIS = "00000000" else
|
||||
Z <= '1' when SBIS = "00000000" and Ctrl_Alu /= "000" else
|
||||
'0';
|
||||
S <= SBIS;
|
||||
end Behavioral;
|
||||
|
|
|
|||
|
|
@ -76,5 +76,5 @@
|
|||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 04/15/2021 - 10:56:37</center>
|
||||
<br><center><b>Date Generated:</b> 04/16/2021 - 12:24:04</center>
|
||||
</BODY></HTML>
|
||||
|
|
@ -88,12 +88,38 @@ BEGIN
|
|||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
B<="11111111";
|
||||
A<="11111111";
|
||||
Ctrl_Alu<="001" after 4 ns;
|
||||
Ctrl_Alu<="010" after 8 ns;
|
||||
Ctrl_Alu<="011" after 12 ns;
|
||||
-- 3 op on random numbers
|
||||
wait for 100 ns;
|
||||
A<="00000111";
|
||||
B<="00000011";
|
||||
wait for 100 ns;
|
||||
Ctrl_Alu<="001";
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="010";
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="011";
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="000";
|
||||
wait for 30 ns;
|
||||
A<="11111111";
|
||||
B<="11111111";
|
||||
-- test carry
|
||||
wait for 100 ns;
|
||||
Ctrl_Alu<="001";
|
||||
-- test multiply
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="011";
|
||||
--test null
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="010";
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="000";
|
||||
wait for 30 ns;
|
||||
-- test less than 0
|
||||
A<="00000001";
|
||||
wait for 30 ns;
|
||||
Ctrl_Alu<="010";
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
|
|
|
|||
|
|
@ -46,7 +46,8 @@ begin
|
|||
data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
|
||||
end if;
|
||||
if RST='0' then
|
||||
registres <= (others => "00000000");
|
||||
data_memory <= (others => "00000000");
|
||||
OUT_data <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
|
|
|||
BIN
xilinx/ALU/bm_data_isim_beh.exe
Executable file
BIN
xilinx/ALU/bm_data_isim_beh.exe
Executable file
Binary file not shown.
114
xilinx/ALU/bm_data_test.vhd
Normal file
114
xilinx/ALU/bm_data_test.vhd
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:17:22 04/16/2021
|
||||
-- Design Name:
|
||||
-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd
|
||||
-- Project Name: ALU
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: bm_data
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY bm_data_test IS
|
||||
END bm_data_test;
|
||||
|
||||
ARCHITECTURE behavior OF bm_data_test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT bm_data
|
||||
PORT(
|
||||
IN_addr : IN std_logic_vector(7 downto 0);
|
||||
IN_data : IN std_logic_vector(7 downto 0);
|
||||
RW : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
OUT_data : OUT std_logic_vector(7 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal IN_data : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal RW : std_logic := '0';
|
||||
signal RST : std_logic := '0';
|
||||
signal CLK : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal OUT_data : std_logic_vector(7 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: bm_data PORT MAP (
|
||||
IN_addr => IN_addr,
|
||||
IN_data => IN_data,
|
||||
RW => RW,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
OUT_data => OUT_data
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
wait for CLK_period*10;
|
||||
RST <= '1';
|
||||
IN_addr <= "00000001";
|
||||
IN_data <= "00000001";
|
||||
wait for 30 ns;
|
||||
IN_addr <= "00000010";
|
||||
IN_data <= "00000010";
|
||||
|
||||
RW <= '1';
|
||||
wait for 30 ns;
|
||||
IN_addr <= "00000001";
|
||||
wait for 30 ns;
|
||||
IN_addr <= "00000000";
|
||||
|
||||
wait for 30 ns;
|
||||
RST <= '0';
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
2
xilinx/ALU/bm_data_test_beh.prj
Normal file
2
xilinx/ALU/bm_data_test_beh.prj
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
vhdl work "bm.vhd"
|
||||
vhdl work "bm_data_test.vhd"
|
||||
BIN
xilinx/ALU/bm_data_test_isim_beh.exe
Executable file
BIN
xilinx/ALU/bm_data_test_isim_beh.exe
Executable file
Binary file not shown.
BIN
xilinx/ALU/bm_data_test_isim_beh.wdb
Normal file
BIN
xilinx/ALU/bm_data_test_isim_beh.wdb
Normal file
Binary file not shown.
BIN
xilinx/ALU/bm_data_test_isim_beh1.wdb
Normal file
BIN
xilinx/ALU/bm_data_test_isim_beh1.wdb
Normal file
Binary file not shown.
|
|
@ -1,2 +0,0 @@
|
|||
vhdl work "bm_instr.vhd"
|
||||
vhdl work "bm_instr_test.vhd"
|
||||
Binary file not shown.
|
|
@ -104,22 +104,27 @@ BEGIN
|
|||
wait for CLK_period*10;
|
||||
|
||||
RST <= '1';
|
||||
wait for 100 ns ;
|
||||
--Write only
|
||||
wait for 30 ns ;
|
||||
DATA <= "10000000";
|
||||
wait for 100 ns ;
|
||||
W_addr <= "0000";
|
||||
wait for 100 ns ;
|
||||
W <= '1';
|
||||
wait for 100 ns ;
|
||||
|
||||
wait for 30 ns;
|
||||
W_addr <= "0001";
|
||||
DATA <= "10000100";
|
||||
wait for 30 ns ;
|
||||
-- Read only
|
||||
W <= '0';
|
||||
wait for 100 ns ;
|
||||
|
||||
A_addr <= "0000" ;
|
||||
B_addr <= "0001" ;
|
||||
|
||||
|
||||
|
||||
wait for 30 ns;
|
||||
--Bypass for B and writting and reading at different addr for A
|
||||
DATA <= "10000001";
|
||||
wait for 30 ns;
|
||||
W <= '1';
|
||||
wait for 30 ns;
|
||||
W <= '0';
|
||||
RST <= '0';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,25 +1,25 @@
|
|||
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj work.bm_instr_test
|
||||
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj work.bm_data_test
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
Number of CPUs detected in this system: 6
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 12
|
||||
Number of CPUs detected in this system: 12
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 24
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd" into library work
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
|
||||
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd" into library work
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 98500 KB
|
||||
Fuse CPU Usage: 750 ms
|
||||
Fuse Memory Usage: 98496 KB
|
||||
Fuse CPU Usage: 730 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling package std_logic_arith
|
||||
Compiling package std_logic_unsigned
|
||||
Compiling package numeric_std
|
||||
Compiling architecture behavioral of entity bm_instr [bm_instr_default]
|
||||
Compiling architecture behavior of entity bm_instr_test
|
||||
Compiling architecture behavioral of entity bm_data [bm_data_default]
|
||||
Compiling architecture behavior of entity bm_data_test
|
||||
Time Resolution for simulation is 1ps.
|
||||
Waiting for 1 sub-compilation(s) to finish...
|
||||
Compiled 8 VHDL Units
|
||||
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe
|
||||
Fuse Memory Usage: 936380 KB
|
||||
Fuse CPU Usage: 840 ms
|
||||
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe
|
||||
Fuse Memory Usage: 1722956 KB
|
||||
Fuse CPU Usage: 850 ms
|
||||
GCC CPU Usage: 1640 ms
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj" "work.bm_instr_test"
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_beh.prj" "work.bm_data_test"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2021-04-15T10:56:37</DateModified>
|
||||
<DateModified>2021-04-16T12:24:04</DateModified>
|
||||
<ModuleName>alu</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
ISim log file
|
||||
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb
|
||||
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test_isim_beh.wdb
|
||||
ISim O.87xd (signature 0x8ddf5b5d)
|
||||
WARNING: A WEBPACK license was found.
|
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
||||
|
|
|
|||
Binary file not shown.
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe
Executable file
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/bm_data_test_isim_beh.exe
Executable file
Binary file not shown.
29
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log
Normal file
29
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/isimkernel.log
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
Command line:
|
||||
bm_data_test_isim_beh.exe
|
||||
-simmode gui
|
||||
-simrunnum 0
|
||||
-socket 53487
|
||||
|
||||
Fri Apr 16 13:35:42 2021
|
||||
|
||||
|
||||
Elaboration Time: 0.01 sec
|
||||
|
||||
Current Memory Usage: 183.046 Meg
|
||||
|
||||
Total Signals : 13
|
||||
Total Nets : 2075
|
||||
Total Signal Drivers : 7
|
||||
Total Blocks : 6
|
||||
Total Primitive Blocks : 5
|
||||
Total Processes : 3
|
||||
Total Traceable Variables : 16
|
||||
Total Scalar Nets and Variables : 2577
|
||||
Total Line Count : 27
|
||||
|
||||
Total Simulation Time: 0.1 sec
|
||||
|
||||
Current Memory Usage: 258.548 Meg
|
||||
|
||||
Fri Apr 16 13:37:04 2021
|
||||
|
||||
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat
Normal file
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/netId.dat
Normal file
Binary file not shown.
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1
Normal file
BIN
xilinx/ALU/isim/bm_data_test_isim_beh.exe.sim/tmp_save/_1
Normal file
Binary file not shown.
|
|
@ -0,0 +1,181 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd";
|
||||
extern char *IEEE_P_2592010699;
|
||||
extern char *IEEE_P_1242562249;
|
||||
|
||||
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
|
||||
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
|
||||
|
||||
|
||||
static void work_a_1466808984_3212880686_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
unsigned char t4;
|
||||
char *t5;
|
||||
unsigned char t6;
|
||||
char *t7;
|
||||
int t8;
|
||||
int t9;
|
||||
unsigned int t10;
|
||||
unsigned int t11;
|
||||
unsigned int t12;
|
||||
char *t13;
|
||||
char *t14;
|
||||
char *t15;
|
||||
char *t16;
|
||||
char *t17;
|
||||
char *t18;
|
||||
unsigned char t19;
|
||||
|
||||
LAB0: t1 = (t0 + 3144U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(42, ng0);
|
||||
|
||||
LAB6: t2 = (t0 + 3464);
|
||||
*((int *)t2) = 1;
|
||||
*((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: t5 = (t0 + 3464);
|
||||
*((int *)t5) = 0;
|
||||
xsi_set_current_line(43, ng0);
|
||||
t2 = (t0 + 1352U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t6 = (t4 == (unsigned char)3);
|
||||
if (t6 != 0)
|
||||
goto LAB8;
|
||||
|
||||
LAB10: xsi_set_current_line(46, ng0);
|
||||
t2 = (t0 + 1192U);
|
||||
t3 = *((char **)t2);
|
||||
t2 = (t0 + 1032U);
|
||||
t5 = *((char **)t2);
|
||||
t2 = (t0 + 5968U);
|
||||
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
|
||||
t9 = (t8 - 0);
|
||||
t10 = (t9 * 1);
|
||||
t11 = (8U * t10);
|
||||
t12 = (0U + t11);
|
||||
t7 = (t0 + 3608);
|
||||
t13 = (t7 + 56U);
|
||||
t14 = *((char **)t13);
|
||||
t15 = (t14 + 56U);
|
||||
t16 = *((char **)t15);
|
||||
memcpy(t16, t3, 8U);
|
||||
xsi_driver_first_trans_delta(t7, t12, 8U, 0LL);
|
||||
|
||||
LAB9: xsi_set_current_line(48, ng0);
|
||||
t2 = (t0 + 1512U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t6 = (t4 == (unsigned char)2);
|
||||
if (t6 != 0)
|
||||
goto LAB11;
|
||||
|
||||
LAB13:
|
||||
LAB12: goto LAB2;
|
||||
|
||||
LAB5: t3 = (t0 + 1632U);
|
||||
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
|
||||
if (t4 == 1)
|
||||
goto LAB4;
|
||||
else
|
||||
goto LAB6;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(44, ng0);
|
||||
t2 = (t0 + 1992U);
|
||||
t5 = *((char **)t2);
|
||||
t2 = (t0 + 1032U);
|
||||
t7 = *((char **)t2);
|
||||
t2 = (t0 + 5968U);
|
||||
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
|
||||
t9 = (t8 - 0);
|
||||
t10 = (t9 * 1);
|
||||
xsi_vhdl_check_range_of_index(0, 255, 1, t8);
|
||||
t11 = (8U * t10);
|
||||
t12 = (0 + t11);
|
||||
t13 = (t5 + t12);
|
||||
t14 = (t0 + 3544);
|
||||
t15 = (t14 + 56U);
|
||||
t16 = *((char **)t15);
|
||||
t17 = (t16 + 56U);
|
||||
t18 = *((char **)t17);
|
||||
memcpy(t18, t13, 8U);
|
||||
xsi_driver_first_trans_fast_port(t14);
|
||||
goto LAB9;
|
||||
|
||||
LAB11: xsi_set_current_line(49, ng0);
|
||||
t2 = xsi_get_transient_memory(2048U);
|
||||
memset(t2, 0, 2048U);
|
||||
t5 = t2;
|
||||
t7 = (t0 + 8123);
|
||||
t19 = (8U != 0);
|
||||
if (t19 == 1)
|
||||
goto LAB14;
|
||||
|
||||
LAB15: t14 = (t0 + 3608);
|
||||
t15 = (t14 + 56U);
|
||||
t16 = *((char **)t15);
|
||||
t17 = (t16 + 56U);
|
||||
t18 = *((char **)t17);
|
||||
memcpy(t18, t2, 2048U);
|
||||
xsi_driver_first_trans_fast(t14);
|
||||
xsi_set_current_line(50, ng0);
|
||||
t2 = xsi_get_transient_memory(8U);
|
||||
memset(t2, 0, 8U);
|
||||
t3 = t2;
|
||||
memset(t3, (unsigned char)2, 8U);
|
||||
t5 = (t0 + 3544);
|
||||
t7 = (t5 + 56U);
|
||||
t13 = *((char **)t7);
|
||||
t14 = (t13 + 56U);
|
||||
t15 = *((char **)t14);
|
||||
memcpy(t15, t2, 8U);
|
||||
xsi_driver_first_trans_fast_port(t5);
|
||||
goto LAB12;
|
||||
|
||||
LAB14: t10 = (2048U / 8U);
|
||||
xsi_mem_set_data(t5, t7, 8U, t10);
|
||||
goto LAB15;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_1466808984_3212880686_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_1466808984_3212880686_p_0};
|
||||
xsi_register_didat("work_a_1466808984_3212880686", "isim/bm_data_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,288 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_data_test.vhd";
|
||||
|
||||
|
||||
|
||||
static void work_a_2533693612_2372691052_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
char *t4;
|
||||
char *t5;
|
||||
char *t6;
|
||||
int64 t7;
|
||||
int64 t8;
|
||||
|
||||
LAB0: t1 = (t0 + 3104U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(82, ng0);
|
||||
t2 = (t0 + 3736);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(83, ng0);
|
||||
t2 = (t0 + 2128U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2912);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(84, ng0);
|
||||
t2 = (t0 + 3736);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(85, ng0);
|
||||
t2 = (t0 + 2128U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2912);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: goto LAB2;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_2533693612_2372691052_p_1(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
int64 t3;
|
||||
char *t4;
|
||||
int64 t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
char *t9;
|
||||
char *t10;
|
||||
|
||||
LAB0: t1 = (t0 + 3352U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(93, ng0);
|
||||
t3 = (100 * 1000LL);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(94, ng0);
|
||||
t2 = (t0 + 2128U);
|
||||
t4 = *((char **)t2);
|
||||
t3 = *((int64 *)t4);
|
||||
t5 = (t3 * 10);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t5);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(95, ng0);
|
||||
t2 = (t0 + 3800);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(96, ng0);
|
||||
t2 = (t0 + 6536);
|
||||
t6 = (t0 + 3864);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(97, ng0);
|
||||
t2 = (t0 + 6544);
|
||||
t6 = (t0 + 3928);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(98, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB14: *((char **)t1) = &&LAB15;
|
||||
goto LAB1;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
LAB12: xsi_set_current_line(99, ng0);
|
||||
t2 = (t0 + 6552);
|
||||
t6 = (t0 + 3864);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(100, ng0);
|
||||
t2 = (t0 + 6560);
|
||||
t6 = (t0 + 3928);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(102, ng0);
|
||||
t2 = (t0 + 3992);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(103, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB18: *((char **)t1) = &&LAB19;
|
||||
goto LAB1;
|
||||
|
||||
LAB13: goto LAB12;
|
||||
|
||||
LAB15: goto LAB13;
|
||||
|
||||
LAB16: xsi_set_current_line(104, ng0);
|
||||
t2 = (t0 + 6568);
|
||||
t6 = (t0 + 3864);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(105, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB22: *((char **)t1) = &&LAB23;
|
||||
goto LAB1;
|
||||
|
||||
LAB17: goto LAB16;
|
||||
|
||||
LAB19: goto LAB17;
|
||||
|
||||
LAB20: xsi_set_current_line(106, ng0);
|
||||
t2 = (t0 + 6576);
|
||||
t6 = (t0 + 3864);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(108, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3160);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB26: *((char **)t1) = &&LAB27;
|
||||
goto LAB1;
|
||||
|
||||
LAB21: goto LAB20;
|
||||
|
||||
LAB23: goto LAB21;
|
||||
|
||||
LAB24: xsi_set_current_line(109, ng0);
|
||||
t2 = (t0 + 3800);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(111, ng0);
|
||||
|
||||
LAB30: *((char **)t1) = &&LAB31;
|
||||
goto LAB1;
|
||||
|
||||
LAB25: goto LAB24;
|
||||
|
||||
LAB27: goto LAB25;
|
||||
|
||||
LAB28: goto LAB2;
|
||||
|
||||
LAB29: goto LAB28;
|
||||
|
||||
LAB31: goto LAB29;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_2533693612_2372691052_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_2533693612_2372691052_p_0,(void *)work_a_2533693612_2372691052_p_1};
|
||||
xsi_register_didat("work_a_2533693612_2372691052", "isim/bm_data_test_isim_beh.exe.sim/work/a_2533693612_2372691052.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -31,11 +31,11 @@ int main(int argc, char **argv)
|
|||
ieee_p_3499444699_init();
|
||||
ieee_p_3620187407_init();
|
||||
ieee_p_1242562249_init();
|
||||
work_a_1802466774_3212880686_init();
|
||||
work_a_4060154216_2372691052_init();
|
||||
work_a_1466808984_3212880686_init();
|
||||
work_a_2533693612_2372691052_init();
|
||||
|
||||
|
||||
xsi_register_tops("work_a_4060154216_2372691052");
|
||||
xsi_register_tops("work_a_2533693612_2372691052");
|
||||
|
||||
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
|
||||
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,29 +0,0 @@
|
|||
Command line:
|
||||
bm_instr_test_isim_beh.exe
|
||||
-simmode gui
|
||||
-simrunnum 0
|
||||
-socket 58139
|
||||
|
||||
Thu Apr 15 10:54:21 2021
|
||||
|
||||
|
||||
Elaboration Time: 0 sec
|
||||
|
||||
Current Memory Usage: 182.768 Meg
|
||||
|
||||
Total Signals : 7
|
||||
Total Nets : 2065
|
||||
Total Signal Drivers : 3
|
||||
Total Blocks : 6
|
||||
Total Primitive Blocks : 5
|
||||
Total Processes : 3
|
||||
Total Traceable Variables : 16
|
||||
Total Scalar Nets and Variables : 2567
|
||||
Total Line Count : 12
|
||||
|
||||
Total Simulation Time: 0.02 sec
|
||||
|
||||
Current Memory Usage: 258.269 Meg
|
||||
|
||||
Thu Apr 15 10:54:49 2021
|
||||
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,106 +0,0 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd";
|
||||
extern char *IEEE_P_2592010699;
|
||||
extern char *IEEE_P_1242562249;
|
||||
|
||||
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
|
||||
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
|
||||
|
||||
|
||||
static void work_a_1802466774_3212880686_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
unsigned char t4;
|
||||
char *t5;
|
||||
int t6;
|
||||
int t7;
|
||||
unsigned int t8;
|
||||
unsigned int t9;
|
||||
unsigned int t10;
|
||||
char *t11;
|
||||
char *t12;
|
||||
char *t13;
|
||||
char *t14;
|
||||
char *t15;
|
||||
char *t16;
|
||||
|
||||
LAB0: t1 = (t0 + 2664U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(40, ng0);
|
||||
|
||||
LAB6: t2 = (t0 + 2984);
|
||||
*((int *)t2) = 1;
|
||||
*((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: t5 = (t0 + 2984);
|
||||
*((int *)t5) = 0;
|
||||
xsi_set_current_line(41, ng0);
|
||||
t2 = (t0 + 1512U);
|
||||
t3 = *((char **)t2);
|
||||
t2 = (t0 + 1032U);
|
||||
t5 = *((char **)t2);
|
||||
t2 = (t0 + 5232U);
|
||||
t6 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
|
||||
t7 = (t6 - 0);
|
||||
t8 = (t7 * 1);
|
||||
xsi_vhdl_check_range_of_index(0, 255, 1, t6);
|
||||
t9 = (8U * t8);
|
||||
t10 = (0 + t9);
|
||||
t11 = (t3 + t10);
|
||||
t12 = (t0 + 3064);
|
||||
t13 = (t12 + 56U);
|
||||
t14 = *((char **)t13);
|
||||
t15 = (t14 + 56U);
|
||||
t16 = *((char **)t15);
|
||||
memcpy(t16, t11, 8U);
|
||||
xsi_driver_first_trans_fast_port(t12);
|
||||
goto LAB2;
|
||||
|
||||
LAB5: t3 = (t0 + 1312U);
|
||||
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
|
||||
if (t4 == 1)
|
||||
goto LAB4;
|
||||
else
|
||||
goto LAB6;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_1802466774_3212880686_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
|
||||
xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,192 +0,0 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
|
||||
|
||||
|
||||
|
||||
static void work_a_4060154216_2372691052_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
char *t4;
|
||||
char *t5;
|
||||
char *t6;
|
||||
int64 t7;
|
||||
int64 t8;
|
||||
|
||||
LAB0: t1 = (t0 + 2624U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(73, ng0);
|
||||
t2 = (t0 + 3256);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(74, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2432);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(75, ng0);
|
||||
t2 = (t0 + 3256);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(76, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2432);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: goto LAB2;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_4060154216_2372691052_p_1(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
int64 t3;
|
||||
char *t4;
|
||||
int64 t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
char *t9;
|
||||
char *t10;
|
||||
|
||||
LAB0: t1 = (t0 + 2872U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(84, ng0);
|
||||
t3 = (100 * 1000LL);
|
||||
t2 = (t0 + 2680);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(86, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t4 = *((char **)t2);
|
||||
t3 = *((int64 *)t4);
|
||||
t5 = (t3 * 10);
|
||||
t2 = (t0 + 2680);
|
||||
xsi_process_wait(t2, t5);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(88, ng0);
|
||||
t2 = (t0 + 5544);
|
||||
t6 = (t0 + 3320);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(89, ng0);
|
||||
t3 = (100 * 1000LL);
|
||||
t2 = (t0 + 2680);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB14: *((char **)t1) = &&LAB15;
|
||||
goto LAB1;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
LAB12: xsi_set_current_line(91, ng0);
|
||||
t2 = (t0 + 5552);
|
||||
t6 = (t0 + 3320);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(94, ng0);
|
||||
|
||||
LAB18: *((char **)t1) = &&LAB19;
|
||||
goto LAB1;
|
||||
|
||||
LAB13: goto LAB12;
|
||||
|
||||
LAB15: goto LAB13;
|
||||
|
||||
LAB16: goto LAB2;
|
||||
|
||||
LAB17: goto LAB16;
|
||||
|
||||
LAB19: goto LAB17;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_4060154216_2372691052_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
|
||||
xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe
Executable file
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/br_test_isim_beh.exe
Executable file
Binary file not shown.
29
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log
Normal file
29
xilinx/ALU/isim/br_test_isim_beh.exe.sim/isimkernel.log
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
Command line:
|
||||
br_test_isim_beh.exe
|
||||
-simmode gui
|
||||
-simrunnum 0
|
||||
-socket 44223
|
||||
|
||||
Fri Apr 16 13:26:05 2021
|
||||
|
||||
|
||||
Elaboration Time: 0 sec
|
||||
|
||||
Current Memory Usage: 181.682 Meg
|
||||
|
||||
Total Signals : 19
|
||||
Total Nets : 167
|
||||
Total Signal Drivers : 10
|
||||
Total Blocks : 6
|
||||
Total Primitive Blocks : 5
|
||||
Total Processes : 5
|
||||
Total Traceable Variables : 16
|
||||
Total Scalar Nets and Variables : 669
|
||||
Total Line Count : 33
|
||||
|
||||
Total Simulation Time: 0.01 sec
|
||||
|
||||
Current Memory Usage: 257.184 Meg
|
||||
|
||||
Fri Apr 16 13:26:10 2021
|
||||
|
||||
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat
Normal file
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/netId.dat
Normal file
Binary file not shown.
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1
Normal file
BIN
xilinx/ALU/isim/br_test_isim_beh.exe.sim/tmp_save/_1
Normal file
Binary file not shown.
|
|
@ -0,0 +1,345 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd";
|
||||
|
||||
|
||||
|
||||
static void work_a_3692836482_2372691052_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
char *t4;
|
||||
char *t5;
|
||||
char *t6;
|
||||
int64 t7;
|
||||
int64 t8;
|
||||
|
||||
LAB0: t1 = (t0 + 3584U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(91, ng0);
|
||||
t2 = (t0 + 4216);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(92, ng0);
|
||||
t2 = (t0 + 2608U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 3392);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(93, ng0);
|
||||
t2 = (t0 + 4216);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(94, ng0);
|
||||
t2 = (t0 + 2608U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 3392);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: goto LAB2;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_3692836482_2372691052_p_1(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
int64 t3;
|
||||
char *t4;
|
||||
int64 t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
char *t9;
|
||||
char *t10;
|
||||
|
||||
LAB0: t1 = (t0 + 3832U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(102, ng0);
|
||||
t3 = (100 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(104, ng0);
|
||||
t2 = (t0 + 2608U);
|
||||
t4 = *((char **)t2);
|
||||
t3 = *((int64 *)t4);
|
||||
t5 = (t3 * 10);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t5);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(106, ng0);
|
||||
t2 = (t0 + 4280);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(108, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB14: *((char **)t1) = &&LAB15;
|
||||
goto LAB1;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
LAB12: xsi_set_current_line(109, ng0);
|
||||
t2 = (t0 + 7400);
|
||||
t6 = (t0 + 4344);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(110, ng0);
|
||||
t2 = (t0 + 7408);
|
||||
t6 = (t0 + 4408);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 4U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(111, ng0);
|
||||
t2 = (t0 + 4472);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(112, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB18: *((char **)t1) = &&LAB19;
|
||||
goto LAB1;
|
||||
|
||||
LAB13: goto LAB12;
|
||||
|
||||
LAB15: goto LAB13;
|
||||
|
||||
LAB16: xsi_set_current_line(113, ng0);
|
||||
t2 = (t0 + 7412);
|
||||
t6 = (t0 + 4408);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 4U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(114, ng0);
|
||||
t2 = (t0 + 7416);
|
||||
t6 = (t0 + 4344);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(115, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB22: *((char **)t1) = &&LAB23;
|
||||
goto LAB1;
|
||||
|
||||
LAB17: goto LAB16;
|
||||
|
||||
LAB19: goto LAB17;
|
||||
|
||||
LAB20: xsi_set_current_line(117, ng0);
|
||||
t2 = (t0 + 4472);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(118, ng0);
|
||||
t2 = (t0 + 7424);
|
||||
t6 = (t0 + 4536);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 4U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(119, ng0);
|
||||
t2 = (t0 + 7428);
|
||||
t6 = (t0 + 4600);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 4U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(120, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB26: *((char **)t1) = &&LAB27;
|
||||
goto LAB1;
|
||||
|
||||
LAB21: goto LAB20;
|
||||
|
||||
LAB23: goto LAB21;
|
||||
|
||||
LAB24: xsi_set_current_line(122, ng0);
|
||||
t2 = (t0 + 7432);
|
||||
t6 = (t0 + 4344);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
t9 = (t8 + 56U);
|
||||
t10 = *((char **)t9);
|
||||
memcpy(t10, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t6);
|
||||
xsi_set_current_line(123, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB30: *((char **)t1) = &&LAB31;
|
||||
goto LAB1;
|
||||
|
||||
LAB25: goto LAB24;
|
||||
|
||||
LAB27: goto LAB25;
|
||||
|
||||
LAB28: xsi_set_current_line(124, ng0);
|
||||
t2 = (t0 + 4472);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(125, ng0);
|
||||
t3 = (30 * 1000LL);
|
||||
t2 = (t0 + 3640);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB34: *((char **)t1) = &&LAB35;
|
||||
goto LAB1;
|
||||
|
||||
LAB29: goto LAB28;
|
||||
|
||||
LAB31: goto LAB29;
|
||||
|
||||
LAB32: xsi_set_current_line(126, ng0);
|
||||
t2 = (t0 + 4472);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(127, ng0);
|
||||
t2 = (t0 + 4280);
|
||||
t4 = (t2 + 56U);
|
||||
t6 = *((char **)t4);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
*((unsigned char *)t8) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(128, ng0);
|
||||
|
||||
LAB38: *((char **)t1) = &&LAB39;
|
||||
goto LAB1;
|
||||
|
||||
LAB33: goto LAB32;
|
||||
|
||||
LAB35: goto LAB33;
|
||||
|
||||
LAB36: goto LAB2;
|
||||
|
||||
LAB37: goto LAB36;
|
||||
|
||||
LAB39: goto LAB37;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_3692836482_2372691052_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_3692836482_2372691052_p_0,(void *)work_a_3692836482_2372691052_p_1};
|
||||
xsi_register_didat("work_a_3692836482_2372691052", "isim/br_test_isim_beh.exe.sim/work/a_3692836482_2372691052.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,343 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0x8ddf5b5d */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd";
|
||||
extern char *IEEE_P_2592010699;
|
||||
extern char *IEEE_P_1242562249;
|
||||
extern char *IEEE_P_3620187407;
|
||||
|
||||
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
|
||||
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
|
||||
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
|
||||
|
||||
|
||||
static void work_a_3998322972_3212880686_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
unsigned char t4;
|
||||
char *t5;
|
||||
unsigned char t6;
|
||||
char *t7;
|
||||
int t8;
|
||||
int t9;
|
||||
unsigned int t10;
|
||||
unsigned int t11;
|
||||
unsigned int t12;
|
||||
char *t13;
|
||||
char *t14;
|
||||
char *t15;
|
||||
char *t16;
|
||||
char *t17;
|
||||
unsigned char t18;
|
||||
char *t19;
|
||||
|
||||
LAB0: t1 = (t0 + 3624U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(47, ng0);
|
||||
|
||||
LAB6: t2 = (t0 + 4440);
|
||||
*((int *)t2) = 1;
|
||||
*((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: t5 = (t0 + 4440);
|
||||
*((int *)t5) = 0;
|
||||
xsi_set_current_line(48, ng0);
|
||||
t2 = (t0 + 1512U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t6 = (t4 == (unsigned char)3);
|
||||
if (t6 != 0)
|
||||
goto LAB8;
|
||||
|
||||
LAB10:
|
||||
LAB9: xsi_set_current_line(51, ng0);
|
||||
t2 = (t0 + 1832U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t6 = (t4 == (unsigned char)2);
|
||||
if (t6 != 0)
|
||||
goto LAB11;
|
||||
|
||||
LAB13:
|
||||
LAB12: goto LAB2;
|
||||
|
||||
LAB5: t3 = (t0 + 1952U);
|
||||
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
|
||||
if (t4 == 1)
|
||||
goto LAB4;
|
||||
else
|
||||
goto LAB6;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(49, ng0);
|
||||
t2 = (t0 + 1672U);
|
||||
t5 = *((char **)t2);
|
||||
t2 = (t0 + 1352U);
|
||||
t7 = *((char **)t2);
|
||||
t2 = (t0 + 7424U);
|
||||
t8 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t7, t2);
|
||||
t9 = (t8 - 0);
|
||||
t10 = (t9 * 1);
|
||||
t11 = (8U * t10);
|
||||
t12 = (0U + t11);
|
||||
t13 = (t0 + 4552);
|
||||
t14 = (t13 + 56U);
|
||||
t15 = *((char **)t14);
|
||||
t16 = (t15 + 56U);
|
||||
t17 = *((char **)t16);
|
||||
memcpy(t17, t5, 8U);
|
||||
xsi_driver_first_trans_delta(t13, t12, 8U, 0LL);
|
||||
goto LAB9;
|
||||
|
||||
LAB11: xsi_set_current_line(52, ng0);
|
||||
t2 = xsi_get_transient_memory(128U);
|
||||
memset(t2, 0, 128U);
|
||||
t5 = t2;
|
||||
t7 = (t0 + 7679);
|
||||
t18 = (8U != 0);
|
||||
if (t18 == 1)
|
||||
goto LAB14;
|
||||
|
||||
LAB15: t14 = (t0 + 4552);
|
||||
t15 = (t14 + 56U);
|
||||
t16 = *((char **)t15);
|
||||
t17 = (t16 + 56U);
|
||||
t19 = *((char **)t17);
|
||||
memcpy(t19, t2, 128U);
|
||||
xsi_driver_first_trans_fast(t14);
|
||||
goto LAB12;
|
||||
|
||||
LAB14: t10 = (128U / 8U);
|
||||
xsi_mem_set_data(t5, t7, 8U, t10);
|
||||
goto LAB15;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_3998322972_3212880686_p_1(char *t0)
|
||||
{
|
||||
unsigned char t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
unsigned char t4;
|
||||
unsigned char t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
unsigned char t9;
|
||||
char *t10;
|
||||
char *t11;
|
||||
char *t12;
|
||||
int t13;
|
||||
int t14;
|
||||
unsigned int t15;
|
||||
unsigned int t16;
|
||||
unsigned int t17;
|
||||
char *t18;
|
||||
char *t19;
|
||||
char *t20;
|
||||
char *t21;
|
||||
char *t22;
|
||||
char *t23;
|
||||
char *t24;
|
||||
char *t25;
|
||||
char *t26;
|
||||
char *t27;
|
||||
char *t28;
|
||||
char *t29;
|
||||
char *t30;
|
||||
|
||||
LAB0: xsi_set_current_line(55, ng0);
|
||||
t2 = (t0 + 1512U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t5 = (t4 == (unsigned char)2);
|
||||
if (t5 == 1)
|
||||
goto LAB5;
|
||||
|
||||
LAB6: t2 = (t0 + 1032U);
|
||||
t6 = *((char **)t2);
|
||||
t2 = (t0 + 7392U);
|
||||
t7 = (t0 + 1352U);
|
||||
t8 = *((char **)t7);
|
||||
t7 = (t0 + 7424U);
|
||||
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
|
||||
t1 = t9;
|
||||
|
||||
LAB7: if (t1 != 0)
|
||||
goto LAB3;
|
||||
|
||||
LAB4:
|
||||
LAB8: t24 = (t0 + 1672U);
|
||||
t25 = *((char **)t24);
|
||||
t24 = (t0 + 4616);
|
||||
t26 = (t24 + 56U);
|
||||
t27 = *((char **)t26);
|
||||
t28 = (t27 + 56U);
|
||||
t29 = *((char **)t28);
|
||||
memcpy(t29, t25, 8U);
|
||||
xsi_driver_first_trans_fast_port(t24);
|
||||
|
||||
LAB2: t30 = (t0 + 4456);
|
||||
*((int *)t30) = 1;
|
||||
|
||||
LAB1: return;
|
||||
LAB3: t10 = (t0 + 2472U);
|
||||
t11 = *((char **)t10);
|
||||
t10 = (t0 + 1032U);
|
||||
t12 = *((char **)t10);
|
||||
t10 = (t0 + 7392U);
|
||||
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
|
||||
t14 = (t13 - 0);
|
||||
t15 = (t14 * 1);
|
||||
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
|
||||
t16 = (8U * t15);
|
||||
t17 = (0 + t16);
|
||||
t18 = (t11 + t17);
|
||||
t19 = (t0 + 4616);
|
||||
t20 = (t19 + 56U);
|
||||
t21 = *((char **)t20);
|
||||
t22 = (t21 + 56U);
|
||||
t23 = *((char **)t22);
|
||||
memcpy(t23, t18, 8U);
|
||||
xsi_driver_first_trans_fast_port(t19);
|
||||
goto LAB2;
|
||||
|
||||
LAB5: t1 = (unsigned char)1;
|
||||
goto LAB7;
|
||||
|
||||
LAB9: goto LAB2;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_3998322972_3212880686_p_2(char *t0)
|
||||
{
|
||||
unsigned char t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
unsigned char t4;
|
||||
unsigned char t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
unsigned char t9;
|
||||
char *t10;
|
||||
char *t11;
|
||||
char *t12;
|
||||
int t13;
|
||||
int t14;
|
||||
unsigned int t15;
|
||||
unsigned int t16;
|
||||
unsigned int t17;
|
||||
char *t18;
|
||||
char *t19;
|
||||
char *t20;
|
||||
char *t21;
|
||||
char *t22;
|
||||
char *t23;
|
||||
char *t24;
|
||||
char *t25;
|
||||
char *t26;
|
||||
char *t27;
|
||||
char *t28;
|
||||
char *t29;
|
||||
char *t30;
|
||||
|
||||
LAB0: xsi_set_current_line(57, ng0);
|
||||
t2 = (t0 + 1512U);
|
||||
t3 = *((char **)t2);
|
||||
t4 = *((unsigned char *)t3);
|
||||
t5 = (t4 == (unsigned char)2);
|
||||
if (t5 == 1)
|
||||
goto LAB5;
|
||||
|
||||
LAB6: t2 = (t0 + 1192U);
|
||||
t6 = *((char **)t2);
|
||||
t2 = (t0 + 7408U);
|
||||
t7 = (t0 + 1352U);
|
||||
t8 = *((char **)t7);
|
||||
t7 = (t0 + 7424U);
|
||||
t9 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t6, t2, t8, t7);
|
||||
t1 = t9;
|
||||
|
||||
LAB7: if (t1 != 0)
|
||||
goto LAB3;
|
||||
|
||||
LAB4:
|
||||
LAB8: t24 = (t0 + 1672U);
|
||||
t25 = *((char **)t24);
|
||||
t24 = (t0 + 4680);
|
||||
t26 = (t24 + 56U);
|
||||
t27 = *((char **)t26);
|
||||
t28 = (t27 + 56U);
|
||||
t29 = *((char **)t28);
|
||||
memcpy(t29, t25, 8U);
|
||||
xsi_driver_first_trans_fast_port(t24);
|
||||
|
||||
LAB2: t30 = (t0 + 4472);
|
||||
*((int *)t30) = 1;
|
||||
|
||||
LAB1: return;
|
||||
LAB3: t10 = (t0 + 2472U);
|
||||
t11 = *((char **)t10);
|
||||
t10 = (t0 + 1192U);
|
||||
t12 = *((char **)t10);
|
||||
t10 = (t0 + 7408U);
|
||||
t13 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t12, t10);
|
||||
t14 = (t13 - 0);
|
||||
t15 = (t14 * 1);
|
||||
xsi_vhdl_check_range_of_index(0, 15, 1, t13);
|
||||
t16 = (8U * t15);
|
||||
t17 = (0 + t16);
|
||||
t18 = (t11 + t17);
|
||||
t19 = (t0 + 4680);
|
||||
t20 = (t19 + 56U);
|
||||
t21 = *((char **)t20);
|
||||
t22 = (t21 + 56U);
|
||||
t23 = *((char **)t22);
|
||||
memcpy(t23, t18, 8U);
|
||||
xsi_driver_first_trans_fast_port(t19);
|
||||
goto LAB2;
|
||||
|
||||
LAB5: t1 = (unsigned char)1;
|
||||
goto LAB7;
|
||||
|
||||
LAB9: goto LAB2;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_3998322972_3212880686_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_3998322972_3212880686_p_0,(void *)work_a_3998322972_3212880686_p_1,(void *)work_a_3998322972_3212880686_p_2};
|
||||
xsi_register_didat("work_a_3998322972_3212880686", "isim/br_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,49 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
#include "xsi.h"
|
||||
|
||||
struct XSI_INFO xsi_info;
|
||||
|
||||
char *IEEE_P_2592010699;
|
||||
char *STD_STANDARD;
|
||||
char *IEEE_P_3620187407;
|
||||
char *IEEE_P_3499444699;
|
||||
char *IEEE_P_1242562249;
|
||||
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
xsi_init_design(argc, argv);
|
||||
xsi_register_info(&xsi_info);
|
||||
|
||||
xsi_register_min_prec_unit(-12);
|
||||
ieee_p_2592010699_init();
|
||||
ieee_p_3499444699_init();
|
||||
ieee_p_3620187407_init();
|
||||
ieee_p_1242562249_init();
|
||||
work_a_3998322972_3212880686_init();
|
||||
work_a_3692836482_2372691052_init();
|
||||
|
||||
|
||||
xsi_register_tops("work_a_3692836482_2372691052");
|
||||
|
||||
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
|
||||
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
|
||||
STD_STANDARD = xsi_get_engine_memory("std_standard");
|
||||
IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
|
||||
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
|
||||
IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
|
||||
|
||||
return xsi_run_simulation(argc, argv);
|
||||
|
||||
}
|
||||
Binary file not shown.
|
|
@ -2,14 +2,14 @@
|
|||
<xtag-section name="ISimStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>840 ms, 936380 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1722956 KB</xtag-isim-property-value></TD></TR>
|
||||
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>2065</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>13</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>2075</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.02 sec, 257216 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 257495 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
xilinx/ALU/isim/work/bm_data.vdb
Normal file
BIN
xilinx/ALU/isim/work/bm_data.vdb
Normal file
Binary file not shown.
BIN
xilinx/ALU/isim/work/bm_data_test.vdb
Normal file
BIN
xilinx/ALU/isim/work/bm_data_test.vdb
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +1 @@
|
|||
work "bm_instr.vhd"
|
||||
work "bm.vhd"
|
||||
|
|
|
|||
55
xilinx/ALU/pipeline.vhd
Normal file
55
xilinx/ALU/pipeline.vhd
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:45:17 04/16/2021
|
||||
-- Design Name:
|
||||
-- Module Name: pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity pipeline is
|
||||
Port ( OP_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
A_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
B_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
C_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
C_OUT : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end pipeline;
|
||||
|
||||
architecture Behavioral of pipeline is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
OP_OUT <= OP_IN;
|
||||
A_OUT <= A_IN;
|
||||
B_OUT <= B_IN;
|
||||
C_OUT <= C_IN;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
||||
Loading…
Reference in a new issue