93 lines
2 KiB
VHDL
93 lines
2 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09:37:50 05/10/2021
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-- Design Name:
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-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd
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-- Project Name: ALU
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: processeur
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY process_test IS
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END process_test;
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ARCHITECTURE behavior OF process_test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT processeur
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PORT(
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CLK : IN std_logic;
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RST : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RST : std_logic := '0';
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: processeur PORT MAP (
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CLK => CLK,
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RST => RST
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for CLK_period*10;
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-- insert stimulus here
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-- AFC test
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RST<='1';
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wait;
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end process;
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END;
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