60 lines
1.5 KiB
VHDL
60 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:29:59 04/13/2021
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-- Design Name:
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-- Module Name: br - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--use UNISIM.VComponents.all;
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entity br is
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Port ( A_addr : in STD_LOGIC_VECTOR (3 downto 0);
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B_addr : in STD_LOGIC_VECTOR (3 downto 0);
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W_addr : in STD_LOGIC_VECTOR (3 downto 0);
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W : in STD_LOGIC;
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Data : in STD_LOGIC_VECTOR (7 downto 0);
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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QA : out STD_LOGIC_VECTOR (7 downto 0);
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QB : out STD_LOGIC_VECTOR (7 downto 0));
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end br;
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architecture Behavioral of br is
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type reg is array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
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signal registres: reg;
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begin
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process
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begin
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wait until rising_edge(CLK);
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if W = '1' then
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registres(to_integer(unsigned(W_addr))) <= Data;
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end if;
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if RST='0' then
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registres <= (others => "00000000");
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end if;
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end process;
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QA <= registres(to_integer(unsigned(A_addr))) when W ='0' or A_addr /= W_addr
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else Data;
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QB <= registres(to_integer(unsigned(B_addr))) when W ='0' or B_addr /= W_addr
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else Data;
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end Behavioral;
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