56 lines
1.3 KiB
VHDL
56 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:32:11 04/15/2021
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-- Design Name:
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-- Module Name: bm_data - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity bm_data is
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Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
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IN_data : in STD_LOGIC_VECTOR (7 downto 0);
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RW : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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OUT_data : out STD_LOGIC_VECTOR (7 downto 0));
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end bm_data;
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architecture Behavioral of bm_data is
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type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
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signal data_memory: mem;
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begin
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process
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begin
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wait until rising_edge(CLK);
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if RW = '1' then
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OUT_data <= data_memory(to_integer(unsigned(IN_addr)));
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else
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data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
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end if;
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if RST='0' then
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data_memory <= (others => "00000000");
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OUT_data <= (others => '0');
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end if;
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end process;
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end Behavioral;
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