50 lines
1.3 KiB
VHDL
50 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:28:01 04/13/2021
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-- Design Name:
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-- Module Name: BR - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity BR is
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Port ( A_addr : in STD_LOGIC_VECTOR (3 downto 0);
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B_addr : in STD_LOGIC_VECTOR (3 downto 0);
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W_addr : in STD_LOGIC_VECTOR (3 downto 0);
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W : in STD_LOGIC;
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Data : in STD_LOGIC_VECTOR (7 downto 0);
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RST : in STD_LOGIC;
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CLK : in STD_LOGIC;
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QA : out STD_LOGIC_VECTOR (7 downto 0);
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QB : out STD_LOGIC_VECTOR (7 downto 0));
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end BR;
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architecture Behavioral of BR is
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begin
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end Behavioral;
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