50 lines
1.5 KiB
VHDL
50 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:40:07 04/15/2021
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-- Design Name:
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-- Module Name: bm_instr - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity bm_instr is
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Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
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OUT_data : out STD_LOGIC_VECTOR (31 downto 0);
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CLK : in STD_LOGIC);
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end bm_instr;
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architecture Behavioral of bm_instr is
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type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
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-- instruction "00000110 00000001 00000110 00000000"
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--test afc
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--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
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--test afc cop
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signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
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--test add
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--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
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begin
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OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));
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end Behavioral;
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