46 lines
1,021 B
VHDL
46 lines
1,021 B
VHDL
-- TestBench Template
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY testbench IS
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END testbench;
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ARCHITECTURE behavior OF testbench IS
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-- Component Declaration
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COMPONENT <component name>
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PORT(
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<port1> : IN std_logic;
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<port2> : IN std_logic_vector(3 downto 0);
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<port3> : OUT std_logic_vector(3 downto 0)
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);
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END COMPONENT;
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SIGNAL <signal1> : std_logic;
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SIGNAL <signal2> : std_logic_vector(3 downto 0);
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BEGIN
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-- Component Instantiation
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uut: <component name> PORT MAP(
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<port1> => <signal1>,
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<port3> => <signal2>
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);
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-- Test Bench Statements
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tb : PROCESS
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BEGIN
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wait for 100 ns; -- wait until global set/reset completes
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-- Add user defined stimulus here
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wait; -- will wait forever
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END PROCESS tb;
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-- End Test Bench
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END;
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