303 lines
13 KiB
Text
303 lines
13 KiB
Text
Release 13.4 - xst O.87xd (lin64)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.03 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.03 secs
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-->
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Reading design: processeur.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "processeur.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "processeur"
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Output Format : NGC
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Target Device : xc6slx16-3-csg324
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---- Source Options
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Top Module Name : processeur
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
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Parsing entity <pipeline>.
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Parsing architecture <Behavioral> of entity <pipeline>.
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
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Parsing entity <br>.
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Parsing architecture <Behavioral> of entity <br>.
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
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Parsing entity <bm_instr>.
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Parsing architecture <Behavioral> of entity <bm_instr>.
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
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Parsing entity <bm_data>.
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Parsing architecture <Behavioral> of entity <bm_data>.
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
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Parsing entity <alu>.
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Parsing architecture <Behavioral> of entity <alu>.
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Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
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Parsing entity <processeur>.
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Parsing architecture <Behavioral> of entity <processeur>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity <processeur> (architecture <Behavioral>) from library <work>.
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Elaborating entity <bm_instr> (architecture <Behavioral>) from library <work>.
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Elaborating entity <pipeline> (architecture <Behavioral>) from library <work>.
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Elaborating entity <br> (architecture <Behavioral>) from library <work>.
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Elaborating entity <alu> (architecture <Behavioral>) from library <work>.
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Elaborating entity <bm_data> (architecture <Behavioral>) from library <work>.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance <addr_instructions> of block <bm_instr> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance <LI_LD> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance <banc_registres> of block <br> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance <DI_EX> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance <UAL> of block <alu> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance <EX_Mem> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance <data_memory> of block <bm_data> are unconnected in block <processeur>. Underlying logic will be removed.
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WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance <Mem_RE> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <processeur>.
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Related source file is "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd".
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <N> of the instance <UAL> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <O> of the instance <UAL> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <Z> of the instance <UAL> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <C> of the instance <UAL> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port <C_OUT> of the instance <EX_Mem> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port <C_OUT> of the instance <Mem_RE> is unconnected or connected to loadless signal.
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Summary:
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no macro.
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Unit <processeur> synthesized.
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=========================================================================
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HDL Synthesis Report
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Found no macro
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Found no macro
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <processeur> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block processeur, actual ratio is 0.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Design Summary *
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=========================================================================
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Top Level Output File Name : processeur.ngc
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Primitive and Black Box Usage:
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------------------------------
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Device utilization summary:
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---------------------------
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Selected Device : 6slx16csg324-3
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Slice Logic Utilization:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 0
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Number with an unused Flip Flop: 0 out of 0
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Number with an unused LUT: 0 out of 0
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Number of fully used LUT-FF pairs: 0 out of 0
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Number of unique control sets: 0
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IO Utilization:
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Number of IOs: 2
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Number of bonded IOBs: 0 out of 232 0%
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Specific Feature Utilization:
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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Timing Report
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -3
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: No path found
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Timing Details:
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---------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Cross Clock Domains Report:
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--------------------------
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=========================================================================
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Total REAL time to Xst completion: 4.00 secs
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Total CPU time to Xst completion: 2.94 secs
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-->
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Total memory usage is 389560 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 8 ( 0 filtered)
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Number of infos : 7 ( 0 filtered)
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