126 lines
3 KiB
VHDL
126 lines
3 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:50:53 04/13/2021
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-- Design Name:
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-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd
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-- Project Name: ALU
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: alu
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY alu_test IS
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END alu_test;
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ARCHITECTURE behavior OF alu_test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT alu
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PORT(
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A : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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Ctrl_Alu : IN std_logic_vector(2 downto 0);
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N : OUT std_logic;
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O : OUT std_logic;
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Z : OUT std_logic;
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C : OUT std_logic;
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S : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal A : std_logic_vector(7 downto 0) := (others => '0');
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signal B : std_logic_vector(7 downto 0) := (others => '0');
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signal Ctrl_Alu : std_logic_vector(2 downto 0) := (others => '0');
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--Outputs
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signal N : std_logic;
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signal O : std_logic;
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signal Z : std_logic;
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signal C : std_logic;
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signal S : std_logic_vector(7 downto 0);
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-- No clocks detected in port list. Replace <clock> below with
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-- appropriate port name
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: alu PORT MAP (
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A => A,
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B => B,
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Ctrl_Alu => Ctrl_Alu,
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N => N,
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O => O,
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Z => Z,
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C => C,
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S => S
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);
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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-- 3 op on random numbers
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wait for 100 ns;
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A<="00000111";
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B<="00000011";
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wait for 100 ns;
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Ctrl_Alu<="001";
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wait for 30 ns;
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Ctrl_Alu<="010";
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wait for 30 ns;
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Ctrl_Alu<="011";
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wait for 30 ns;
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Ctrl_Alu<="000";
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wait for 30 ns;
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A<="11111111";
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B<="11111111";
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-- test carry
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wait for 100 ns;
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Ctrl_Alu<="001";
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-- test multiply
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wait for 30 ns;
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Ctrl_Alu<="011";
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--test null
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wait for 30 ns;
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Ctrl_Alu<="010";
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wait for 30 ns;
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Ctrl_Alu<="000";
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wait for 30 ns;
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-- test less than 0
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A<="00000001";
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wait for 30 ns;
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Ctrl_Alu<="010";
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wait;
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end process;
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END;
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