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stm32f1xx_ll_fsmc.h 39KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_fsmc.h
  4. * @author MCD Application Team
  5. * @brief Header file of FSMC HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32F1xx_LL_FSMC_H
  21. #define STM32F1xx_LL_FSMC_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f1xx_hal_def.h"
  27. /** @addtogroup STM32F1xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup FSMC_LL
  31. * @{
  32. */
  33. /** @addtogroup FSMC_LL_Private_Macros
  34. * @{
  35. */
  36. #if defined FSMC_BANK1
  37. #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
  38. ((__BANK__) == FSMC_NORSRAM_BANK2) || \
  39. ((__BANK__) == FSMC_NORSRAM_BANK3) || \
  40. ((__BANK__) == FSMC_NORSRAM_BANK4))
  41. #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
  42. ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
  43. #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
  44. ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
  45. ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
  46. #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
  47. ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  48. ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
  49. #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
  50. ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
  51. ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
  52. ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
  53. ((__SIZE__) == FSMC_PAGE_SIZE_1024))
  54. #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
  55. ((__MODE__) == FSMC_ACCESS_MODE_B) || \
  56. ((__MODE__) == FSMC_ACCESS_MODE_C) || \
  57. ((__MODE__) == FSMC_ACCESS_MODE_D))
  58. #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
  59. ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
  60. #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
  61. ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
  62. #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
  63. ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
  64. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
  65. ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
  66. #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
  67. ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
  68. #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
  69. ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
  70. #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
  71. ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
  72. #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
  73. ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
  74. #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
  75. #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
  76. ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
  77. #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
  78. ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
  79. #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
  80. #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
  81. #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
  82. #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
  83. #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
  84. #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
  85. #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
  86. #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
  87. #endif /* FSMC_BANK1 */
  88. #if defined(FSMC_BANK3)
  89. #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
  90. #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
  91. ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
  92. #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
  93. ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
  94. #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
  95. ((__STATE__) == FSMC_NAND_ECC_ENABLE))
  96. #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
  97. ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
  98. ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
  99. ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
  100. ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
  101. ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
  102. #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
  103. #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
  104. #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
  105. #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
  106. #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
  107. #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
  108. #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
  109. #endif /* FSMC_BANK3 */
  110. #if defined(FSMC_BANK4)
  111. #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
  112. #endif /* FSMC_BANK4 */
  113. /**
  114. * @}
  115. */
  116. /* Exported typedef ----------------------------------------------------------*/
  117. /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
  118. * @{
  119. */
  120. #if defined FSMC_BANK1
  121. #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
  122. #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
  123. #endif /* FSMC_BANK1 */
  124. #if defined(FSMC_BANK3)
  125. #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
  126. #endif /* FSMC_BANK3 */
  127. #if defined(FSMC_BANK4)
  128. #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
  129. #endif /* FSMC_BANK4 */
  130. #if defined FSMC_BANK1
  131. #define FSMC_NORSRAM_DEVICE FSMC_Bank1
  132. #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
  133. #endif /* FSMC_BANK1 */
  134. #if defined(FSMC_BANK3)
  135. #define FSMC_NAND_DEVICE FSMC_Bank2_3
  136. #endif /* FSMC_BANK3 */
  137. #if defined(FSMC_BANK4)
  138. #define FSMC_PCCARD_DEVICE FSMC_Bank4
  139. #endif /* FSMC_BANK4 */
  140. #if defined FSMC_BANK1
  141. /**
  142. * @brief FSMC NORSRAM Configuration Structure definition
  143. */
  144. typedef struct
  145. {
  146. uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
  147. This parameter can be a value of @ref FSMC_NORSRAM_Bank */
  148. uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
  149. multiplexed on the data bus or not.
  150. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
  151. uint32_t MemoryType; /*!< Specifies the type of external memory attached to
  152. the corresponding memory device.
  153. This parameter can be a value of @ref FSMC_Memory_Type */
  154. uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
  155. This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
  156. uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
  157. valid only with synchronous burst Flash memories.
  158. This parameter can be a value of @ref FSMC_Burst_Access_Mode */
  159. uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
  160. the Flash memory in burst mode.
  161. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
  162. uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
  163. memory, valid only when accessing Flash memories in burst mode.
  164. This parameter can be a value of @ref FSMC_Wrap_Mode */
  165. uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
  166. clock cycle before the wait state or during the wait state,
  167. valid only when accessing memories in burst mode.
  168. This parameter can be a value of @ref FSMC_Wait_Timing */
  169. uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
  170. This parameter can be a value of @ref FSMC_Write_Operation */
  171. uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
  172. signal, valid for Flash memory access in burst mode.
  173. This parameter can be a value of @ref FSMC_Wait_Signal */
  174. uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
  175. This parameter can be a value of @ref FSMC_Extended_Mode */
  176. uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
  177. valid only with asynchronous Flash memories.
  178. This parameter can be a value of @ref FSMC_AsynchronousWait */
  179. uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
  180. This parameter can be a value of @ref FSMC_Write_Burst */
  181. uint32_t PageSize; /*!< Specifies the memory page size.
  182. This parameter can be a value of @ref FSMC_Page_Size */
  183. }FSMC_NORSRAM_InitTypeDef;
  184. /**
  185. * @brief FSMC NORSRAM Timing parameters structure definition
  186. */
  187. typedef struct
  188. {
  189. uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
  190. the duration of the address setup time.
  191. This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  192. @note This parameter is not used with synchronous NOR Flash memories. */
  193. uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
  194. the duration of the address hold time.
  195. This parameter can be a value between Min_Data = 1 and Max_Data = 15.
  196. @note This parameter is not used with synchronous NOR Flash memories. */
  197. uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
  198. the duration of the data setup time.
  199. This parameter can be a value between Min_Data = 1 and Max_Data = 255.
  200. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
  201. NOR Flash memories. */
  202. uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
  203. the duration of the bus turnaround.
  204. This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  205. @note This parameter is only used for multiplexed NOR Flash memories. */
  206. uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
  207. HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
  208. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
  209. accesses. */
  210. uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
  211. to the memory before getting the first data.
  212. The parameter value depends on the memory type as shown below:
  213. - It must be set to 0 in case of a CRAM
  214. - It is don't care in asynchronous NOR, SRAM or ROM accesses
  215. - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
  216. with synchronous burst mode enable */
  217. uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
  218. This parameter can be a value of @ref FSMC_Access_Mode */
  219. }FSMC_NORSRAM_TimingTypeDef;
  220. #endif /* FSMC_BANK1 */
  221. #if defined(FSMC_BANK3)
  222. /**
  223. * @brief FSMC NAND Configuration Structure definition
  224. */
  225. typedef struct
  226. {
  227. uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
  228. This parameter can be a value of @ref FSMC_NAND_Bank */
  229. uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
  230. This parameter can be any value of @ref FSMC_Wait_feature */
  231. uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
  232. This parameter can be any value of @ref FSMC_NAND_Data_Width */
  233. uint32_t EccComputation; /*!< Enables or disables the ECC computation.
  234. This parameter can be any value of @ref FSMC_ECC */
  235. uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
  236. This parameter can be any value of @ref FSMC_ECC_Page_Size */
  237. uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
  238. delay between CLE low and RE low.
  239. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
  240. uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
  241. delay between ALE low and RE low.
  242. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  243. }FSMC_NAND_InitTypeDef;
  244. #endif
  245. #if defined(FSMC_BANK3)||defined(FSMC_BANK4)
  246. /**
  247. * @brief FSMC NAND Timing parameters structure definition
  248. */
  249. typedef struct
  250. {
  251. uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
  252. the command assertion for NAND-Flash read or write access
  253. to common/Attribute or I/O memory space (depending on
  254. the memory space timing to be configured).
  255. This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
  256. uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
  257. command for NAND-Flash read or write access to
  258. common/Attribute or I/O memory space (depending on the
  259. memory space timing to be configured).
  260. This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
  261. uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
  262. (and data for write access) after the command de-assertion
  263. for NAND-Flash read or write access to common/Attribute
  264. or I/O memory space (depending on the memory space timing
  265. to be configured).
  266. This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
  267. uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
  268. data bus is kept in HiZ after the start of a NAND-Flash
  269. write access to common/Attribute or I/O memory space (depending
  270. on the memory space timing to be configured).
  271. This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
  272. }FSMC_NAND_PCC_TimingTypeDef;
  273. #endif /* FSMC_BANK3 */
  274. #if defined(FSMC_BANK4)
  275. /**
  276. * @brief FSMC PCCARD Configuration Structure definition
  277. */
  278. typedef struct
  279. {
  280. uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
  281. This parameter can be any value of @ref FSMC_Wait_feature */
  282. uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
  283. delay between CLE low and RE low.
  284. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
  285. uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
  286. delay between ALE low and RE low.
  287. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  288. }FSMC_PCCARD_InitTypeDef;
  289. #endif
  290. /**
  291. * @}
  292. */
  293. /* Exported constants --------------------------------------------------------*/
  294. /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
  295. * @{
  296. */
  297. #if defined FSMC_BANK1
  298. /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
  299. * @{
  300. */
  301. /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
  302. * @{
  303. */
  304. #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
  305. #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
  306. #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
  307. #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
  308. /**
  309. * @}
  310. */
  311. /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
  312. * @{
  313. */
  314. #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
  315. #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
  316. /**
  317. * @}
  318. */
  319. /** @defgroup FSMC_Memory_Type FSMC Memory Type
  320. * @{
  321. */
  322. #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
  323. #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
  324. #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
  325. /**
  326. * @}
  327. */
  328. /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
  329. * @{
  330. */
  331. #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
  332. #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
  333. #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
  334. /**
  335. * @}
  336. */
  337. /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
  338. * @{
  339. */
  340. #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
  341. #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
  342. /**
  343. * @}
  344. */
  345. /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
  346. * @{
  347. */
  348. #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
  349. #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
  350. /**
  351. * @}
  352. */
  353. /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
  354. * @{
  355. */
  356. #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
  357. #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
  358. /**
  359. * @}
  360. */
  361. /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
  362. * @{
  363. */
  364. #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
  365. #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
  366. /**
  367. * @}
  368. */
  369. /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
  370. * @{
  371. */
  372. #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
  373. #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
  374. /**
  375. * @}
  376. */
  377. /** @defgroup FSMC_Write_Operation FSMC Write Operation
  378. * @{
  379. */
  380. #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
  381. #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
  382. /**
  383. * @}
  384. */
  385. /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
  386. * @{
  387. */
  388. #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
  389. #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
  390. /**
  391. * @}
  392. */
  393. /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
  394. * @{
  395. */
  396. #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
  397. #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
  398. /**
  399. * @}
  400. */
  401. /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
  402. * @{
  403. */
  404. #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
  405. #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
  406. /**
  407. * @}
  408. */
  409. /** @defgroup FSMC_Page_Size FSMC Page Size
  410. * @{
  411. */
  412. #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
  413. #define FSMC_PAGE_SIZE_128 ((uint32_t)0x00010000U)
  414. #define FSMC_PAGE_SIZE_256 ((uint32_t)0x00020000U)
  415. #define FSMC_PAGE_SIZE_512 ((uint32_t)0x00030000U)
  416. #define FSMC_PAGE_SIZE_1024 ((uint32_t)0x00040000U)
  417. /**
  418. * @}
  419. */
  420. /** @defgroup FSMC_Write_Burst FSMC Write Burst
  421. * @{
  422. */
  423. #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
  424. #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
  425. /**
  426. * @}
  427. */
  428. /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
  429. * @{
  430. */
  431. #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
  432. #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
  433. /**
  434. * @}
  435. */
  436. /** @defgroup FSMC_Access_Mode FSMC Access Mode
  437. * @{
  438. */
  439. #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
  440. #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
  441. #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
  442. #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
  443. /**
  444. * @}
  445. */
  446. /**
  447. * @}
  448. */
  449. #endif /* FSMC_BANK1 */
  450. #if defined(FSMC_BANK3)||defined(FSMC_BANK4)
  451. /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
  452. * @{
  453. */
  454. /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
  455. * @{
  456. */
  457. #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
  458. #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
  459. /**
  460. * @}
  461. */
  462. /** @defgroup FSMC_Wait_feature FSMC Wait feature
  463. * @{
  464. */
  465. #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
  466. #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
  467. /**
  468. * @}
  469. */
  470. /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
  471. * @{
  472. */
  473. #if defined(FSMC_BANK4)
  474. #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
  475. #endif
  476. #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
  477. /**
  478. * @}
  479. */
  480. /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
  481. * @{
  482. */
  483. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
  484. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
  485. /**
  486. * @}
  487. */
  488. /** @defgroup FSMC_ECC FSMC ECC
  489. * @{
  490. */
  491. #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
  492. #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
  493. /**
  494. * @}
  495. */
  496. /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
  497. * @{
  498. */
  499. #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
  500. #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
  501. #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
  502. #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
  503. #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
  504. #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
  505. /**
  506. * @}
  507. */
  508. /**
  509. * @}
  510. */
  511. #endif /* FSMC_BANK3 */
  512. /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
  513. * @{
  514. */
  515. #if defined(FSMC_BANK3)||defined(FSMC_BANK4)
  516. #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
  517. #define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
  518. #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
  519. #endif /* FSMC_BANK3 */
  520. /**
  521. * @}
  522. */
  523. /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
  524. * @{
  525. */
  526. #if defined(FSMC_BANK3)||defined(FSMC_BANK4)
  527. #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
  528. #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
  529. #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
  530. #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
  531. #endif /* FSMC_BANK3 */
  532. /**
  533. * @}
  534. */
  535. /**
  536. * @}
  537. */
  538. /**
  539. * @}
  540. */
  541. /* Private macro -------------------------------------------------------------*/
  542. /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
  543. * @{
  544. */
  545. #if defined FSMC_BANK1
  546. /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
  547. * @brief macros to handle NOR device enable/disable and read/write operations
  548. * @{
  549. */
  550. /**
  551. * @brief Enable the NORSRAM device access.
  552. * @param __INSTANCE__ FSMC_NORSRAM Instance
  553. * @param __BANK__ FSMC_NORSRAM Bank
  554. * @retval None
  555. */
  556. #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
  557. /**
  558. * @brief Disable the NORSRAM device access.
  559. * @param __INSTANCE__ FSMC_NORSRAM Instance
  560. * @param __BANK__ FSMC_NORSRAM Bank
  561. * @retval None
  562. */
  563. #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)
  564. /**
  565. * @}
  566. */
  567. #endif /* FSMC_BANK1 */
  568. #if defined(FSMC_BANK3)
  569. /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
  570. * @brief macros to handle NAND device enable/disable
  571. * @{
  572. */
  573. /**
  574. * @brief Enable the NAND device access.
  575. * @param __INSTANCE__ FSMC_NAND Instance
  576. * @param __BANK__ FSMC_NAND Bank
  577. * @retval None
  578. */
  579. #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \
  580. ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
  581. /**
  582. * @brief Disable the NAND device access.
  583. * @param __INSTANCE__ FSMC_NAND Instance
  584. * @param __BANK__ FSMC_NAND Bank
  585. * @retval None
  586. */
  587. #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  588. CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
  589. /**
  590. * @}
  591. */
  592. #endif
  593. #if defined(FSMC_BANK4)
  594. /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
  595. * @brief macros to handle PCCARD read/write operations
  596. * @{
  597. */
  598. /**
  599. * @brief Enable the PCCARD device access.
  600. * @param __INSTANCE__ FSMC_PCCARD Instance
  601. * @retval None
  602. */
  603. #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
  604. /**
  605. * @brief Disable the PCCARD device access.
  606. * @param __INSTANCE__ FSMC_PCCARD Instance
  607. * @retval None
  608. */
  609. #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
  610. /**
  611. * @}
  612. */
  613. #endif
  614. #if defined(FSMC_BANK3)
  615. /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
  616. * @brief macros to handle NAND interrupts
  617. * @{
  618. */
  619. /**
  620. * @brief Enable the NAND device interrupt.
  621. * @param __INSTANCE__ FSMC_NAND instance
  622. * @param __BANK__ FSMC_NAND Bank
  623. * @param __INTERRUPT__ FSMC_NAND interrupt
  624. * This parameter can be any combination of the following values:
  625. * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  626. * @arg FSMC_IT_LEVEL: Interrupt level.
  627. * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  628. * @retval None
  629. */
  630. #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
  631. ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
  632. /**
  633. * @brief Disable the NAND device interrupt.
  634. * @param __INSTANCE__ FSMC_NAND Instance
  635. * @param __BANK__ FSMC_NAND Bank
  636. * @param __INTERRUPT__ FSMC_NAND interrupt
  637. * This parameter can be any combination of the following values:
  638. * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  639. * @arg FSMC_IT_LEVEL: Interrupt level.
  640. * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  641. * @retval None
  642. */
  643. #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
  644. ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
  645. /**
  646. * @brief Get flag status of the NAND device.
  647. * @param __INSTANCE__ FSMC_NAND Instance
  648. * @param __BANK__ FSMC_NAND Bank
  649. * @param __FLAG__ FSMC_NAND flag
  650. * This parameter can be any combination of the following values:
  651. * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  652. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  653. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  654. * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  655. * @retval The state of FLAG (SET or RESET).
  656. */
  657. #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
  658. (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
  659. /**
  660. * @brief Clear flag status of the NAND device.
  661. * @param __INSTANCE__ FSMC_NAND Instance
  662. * @param __BANK__ FSMC_NAND Bank
  663. * @param __FLAG__ FSMC_NAND flag
  664. * This parameter can be any combination of the following values:
  665. * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  666. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  667. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  668. * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  669. * @retval None
  670. */
  671. #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
  672. ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
  673. /**
  674. * @}
  675. */
  676. #endif /* FSMC_BANK3 */
  677. #if defined(FSMC_BANK4)
  678. /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
  679. * @brief macros to handle PCCARD interrupts
  680. * @{
  681. */
  682. /**
  683. * @brief Enable the PCCARD device interrupt.
  684. * @param __INSTANCE__ FSMC_PCCARD instance
  685. * @param __INTERRUPT__ FSMC_PCCARD interrupt
  686. * This parameter can be any combination of the following values:
  687. * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  688. * @arg FSMC_IT_LEVEL: Interrupt level.
  689. * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  690. * @retval None
  691. */
  692. #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
  693. /**
  694. * @brief Disable the PCCARD device interrupt.
  695. * @param __INSTANCE__ FSMC_PCCARD instance
  696. * @param __INTERRUPT__ FSMC_PCCARD interrupt
  697. * This parameter can be any combination of the following values:
  698. * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  699. * @arg FSMC_IT_LEVEL: Interrupt level.
  700. * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  701. * @retval None
  702. */
  703. #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
  704. /**
  705. * @brief Get flag status of the PCCARD device.
  706. * @param __INSTANCE__ FSMC_PCCARD instance
  707. * @param __FLAG__ FSMC_PCCARD flag
  708. * This parameter can be any combination of the following values:
  709. * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  710. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  711. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  712. * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  713. * @retval The state of FLAG (SET or RESET).
  714. */
  715. #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
  716. /**
  717. * @brief Clear flag status of the PCCARD device.
  718. * @param __INSTANCE__ FSMC_PCCARD instance
  719. * @param __FLAG__ FSMC_PCCARD flag
  720. * This parameter can be any combination of the following values:
  721. * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  722. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  723. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  724. * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  725. * @retval None
  726. */
  727. #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
  728. /**
  729. * @}
  730. */
  731. #endif
  732. /**
  733. * @}
  734. */
  735. /**
  736. * @}
  737. */
  738. /* Private functions ---------------------------------------------------------*/
  739. /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
  740. * @{
  741. */
  742. #if defined FSMC_BANK1
  743. /** @defgroup FSMC_LL_NORSRAM NOR SRAM
  744. * @{
  745. */
  746. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
  747. * @{
  748. */
  749. HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
  750. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
  751. HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
  752. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
  753. /**
  754. * @}
  755. */
  756. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
  757. * @{
  758. */
  759. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  760. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  761. /**
  762. * @}
  763. */
  764. /**
  765. * @}
  766. */
  767. #endif /* FSMC_BANK1 */
  768. #if defined(FSMC_BANK3)
  769. /** @defgroup FSMC_LL_NAND NAND
  770. * @{
  771. */
  772. /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
  773. * @{
  774. */
  775. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
  776. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  777. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  778. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  779. /**
  780. * @}
  781. */
  782. /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
  783. * @{
  784. */
  785. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  786. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  787. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
  788. /**
  789. * @}
  790. */
  791. /**
  792. * @}
  793. */
  794. #endif /* FSMC_BANK3 */
  795. #if defined(FSMC_BANK4)
  796. /** @defgroup FSMC_LL_PCCARD PCCARD
  797. * @{
  798. */
  799. /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
  800. * @{
  801. */
  802. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
  803. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  804. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  805. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  806. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
  807. /**
  808. * @}
  809. */
  810. /**
  811. * @}
  812. */
  813. #endif /* FSMC_BANK4 */
  814. /**
  815. * @}
  816. */
  817. /**
  818. * @}
  819. */
  820. /**
  821. * @}
  822. */
  823. #ifdef __cplusplus
  824. }
  825. #endif
  826. #endif /* STM32F1xx_LL_FSMC_H */
  827. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/