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stm32f1xx_ll_dma.h 75KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_dma.h
  4. * @author MCD Application Team
  5. * @brief Header file of DMA LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef __STM32F1xx_LL_DMA_H
  21. #define __STM32F1xx_LL_DMA_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f1xx.h"
  27. /** @addtogroup STM32F1xx_LL_Driver
  28. * @{
  29. */
  30. #if defined (DMA1) || defined (DMA2)
  31. /** @defgroup DMA_LL DMA
  32. * @{
  33. */
  34. /* Private types -------------------------------------------------------------*/
  35. /* Private variables ---------------------------------------------------------*/
  36. /** @defgroup DMA_LL_Private_Variables DMA Private Variables
  37. * @{
  38. */
  39. /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
  40. static const uint8_t CHANNEL_OFFSET_TAB[] =
  41. {
  42. (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  43. (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  44. (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  45. (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  46. (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  47. (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
  48. (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
  49. };
  50. /**
  51. * @}
  52. */
  53. /* Private constants ---------------------------------------------------------*/
  54. /* Private macros ------------------------------------------------------------*/
  55. #if defined(USE_FULL_LL_DRIVER)
  56. /** @defgroup DMA_LL_Private_Macros DMA Private Macros
  57. * @{
  58. */
  59. /**
  60. * @}
  61. */
  62. #endif /*USE_FULL_LL_DRIVER*/
  63. /* Exported types ------------------------------------------------------------*/
  64. #if defined(USE_FULL_LL_DRIVER)
  65. /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
  66. * @{
  67. */
  68. typedef struct
  69. {
  70. uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
  71. or as Source base address in case of memory to memory transfer direction.
  72. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  73. uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
  74. or as Destination base address in case of memory to memory transfer direction.
  75. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  76. uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
  77. from memory to memory or from peripheral to memory.
  78. This parameter can be a value of @ref DMA_LL_EC_DIRECTION
  79. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
  80. uint32_t Mode; /*!< Specifies the normal or circular operation mode.
  81. This parameter can be a value of @ref DMA_LL_EC_MODE
  82. @note: The circular buffer mode cannot be used if the memory to memory
  83. data transfer direction is configured on the selected Channel
  84. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
  85. uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
  86. is incremented or not.
  87. This parameter can be a value of @ref DMA_LL_EC_PERIPH
  88. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
  89. uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
  90. is incremented or not.
  91. This parameter can be a value of @ref DMA_LL_EC_MEMORY
  92. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
  93. uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
  94. in case of memory to memory transfer direction.
  95. This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
  96. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
  97. uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
  98. in case of memory to memory transfer direction.
  99. This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
  100. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
  101. uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
  102. The data unit is equal to the source buffer configuration set in PeripheralSize
  103. or MemorySize parameters depending in the transfer direction.
  104. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
  105. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
  106. uint32_t Priority; /*!< Specifies the channel priority level.
  107. This parameter can be a value of @ref DMA_LL_EC_PRIORITY
  108. This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
  109. } LL_DMA_InitTypeDef;
  110. /**
  111. * @}
  112. */
  113. #endif /*USE_FULL_LL_DRIVER*/
  114. /* Exported constants --------------------------------------------------------*/
  115. /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
  116. * @{
  117. */
  118. /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
  119. * @brief Flags defines which can be used with LL_DMA_WriteReg function
  120. * @{
  121. */
  122. #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
  123. #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
  124. #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
  125. #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
  126. #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
  127. #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
  128. #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
  129. #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
  130. #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
  131. #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
  132. #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
  133. #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
  134. #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
  135. #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
  136. #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
  137. #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
  138. #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
  139. #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
  140. #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
  141. #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
  142. #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
  143. #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
  144. #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
  145. #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
  146. #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
  147. #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
  148. #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
  149. #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
  150. /**
  151. * @}
  152. */
  153. /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
  154. * @brief Flags defines which can be used with LL_DMA_ReadReg function
  155. * @{
  156. */
  157. #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
  158. #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
  159. #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
  160. #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
  161. #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
  162. #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
  163. #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
  164. #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
  165. #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
  166. #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
  167. #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
  168. #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
  169. #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
  170. #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
  171. #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
  172. #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
  173. #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
  174. #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
  175. #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
  176. #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
  177. #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
  178. #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
  179. #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
  180. #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
  181. #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
  182. #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
  183. #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
  184. #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
  185. /**
  186. * @}
  187. */
  188. /** @defgroup DMA_LL_EC_IT IT Defines
  189. * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
  190. * @{
  191. */
  192. #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
  193. #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
  194. #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
  195. /**
  196. * @}
  197. */
  198. /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
  199. * @{
  200. */
  201. #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
  202. #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
  203. #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
  204. #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
  205. #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
  206. #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
  207. #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
  208. #if defined(USE_FULL_LL_DRIVER)
  209. #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
  210. #endif /*USE_FULL_LL_DRIVER*/
  211. /**
  212. * @}
  213. */
  214. /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
  215. * @{
  216. */
  217. #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
  218. #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
  219. #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
  220. /**
  221. * @}
  222. */
  223. /** @defgroup DMA_LL_EC_MODE Transfer mode
  224. * @{
  225. */
  226. #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
  227. #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
  228. /**
  229. * @}
  230. */
  231. /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
  232. * @{
  233. */
  234. #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
  235. #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
  236. /**
  237. * @}
  238. */
  239. /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
  240. * @{
  241. */
  242. #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
  243. #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
  244. /**
  245. * @}
  246. */
  247. /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
  248. * @{
  249. */
  250. #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
  251. #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
  252. #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
  253. /**
  254. * @}
  255. */
  256. /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
  257. * @{
  258. */
  259. #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
  260. #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
  261. #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
  262. /**
  263. * @}
  264. */
  265. /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
  266. * @{
  267. */
  268. #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
  269. #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
  270. #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
  271. #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
  272. /**
  273. * @}
  274. */
  275. /**
  276. * @}
  277. */
  278. /* Exported macro ------------------------------------------------------------*/
  279. /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
  280. * @{
  281. */
  282. /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
  283. * @{
  284. */
  285. /**
  286. * @brief Write a value in DMA register
  287. * @param __INSTANCE__ DMA Instance
  288. * @param __REG__ Register to be written
  289. * @param __VALUE__ Value to be written in the register
  290. * @retval None
  291. */
  292. #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  293. /**
  294. * @brief Read a value in DMA register
  295. * @param __INSTANCE__ DMA Instance
  296. * @param __REG__ Register to be read
  297. * @retval Register value
  298. */
  299. #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  300. /**
  301. * @}
  302. */
  303. /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
  304. * @{
  305. */
  306. /**
  307. * @brief Convert DMAx_Channely into DMAx
  308. * @param __CHANNEL_INSTANCE__ DMAx_Channely
  309. * @retval DMAx
  310. */
  311. #if defined(DMA2)
  312. #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
  313. (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
  314. #else
  315. #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
  316. #endif
  317. /**
  318. * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
  319. * @param __CHANNEL_INSTANCE__ DMAx_Channely
  320. * @retval LL_DMA_CHANNEL_y
  321. */
  322. #if defined (DMA2)
  323. #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
  324. (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
  325. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
  326. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
  327. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
  328. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
  329. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
  330. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
  331. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
  332. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
  333. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
  334. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
  335. LL_DMA_CHANNEL_7)
  336. #else
  337. #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
  338. (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
  339. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
  340. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
  341. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
  342. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
  343. ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
  344. LL_DMA_CHANNEL_7)
  345. #endif
  346. /**
  347. * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
  348. * @param __DMA_INSTANCE__ DMAx
  349. * @param __CHANNEL__ LL_DMA_CHANNEL_y
  350. * @retval DMAx_Channely
  351. */
  352. #if defined (DMA2)
  353. #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
  354. ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
  355. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
  356. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
  357. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
  358. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
  359. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
  360. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
  361. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
  362. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
  363. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
  364. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
  365. DMA1_Channel7)
  366. #else
  367. #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
  368. ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
  369. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
  370. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
  371. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
  372. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
  373. (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
  374. DMA1_Channel7)
  375. #endif
  376. /**
  377. * @}
  378. */
  379. /**
  380. * @}
  381. */
  382. /* Exported functions --------------------------------------------------------*/
  383. /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
  384. * @{
  385. */
  386. /** @defgroup DMA_LL_EF_Configuration Configuration
  387. * @{
  388. */
  389. /**
  390. * @brief Enable DMA channel.
  391. * @rmtoll CCR EN LL_DMA_EnableChannel
  392. * @param DMAx DMAx Instance
  393. * @param Channel This parameter can be one of the following values:
  394. * @arg @ref LL_DMA_CHANNEL_1
  395. * @arg @ref LL_DMA_CHANNEL_2
  396. * @arg @ref LL_DMA_CHANNEL_3
  397. * @arg @ref LL_DMA_CHANNEL_4
  398. * @arg @ref LL_DMA_CHANNEL_5
  399. * @arg @ref LL_DMA_CHANNEL_6
  400. * @arg @ref LL_DMA_CHANNEL_7
  401. * @retval None
  402. */
  403. __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  404. {
  405. SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
  406. }
  407. /**
  408. * @brief Disable DMA channel.
  409. * @rmtoll CCR EN LL_DMA_DisableChannel
  410. * @param DMAx DMAx Instance
  411. * @param Channel This parameter can be one of the following values:
  412. * @arg @ref LL_DMA_CHANNEL_1
  413. * @arg @ref LL_DMA_CHANNEL_2
  414. * @arg @ref LL_DMA_CHANNEL_3
  415. * @arg @ref LL_DMA_CHANNEL_4
  416. * @arg @ref LL_DMA_CHANNEL_5
  417. * @arg @ref LL_DMA_CHANNEL_6
  418. * @arg @ref LL_DMA_CHANNEL_7
  419. * @retval None
  420. */
  421. __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  422. {
  423. CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
  424. }
  425. /**
  426. * @brief Check if DMA channel is enabled or disabled.
  427. * @rmtoll CCR EN LL_DMA_IsEnabledChannel
  428. * @param DMAx DMAx Instance
  429. * @param Channel This parameter can be one of the following values:
  430. * @arg @ref LL_DMA_CHANNEL_1
  431. * @arg @ref LL_DMA_CHANNEL_2
  432. * @arg @ref LL_DMA_CHANNEL_3
  433. * @arg @ref LL_DMA_CHANNEL_4
  434. * @arg @ref LL_DMA_CHANNEL_5
  435. * @arg @ref LL_DMA_CHANNEL_6
  436. * @arg @ref LL_DMA_CHANNEL_7
  437. * @retval State of bit (1 or 0).
  438. */
  439. __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  440. {
  441. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  442. DMA_CCR_EN) == (DMA_CCR_EN));
  443. }
  444. /**
  445. * @brief Configure all parameters link to DMA transfer.
  446. * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
  447. * CCR MEM2MEM LL_DMA_ConfigTransfer\n
  448. * CCR CIRC LL_DMA_ConfigTransfer\n
  449. * CCR PINC LL_DMA_ConfigTransfer\n
  450. * CCR MINC LL_DMA_ConfigTransfer\n
  451. * CCR PSIZE LL_DMA_ConfigTransfer\n
  452. * CCR MSIZE LL_DMA_ConfigTransfer\n
  453. * CCR PL LL_DMA_ConfigTransfer
  454. * @param DMAx DMAx Instance
  455. * @param Channel This parameter can be one of the following values:
  456. * @arg @ref LL_DMA_CHANNEL_1
  457. * @arg @ref LL_DMA_CHANNEL_2
  458. * @arg @ref LL_DMA_CHANNEL_3
  459. * @arg @ref LL_DMA_CHANNEL_4
  460. * @arg @ref LL_DMA_CHANNEL_5
  461. * @arg @ref LL_DMA_CHANNEL_6
  462. * @arg @ref LL_DMA_CHANNEL_7
  463. * @param Configuration This parameter must be a combination of all the following values:
  464. * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  465. * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
  466. * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
  467. * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
  468. * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
  469. * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
  470. * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
  471. * @retval None
  472. */
  473. __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
  474. {
  475. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  476. DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
  477. Configuration);
  478. }
  479. /**
  480. * @brief Set Data transfer direction (read from peripheral or from memory).
  481. * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
  482. * CCR MEM2MEM LL_DMA_SetDataTransferDirection
  483. * @param DMAx DMAx Instance
  484. * @param Channel This parameter can be one of the following values:
  485. * @arg @ref LL_DMA_CHANNEL_1
  486. * @arg @ref LL_DMA_CHANNEL_2
  487. * @arg @ref LL_DMA_CHANNEL_3
  488. * @arg @ref LL_DMA_CHANNEL_4
  489. * @arg @ref LL_DMA_CHANNEL_5
  490. * @arg @ref LL_DMA_CHANNEL_6
  491. * @arg @ref LL_DMA_CHANNEL_7
  492. * @param Direction This parameter can be one of the following values:
  493. * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  494. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  495. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  496. * @retval None
  497. */
  498. __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
  499. {
  500. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  501. DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
  502. }
  503. /**
  504. * @brief Get Data transfer direction (read from peripheral or from memory).
  505. * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
  506. * CCR MEM2MEM LL_DMA_GetDataTransferDirection
  507. * @param DMAx DMAx Instance
  508. * @param Channel This parameter can be one of the following values:
  509. * @arg @ref LL_DMA_CHANNEL_1
  510. * @arg @ref LL_DMA_CHANNEL_2
  511. * @arg @ref LL_DMA_CHANNEL_3
  512. * @arg @ref LL_DMA_CHANNEL_4
  513. * @arg @ref LL_DMA_CHANNEL_5
  514. * @arg @ref LL_DMA_CHANNEL_6
  515. * @arg @ref LL_DMA_CHANNEL_7
  516. * @retval Returned value can be one of the following values:
  517. * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  518. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  519. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  520. */
  521. __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
  522. {
  523. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  524. DMA_CCR_DIR | DMA_CCR_MEM2MEM));
  525. }
  526. /**
  527. * @brief Set DMA mode circular or normal.
  528. * @note The circular buffer mode cannot be used if the memory-to-memory
  529. * data transfer is configured on the selected Channel.
  530. * @rmtoll CCR CIRC LL_DMA_SetMode
  531. * @param DMAx DMAx Instance
  532. * @param Channel This parameter can be one of the following values:
  533. * @arg @ref LL_DMA_CHANNEL_1
  534. * @arg @ref LL_DMA_CHANNEL_2
  535. * @arg @ref LL_DMA_CHANNEL_3
  536. * @arg @ref LL_DMA_CHANNEL_4
  537. * @arg @ref LL_DMA_CHANNEL_5
  538. * @arg @ref LL_DMA_CHANNEL_6
  539. * @arg @ref LL_DMA_CHANNEL_7
  540. * @param Mode This parameter can be one of the following values:
  541. * @arg @ref LL_DMA_MODE_NORMAL
  542. * @arg @ref LL_DMA_MODE_CIRCULAR
  543. * @retval None
  544. */
  545. __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
  546. {
  547. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
  548. Mode);
  549. }
  550. /**
  551. * @brief Get DMA mode circular or normal.
  552. * @rmtoll CCR CIRC LL_DMA_GetMode
  553. * @param DMAx DMAx Instance
  554. * @param Channel This parameter can be one of the following values:
  555. * @arg @ref LL_DMA_CHANNEL_1
  556. * @arg @ref LL_DMA_CHANNEL_2
  557. * @arg @ref LL_DMA_CHANNEL_3
  558. * @arg @ref LL_DMA_CHANNEL_4
  559. * @arg @ref LL_DMA_CHANNEL_5
  560. * @arg @ref LL_DMA_CHANNEL_6
  561. * @arg @ref LL_DMA_CHANNEL_7
  562. * @retval Returned value can be one of the following values:
  563. * @arg @ref LL_DMA_MODE_NORMAL
  564. * @arg @ref LL_DMA_MODE_CIRCULAR
  565. */
  566. __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
  567. {
  568. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  569. DMA_CCR_CIRC));
  570. }
  571. /**
  572. * @brief Set Peripheral increment mode.
  573. * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
  574. * @param DMAx DMAx Instance
  575. * @param Channel This parameter can be one of the following values:
  576. * @arg @ref LL_DMA_CHANNEL_1
  577. * @arg @ref LL_DMA_CHANNEL_2
  578. * @arg @ref LL_DMA_CHANNEL_3
  579. * @arg @ref LL_DMA_CHANNEL_4
  580. * @arg @ref LL_DMA_CHANNEL_5
  581. * @arg @ref LL_DMA_CHANNEL_6
  582. * @arg @ref LL_DMA_CHANNEL_7
  583. * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  584. * @arg @ref LL_DMA_PERIPH_INCREMENT
  585. * @arg @ref LL_DMA_PERIPH_NOINCREMENT
  586. * @retval None
  587. */
  588. __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
  589. {
  590. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
  591. PeriphOrM2MSrcIncMode);
  592. }
  593. /**
  594. * @brief Get Peripheral increment mode.
  595. * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
  596. * @param DMAx DMAx Instance
  597. * @param Channel This parameter can be one of the following values:
  598. * @arg @ref LL_DMA_CHANNEL_1
  599. * @arg @ref LL_DMA_CHANNEL_2
  600. * @arg @ref LL_DMA_CHANNEL_3
  601. * @arg @ref LL_DMA_CHANNEL_4
  602. * @arg @ref LL_DMA_CHANNEL_5
  603. * @arg @ref LL_DMA_CHANNEL_6
  604. * @arg @ref LL_DMA_CHANNEL_7
  605. * @retval Returned value can be one of the following values:
  606. * @arg @ref LL_DMA_PERIPH_INCREMENT
  607. * @arg @ref LL_DMA_PERIPH_NOINCREMENT
  608. */
  609. __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
  610. {
  611. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  612. DMA_CCR_PINC));
  613. }
  614. /**
  615. * @brief Set Memory increment mode.
  616. * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
  617. * @param DMAx DMAx Instance
  618. * @param Channel This parameter can be one of the following values:
  619. * @arg @ref LL_DMA_CHANNEL_1
  620. * @arg @ref LL_DMA_CHANNEL_2
  621. * @arg @ref LL_DMA_CHANNEL_3
  622. * @arg @ref LL_DMA_CHANNEL_4
  623. * @arg @ref LL_DMA_CHANNEL_5
  624. * @arg @ref LL_DMA_CHANNEL_6
  625. * @arg @ref LL_DMA_CHANNEL_7
  626. * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
  627. * @arg @ref LL_DMA_MEMORY_INCREMENT
  628. * @arg @ref LL_DMA_MEMORY_NOINCREMENT
  629. * @retval None
  630. */
  631. __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
  632. {
  633. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
  634. MemoryOrM2MDstIncMode);
  635. }
  636. /**
  637. * @brief Get Memory increment mode.
  638. * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
  639. * @param DMAx DMAx Instance
  640. * @param Channel This parameter can be one of the following values:
  641. * @arg @ref LL_DMA_CHANNEL_1
  642. * @arg @ref LL_DMA_CHANNEL_2
  643. * @arg @ref LL_DMA_CHANNEL_3
  644. * @arg @ref LL_DMA_CHANNEL_4
  645. * @arg @ref LL_DMA_CHANNEL_5
  646. * @arg @ref LL_DMA_CHANNEL_6
  647. * @arg @ref LL_DMA_CHANNEL_7
  648. * @retval Returned value can be one of the following values:
  649. * @arg @ref LL_DMA_MEMORY_INCREMENT
  650. * @arg @ref LL_DMA_MEMORY_NOINCREMENT
  651. */
  652. __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
  653. {
  654. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  655. DMA_CCR_MINC));
  656. }
  657. /**
  658. * @brief Set Peripheral size.
  659. * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
  660. * @param DMAx DMAx Instance
  661. * @param Channel This parameter can be one of the following values:
  662. * @arg @ref LL_DMA_CHANNEL_1
  663. * @arg @ref LL_DMA_CHANNEL_2
  664. * @arg @ref LL_DMA_CHANNEL_3
  665. * @arg @ref LL_DMA_CHANNEL_4
  666. * @arg @ref LL_DMA_CHANNEL_5
  667. * @arg @ref LL_DMA_CHANNEL_6
  668. * @arg @ref LL_DMA_CHANNEL_7
  669. * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  670. * @arg @ref LL_DMA_PDATAALIGN_BYTE
  671. * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
  672. * @arg @ref LL_DMA_PDATAALIGN_WORD
  673. * @retval None
  674. */
  675. __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
  676. {
  677. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
  678. PeriphOrM2MSrcDataSize);
  679. }
  680. /**
  681. * @brief Get Peripheral size.
  682. * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
  683. * @param DMAx DMAx Instance
  684. * @param Channel This parameter can be one of the following values:
  685. * @arg @ref LL_DMA_CHANNEL_1
  686. * @arg @ref LL_DMA_CHANNEL_2
  687. * @arg @ref LL_DMA_CHANNEL_3
  688. * @arg @ref LL_DMA_CHANNEL_4
  689. * @arg @ref LL_DMA_CHANNEL_5
  690. * @arg @ref LL_DMA_CHANNEL_6
  691. * @arg @ref LL_DMA_CHANNEL_7
  692. * @retval Returned value can be one of the following values:
  693. * @arg @ref LL_DMA_PDATAALIGN_BYTE
  694. * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
  695. * @arg @ref LL_DMA_PDATAALIGN_WORD
  696. */
  697. __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
  698. {
  699. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  700. DMA_CCR_PSIZE));
  701. }
  702. /**
  703. * @brief Set Memory size.
  704. * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
  705. * @param DMAx DMAx Instance
  706. * @param Channel This parameter can be one of the following values:
  707. * @arg @ref LL_DMA_CHANNEL_1
  708. * @arg @ref LL_DMA_CHANNEL_2
  709. * @arg @ref LL_DMA_CHANNEL_3
  710. * @arg @ref LL_DMA_CHANNEL_4
  711. * @arg @ref LL_DMA_CHANNEL_5
  712. * @arg @ref LL_DMA_CHANNEL_6
  713. * @arg @ref LL_DMA_CHANNEL_7
  714. * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
  715. * @arg @ref LL_DMA_MDATAALIGN_BYTE
  716. * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
  717. * @arg @ref LL_DMA_MDATAALIGN_WORD
  718. * @retval None
  719. */
  720. __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
  721. {
  722. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
  723. MemoryOrM2MDstDataSize);
  724. }
  725. /**
  726. * @brief Get Memory size.
  727. * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
  728. * @param DMAx DMAx Instance
  729. * @param Channel This parameter can be one of the following values:
  730. * @arg @ref LL_DMA_CHANNEL_1
  731. * @arg @ref LL_DMA_CHANNEL_2
  732. * @arg @ref LL_DMA_CHANNEL_3
  733. * @arg @ref LL_DMA_CHANNEL_4
  734. * @arg @ref LL_DMA_CHANNEL_5
  735. * @arg @ref LL_DMA_CHANNEL_6
  736. * @arg @ref LL_DMA_CHANNEL_7
  737. * @retval Returned value can be one of the following values:
  738. * @arg @ref LL_DMA_MDATAALIGN_BYTE
  739. * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
  740. * @arg @ref LL_DMA_MDATAALIGN_WORD
  741. */
  742. __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
  743. {
  744. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  745. DMA_CCR_MSIZE));
  746. }
  747. /**
  748. * @brief Set Channel priority level.
  749. * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
  750. * @param DMAx DMAx Instance
  751. * @param Channel This parameter can be one of the following values:
  752. * @arg @ref LL_DMA_CHANNEL_1
  753. * @arg @ref LL_DMA_CHANNEL_2
  754. * @arg @ref LL_DMA_CHANNEL_3
  755. * @arg @ref LL_DMA_CHANNEL_4
  756. * @arg @ref LL_DMA_CHANNEL_5
  757. * @arg @ref LL_DMA_CHANNEL_6
  758. * @arg @ref LL_DMA_CHANNEL_7
  759. * @param Priority This parameter can be one of the following values:
  760. * @arg @ref LL_DMA_PRIORITY_LOW
  761. * @arg @ref LL_DMA_PRIORITY_MEDIUM
  762. * @arg @ref LL_DMA_PRIORITY_HIGH
  763. * @arg @ref LL_DMA_PRIORITY_VERYHIGH
  764. * @retval None
  765. */
  766. __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
  767. {
  768. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
  769. Priority);
  770. }
  771. /**
  772. * @brief Get Channel priority level.
  773. * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
  774. * @param DMAx DMAx Instance
  775. * @param Channel This parameter can be one of the following values:
  776. * @arg @ref LL_DMA_CHANNEL_1
  777. * @arg @ref LL_DMA_CHANNEL_2
  778. * @arg @ref LL_DMA_CHANNEL_3
  779. * @arg @ref LL_DMA_CHANNEL_4
  780. * @arg @ref LL_DMA_CHANNEL_5
  781. * @arg @ref LL_DMA_CHANNEL_6
  782. * @arg @ref LL_DMA_CHANNEL_7
  783. * @retval Returned value can be one of the following values:
  784. * @arg @ref LL_DMA_PRIORITY_LOW
  785. * @arg @ref LL_DMA_PRIORITY_MEDIUM
  786. * @arg @ref LL_DMA_PRIORITY_HIGH
  787. * @arg @ref LL_DMA_PRIORITY_VERYHIGH
  788. */
  789. __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
  790. {
  791. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  792. DMA_CCR_PL));
  793. }
  794. /**
  795. * @brief Set Number of data to transfer.
  796. * @note This action has no effect if
  797. * channel is enabled.
  798. * @rmtoll CNDTR NDT LL_DMA_SetDataLength
  799. * @param DMAx DMAx Instance
  800. * @param Channel This parameter can be one of the following values:
  801. * @arg @ref LL_DMA_CHANNEL_1
  802. * @arg @ref LL_DMA_CHANNEL_2
  803. * @arg @ref LL_DMA_CHANNEL_3
  804. * @arg @ref LL_DMA_CHANNEL_4
  805. * @arg @ref LL_DMA_CHANNEL_5
  806. * @arg @ref LL_DMA_CHANNEL_6
  807. * @arg @ref LL_DMA_CHANNEL_7
  808. * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
  809. * @retval None
  810. */
  811. __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
  812. {
  813. MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
  814. DMA_CNDTR_NDT, NbData);
  815. }
  816. /**
  817. * @brief Get Number of data to transfer.
  818. * @note Once the channel is enabled, the return value indicate the
  819. * remaining bytes to be transmitted.
  820. * @rmtoll CNDTR NDT LL_DMA_GetDataLength
  821. * @param DMAx DMAx Instance
  822. * @param Channel This parameter can be one of the following values:
  823. * @arg @ref LL_DMA_CHANNEL_1
  824. * @arg @ref LL_DMA_CHANNEL_2
  825. * @arg @ref LL_DMA_CHANNEL_3
  826. * @arg @ref LL_DMA_CHANNEL_4
  827. * @arg @ref LL_DMA_CHANNEL_5
  828. * @arg @ref LL_DMA_CHANNEL_6
  829. * @arg @ref LL_DMA_CHANNEL_7
  830. * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  831. */
  832. __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
  833. {
  834. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
  835. DMA_CNDTR_NDT));
  836. }
  837. /**
  838. * @brief Configure the Source and Destination addresses.
  839. * @note This API must not be called when the DMA channel is enabled.
  840. * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
  841. * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
  842. * CMAR MA LL_DMA_ConfigAddresses
  843. * @param DMAx DMAx Instance
  844. * @param Channel This parameter can be one of the following values:
  845. * @arg @ref LL_DMA_CHANNEL_1
  846. * @arg @ref LL_DMA_CHANNEL_2
  847. * @arg @ref LL_DMA_CHANNEL_3
  848. * @arg @ref LL_DMA_CHANNEL_4
  849. * @arg @ref LL_DMA_CHANNEL_5
  850. * @arg @ref LL_DMA_CHANNEL_6
  851. * @arg @ref LL_DMA_CHANNEL_7
  852. * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  853. * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  854. * @param Direction This parameter can be one of the following values:
  855. * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  856. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  857. * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  858. * @retval None
  859. */
  860. __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
  861. uint32_t DstAddress, uint32_t Direction)
  862. {
  863. /* Direction Memory to Periph */
  864. if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
  865. {
  866. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
  867. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
  868. }
  869. /* Direction Periph to Memory and Memory to Memory */
  870. else
  871. {
  872. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
  873. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
  874. }
  875. }
  876. /**
  877. * @brief Set the Memory address.
  878. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  879. * @note This API must not be called when the DMA channel is enabled.
  880. * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
  881. * @param DMAx DMAx Instance
  882. * @param Channel This parameter can be one of the following values:
  883. * @arg @ref LL_DMA_CHANNEL_1
  884. * @arg @ref LL_DMA_CHANNEL_2
  885. * @arg @ref LL_DMA_CHANNEL_3
  886. * @arg @ref LL_DMA_CHANNEL_4
  887. * @arg @ref LL_DMA_CHANNEL_5
  888. * @arg @ref LL_DMA_CHANNEL_6
  889. * @arg @ref LL_DMA_CHANNEL_7
  890. * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  891. * @retval None
  892. */
  893. __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  894. {
  895. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
  896. }
  897. /**
  898. * @brief Set the Peripheral address.
  899. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  900. * @note This API must not be called when the DMA channel is enabled.
  901. * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
  902. * @param DMAx DMAx Instance
  903. * @param Channel This parameter can be one of the following values:
  904. * @arg @ref LL_DMA_CHANNEL_1
  905. * @arg @ref LL_DMA_CHANNEL_2
  906. * @arg @ref LL_DMA_CHANNEL_3
  907. * @arg @ref LL_DMA_CHANNEL_4
  908. * @arg @ref LL_DMA_CHANNEL_5
  909. * @arg @ref LL_DMA_CHANNEL_6
  910. * @arg @ref LL_DMA_CHANNEL_7
  911. * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  912. * @retval None
  913. */
  914. __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
  915. {
  916. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
  917. }
  918. /**
  919. * @brief Get Memory address.
  920. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  921. * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
  922. * @param DMAx DMAx Instance
  923. * @param Channel This parameter can be one of the following values:
  924. * @arg @ref LL_DMA_CHANNEL_1
  925. * @arg @ref LL_DMA_CHANNEL_2
  926. * @arg @ref LL_DMA_CHANNEL_3
  927. * @arg @ref LL_DMA_CHANNEL_4
  928. * @arg @ref LL_DMA_CHANNEL_5
  929. * @arg @ref LL_DMA_CHANNEL_6
  930. * @arg @ref LL_DMA_CHANNEL_7
  931. * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  932. */
  933. __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  934. {
  935. return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
  936. }
  937. /**
  938. * @brief Get Peripheral address.
  939. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  940. * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
  941. * @param DMAx DMAx Instance
  942. * @param Channel This parameter can be one of the following values:
  943. * @arg @ref LL_DMA_CHANNEL_1
  944. * @arg @ref LL_DMA_CHANNEL_2
  945. * @arg @ref LL_DMA_CHANNEL_3
  946. * @arg @ref LL_DMA_CHANNEL_4
  947. * @arg @ref LL_DMA_CHANNEL_5
  948. * @arg @ref LL_DMA_CHANNEL_6
  949. * @arg @ref LL_DMA_CHANNEL_7
  950. * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  951. */
  952. __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  953. {
  954. return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
  955. }
  956. /**
  957. * @brief Set the Memory to Memory Source address.
  958. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  959. * @note This API must not be called when the DMA channel is enabled.
  960. * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
  961. * @param DMAx DMAx Instance
  962. * @param Channel This parameter can be one of the following values:
  963. * @arg @ref LL_DMA_CHANNEL_1
  964. * @arg @ref LL_DMA_CHANNEL_2
  965. * @arg @ref LL_DMA_CHANNEL_3
  966. * @arg @ref LL_DMA_CHANNEL_4
  967. * @arg @ref LL_DMA_CHANNEL_5
  968. * @arg @ref LL_DMA_CHANNEL_6
  969. * @arg @ref LL_DMA_CHANNEL_7
  970. * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  971. * @retval None
  972. */
  973. __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  974. {
  975. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
  976. }
  977. /**
  978. * @brief Set the Memory to Memory Destination address.
  979. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  980. * @note This API must not be called when the DMA channel is enabled.
  981. * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
  982. * @param DMAx DMAx Instance
  983. * @param Channel This parameter can be one of the following values:
  984. * @arg @ref LL_DMA_CHANNEL_1
  985. * @arg @ref LL_DMA_CHANNEL_2
  986. * @arg @ref LL_DMA_CHANNEL_3
  987. * @arg @ref LL_DMA_CHANNEL_4
  988. * @arg @ref LL_DMA_CHANNEL_5
  989. * @arg @ref LL_DMA_CHANNEL_6
  990. * @arg @ref LL_DMA_CHANNEL_7
  991. * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  992. * @retval None
  993. */
  994. __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  995. {
  996. WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
  997. }
  998. /**
  999. * @brief Get the Memory to Memory Source address.
  1000. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1001. * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
  1002. * @param DMAx DMAx Instance
  1003. * @param Channel This parameter can be one of the following values:
  1004. * @arg @ref LL_DMA_CHANNEL_1
  1005. * @arg @ref LL_DMA_CHANNEL_2
  1006. * @arg @ref LL_DMA_CHANNEL_3
  1007. * @arg @ref LL_DMA_CHANNEL_4
  1008. * @arg @ref LL_DMA_CHANNEL_5
  1009. * @arg @ref LL_DMA_CHANNEL_6
  1010. * @arg @ref LL_DMA_CHANNEL_7
  1011. * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1012. */
  1013. __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1014. {
  1015. return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
  1016. }
  1017. /**
  1018. * @brief Get the Memory to Memory Destination address.
  1019. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1020. * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
  1021. * @param DMAx DMAx Instance
  1022. * @param Channel This parameter can be one of the following values:
  1023. * @arg @ref LL_DMA_CHANNEL_1
  1024. * @arg @ref LL_DMA_CHANNEL_2
  1025. * @arg @ref LL_DMA_CHANNEL_3
  1026. * @arg @ref LL_DMA_CHANNEL_4
  1027. * @arg @ref LL_DMA_CHANNEL_5
  1028. * @arg @ref LL_DMA_CHANNEL_6
  1029. * @arg @ref LL_DMA_CHANNEL_7
  1030. * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1031. */
  1032. __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1033. {
  1034. return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
  1035. }
  1036. /**
  1037. * @}
  1038. */
  1039. /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
  1040. * @{
  1041. */
  1042. /**
  1043. * @brief Get Channel 1 global interrupt flag.
  1044. * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
  1045. * @param DMAx DMAx Instance
  1046. * @retval State of bit (1 or 0).
  1047. */
  1048. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
  1049. {
  1050. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
  1051. }
  1052. /**
  1053. * @brief Get Channel 2 global interrupt flag.
  1054. * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
  1055. * @param DMAx DMAx Instance
  1056. * @retval State of bit (1 or 0).
  1057. */
  1058. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
  1059. {
  1060. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
  1061. }
  1062. /**
  1063. * @brief Get Channel 3 global interrupt flag.
  1064. * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
  1065. * @param DMAx DMAx Instance
  1066. * @retval State of bit (1 or 0).
  1067. */
  1068. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
  1069. {
  1070. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
  1071. }
  1072. /**
  1073. * @brief Get Channel 4 global interrupt flag.
  1074. * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
  1075. * @param DMAx DMAx Instance
  1076. * @retval State of bit (1 or 0).
  1077. */
  1078. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
  1079. {
  1080. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
  1081. }
  1082. /**
  1083. * @brief Get Channel 5 global interrupt flag.
  1084. * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
  1085. * @param DMAx DMAx Instance
  1086. * @retval State of bit (1 or 0).
  1087. */
  1088. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
  1089. {
  1090. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
  1091. }
  1092. /**
  1093. * @brief Get Channel 6 global interrupt flag.
  1094. * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
  1095. * @param DMAx DMAx Instance
  1096. * @retval State of bit (1 or 0).
  1097. */
  1098. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
  1099. {
  1100. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
  1101. }
  1102. /**
  1103. * @brief Get Channel 7 global interrupt flag.
  1104. * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
  1105. * @param DMAx DMAx Instance
  1106. * @retval State of bit (1 or 0).
  1107. */
  1108. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
  1109. {
  1110. return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
  1111. }
  1112. /**
  1113. * @brief Get Channel 1 transfer complete flag.
  1114. * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
  1115. * @param DMAx DMAx Instance
  1116. * @retval State of bit (1 or 0).
  1117. */
  1118. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
  1119. {
  1120. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
  1121. }
  1122. /**
  1123. * @brief Get Channel 2 transfer complete flag.
  1124. * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
  1125. * @param DMAx DMAx Instance
  1126. * @retval State of bit (1 or 0).
  1127. */
  1128. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
  1129. {
  1130. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
  1131. }
  1132. /**
  1133. * @brief Get Channel 3 transfer complete flag.
  1134. * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
  1135. * @param DMAx DMAx Instance
  1136. * @retval State of bit (1 or 0).
  1137. */
  1138. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
  1139. {
  1140. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
  1141. }
  1142. /**
  1143. * @brief Get Channel 4 transfer complete flag.
  1144. * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
  1145. * @param DMAx DMAx Instance
  1146. * @retval State of bit (1 or 0).
  1147. */
  1148. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
  1149. {
  1150. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
  1151. }
  1152. /**
  1153. * @brief Get Channel 5 transfer complete flag.
  1154. * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
  1155. * @param DMAx DMAx Instance
  1156. * @retval State of bit (1 or 0).
  1157. */
  1158. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
  1159. {
  1160. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
  1161. }
  1162. /**
  1163. * @brief Get Channel 6 transfer complete flag.
  1164. * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
  1165. * @param DMAx DMAx Instance
  1166. * @retval State of bit (1 or 0).
  1167. */
  1168. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
  1169. {
  1170. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
  1171. }
  1172. /**
  1173. * @brief Get Channel 7 transfer complete flag.
  1174. * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
  1175. * @param DMAx DMAx Instance
  1176. * @retval State of bit (1 or 0).
  1177. */
  1178. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
  1179. {
  1180. return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
  1181. }
  1182. /**
  1183. * @brief Get Channel 1 half transfer flag.
  1184. * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
  1185. * @param DMAx DMAx Instance
  1186. * @retval State of bit (1 or 0).
  1187. */
  1188. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
  1189. {
  1190. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
  1191. }
  1192. /**
  1193. * @brief Get Channel 2 half transfer flag.
  1194. * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
  1195. * @param DMAx DMAx Instance
  1196. * @retval State of bit (1 or 0).
  1197. */
  1198. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
  1199. {
  1200. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
  1201. }
  1202. /**
  1203. * @brief Get Channel 3 half transfer flag.
  1204. * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
  1205. * @param DMAx DMAx Instance
  1206. * @retval State of bit (1 or 0).
  1207. */
  1208. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
  1209. {
  1210. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
  1211. }
  1212. /**
  1213. * @brief Get Channel 4 half transfer flag.
  1214. * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
  1215. * @param DMAx DMAx Instance
  1216. * @retval State of bit (1 or 0).
  1217. */
  1218. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
  1219. {
  1220. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
  1221. }
  1222. /**
  1223. * @brief Get Channel 5 half transfer flag.
  1224. * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
  1225. * @param DMAx DMAx Instance
  1226. * @retval State of bit (1 or 0).
  1227. */
  1228. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
  1229. {
  1230. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
  1231. }
  1232. /**
  1233. * @brief Get Channel 6 half transfer flag.
  1234. * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
  1235. * @param DMAx DMAx Instance
  1236. * @retval State of bit (1 or 0).
  1237. */
  1238. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
  1239. {
  1240. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
  1241. }
  1242. /**
  1243. * @brief Get Channel 7 half transfer flag.
  1244. * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
  1245. * @param DMAx DMAx Instance
  1246. * @retval State of bit (1 or 0).
  1247. */
  1248. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
  1249. {
  1250. return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
  1251. }
  1252. /**
  1253. * @brief Get Channel 1 transfer error flag.
  1254. * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
  1255. * @param DMAx DMAx Instance
  1256. * @retval State of bit (1 or 0).
  1257. */
  1258. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
  1259. {
  1260. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
  1261. }
  1262. /**
  1263. * @brief Get Channel 2 transfer error flag.
  1264. * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
  1265. * @param DMAx DMAx Instance
  1266. * @retval State of bit (1 or 0).
  1267. */
  1268. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
  1269. {
  1270. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
  1271. }
  1272. /**
  1273. * @brief Get Channel 3 transfer error flag.
  1274. * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
  1275. * @param DMAx DMAx Instance
  1276. * @retval State of bit (1 or 0).
  1277. */
  1278. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
  1279. {
  1280. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
  1281. }
  1282. /**
  1283. * @brief Get Channel 4 transfer error flag.
  1284. * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
  1285. * @param DMAx DMAx Instance
  1286. * @retval State of bit (1 or 0).
  1287. */
  1288. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
  1289. {
  1290. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
  1291. }
  1292. /**
  1293. * @brief Get Channel 5 transfer error flag.
  1294. * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
  1295. * @param DMAx DMAx Instance
  1296. * @retval State of bit (1 or 0).
  1297. */
  1298. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
  1299. {
  1300. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
  1301. }
  1302. /**
  1303. * @brief Get Channel 6 transfer error flag.
  1304. * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
  1305. * @param DMAx DMAx Instance
  1306. * @retval State of bit (1 or 0).
  1307. */
  1308. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
  1309. {
  1310. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
  1311. }
  1312. /**
  1313. * @brief Get Channel 7 transfer error flag.
  1314. * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
  1315. * @param DMAx DMAx Instance
  1316. * @retval State of bit (1 or 0).
  1317. */
  1318. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
  1319. {
  1320. return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
  1321. }
  1322. /**
  1323. * @brief Clear Channel 1 global interrupt flag.
  1324. * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
  1325. * @param DMAx DMAx Instance
  1326. * @retval None
  1327. */
  1328. __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
  1329. {
  1330. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
  1331. }
  1332. /**
  1333. * @brief Clear Channel 2 global interrupt flag.
  1334. * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
  1335. * @param DMAx DMAx Instance
  1336. * @retval None
  1337. */
  1338. __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
  1339. {
  1340. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
  1341. }
  1342. /**
  1343. * @brief Clear Channel 3 global interrupt flag.
  1344. * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
  1345. * @param DMAx DMAx Instance
  1346. * @retval None
  1347. */
  1348. __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
  1349. {
  1350. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
  1351. }
  1352. /**
  1353. * @brief Clear Channel 4 global interrupt flag.
  1354. * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
  1355. * @param DMAx DMAx Instance
  1356. * @retval None
  1357. */
  1358. __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
  1359. {
  1360. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
  1361. }
  1362. /**
  1363. * @brief Clear Channel 5 global interrupt flag.
  1364. * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
  1365. * @param DMAx DMAx Instance
  1366. * @retval None
  1367. */
  1368. __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
  1369. {
  1370. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
  1371. }
  1372. /**
  1373. * @brief Clear Channel 6 global interrupt flag.
  1374. * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
  1375. * @param DMAx DMAx Instance
  1376. * @retval None
  1377. */
  1378. __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
  1379. {
  1380. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
  1381. }
  1382. /**
  1383. * @brief Clear Channel 7 global interrupt flag.
  1384. * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
  1385. * @param DMAx DMAx Instance
  1386. * @retval None
  1387. */
  1388. __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
  1389. {
  1390. WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
  1391. }
  1392. /**
  1393. * @brief Clear Channel 1 transfer complete flag.
  1394. * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
  1395. * @param DMAx DMAx Instance
  1396. * @retval None
  1397. */
  1398. __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
  1399. {
  1400. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
  1401. }
  1402. /**
  1403. * @brief Clear Channel 2 transfer complete flag.
  1404. * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
  1405. * @param DMAx DMAx Instance
  1406. * @retval None
  1407. */
  1408. __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
  1409. {
  1410. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
  1411. }
  1412. /**
  1413. * @brief Clear Channel 3 transfer complete flag.
  1414. * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
  1415. * @param DMAx DMAx Instance
  1416. * @retval None
  1417. */
  1418. __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
  1419. {
  1420. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
  1421. }
  1422. /**
  1423. * @brief Clear Channel 4 transfer complete flag.
  1424. * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
  1425. * @param DMAx DMAx Instance
  1426. * @retval None
  1427. */
  1428. __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
  1429. {
  1430. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
  1431. }
  1432. /**
  1433. * @brief Clear Channel 5 transfer complete flag.
  1434. * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
  1435. * @param DMAx DMAx Instance
  1436. * @retval None
  1437. */
  1438. __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
  1439. {
  1440. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
  1441. }
  1442. /**
  1443. * @brief Clear Channel 6 transfer complete flag.
  1444. * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
  1445. * @param DMAx DMAx Instance
  1446. * @retval None
  1447. */
  1448. __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
  1449. {
  1450. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
  1451. }
  1452. /**
  1453. * @brief Clear Channel 7 transfer complete flag.
  1454. * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
  1455. * @param DMAx DMAx Instance
  1456. * @retval None
  1457. */
  1458. __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
  1459. {
  1460. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
  1461. }
  1462. /**
  1463. * @brief Clear Channel 1 half transfer flag.
  1464. * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
  1465. * @param DMAx DMAx Instance
  1466. * @retval None
  1467. */
  1468. __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
  1469. {
  1470. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
  1471. }
  1472. /**
  1473. * @brief Clear Channel 2 half transfer flag.
  1474. * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
  1475. * @param DMAx DMAx Instance
  1476. * @retval None
  1477. */
  1478. __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
  1479. {
  1480. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
  1481. }
  1482. /**
  1483. * @brief Clear Channel 3 half transfer flag.
  1484. * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
  1485. * @param DMAx DMAx Instance
  1486. * @retval None
  1487. */
  1488. __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
  1489. {
  1490. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
  1491. }
  1492. /**
  1493. * @brief Clear Channel 4 half transfer flag.
  1494. * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
  1495. * @param DMAx DMAx Instance
  1496. * @retval None
  1497. */
  1498. __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
  1499. {
  1500. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
  1501. }
  1502. /**
  1503. * @brief Clear Channel 5 half transfer flag.
  1504. * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
  1505. * @param DMAx DMAx Instance
  1506. * @retval None
  1507. */
  1508. __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
  1509. {
  1510. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
  1511. }
  1512. /**
  1513. * @brief Clear Channel 6 half transfer flag.
  1514. * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
  1515. * @param DMAx DMAx Instance
  1516. * @retval None
  1517. */
  1518. __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
  1519. {
  1520. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
  1521. }
  1522. /**
  1523. * @brief Clear Channel 7 half transfer flag.
  1524. * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
  1525. * @param DMAx DMAx Instance
  1526. * @retval None
  1527. */
  1528. __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
  1529. {
  1530. WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
  1531. }
  1532. /**
  1533. * @brief Clear Channel 1 transfer error flag.
  1534. * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
  1535. * @param DMAx DMAx Instance
  1536. * @retval None
  1537. */
  1538. __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
  1539. {
  1540. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
  1541. }
  1542. /**
  1543. * @brief Clear Channel 2 transfer error flag.
  1544. * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
  1545. * @param DMAx DMAx Instance
  1546. * @retval None
  1547. */
  1548. __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
  1549. {
  1550. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
  1551. }
  1552. /**
  1553. * @brief Clear Channel 3 transfer error flag.
  1554. * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
  1555. * @param DMAx DMAx Instance
  1556. * @retval None
  1557. */
  1558. __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
  1559. {
  1560. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
  1561. }
  1562. /**
  1563. * @brief Clear Channel 4 transfer error flag.
  1564. * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
  1565. * @param DMAx DMAx Instance
  1566. * @retval None
  1567. */
  1568. __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
  1569. {
  1570. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
  1571. }
  1572. /**
  1573. * @brief Clear Channel 5 transfer error flag.
  1574. * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
  1575. * @param DMAx DMAx Instance
  1576. * @retval None
  1577. */
  1578. __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
  1579. {
  1580. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
  1581. }
  1582. /**
  1583. * @brief Clear Channel 6 transfer error flag.
  1584. * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
  1585. * @param DMAx DMAx Instance
  1586. * @retval None
  1587. */
  1588. __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
  1589. {
  1590. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
  1591. }
  1592. /**
  1593. * @brief Clear Channel 7 transfer error flag.
  1594. * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
  1595. * @param DMAx DMAx Instance
  1596. * @retval None
  1597. */
  1598. __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
  1599. {
  1600. WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
  1601. }
  1602. /**
  1603. * @}
  1604. */
  1605. /** @defgroup DMA_LL_EF_IT_Management IT_Management
  1606. * @{
  1607. */
  1608. /**
  1609. * @brief Enable Transfer complete interrupt.
  1610. * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
  1611. * @param DMAx DMAx Instance
  1612. * @param Channel This parameter can be one of the following values:
  1613. * @arg @ref LL_DMA_CHANNEL_1
  1614. * @arg @ref LL_DMA_CHANNEL_2
  1615. * @arg @ref LL_DMA_CHANNEL_3
  1616. * @arg @ref LL_DMA_CHANNEL_4
  1617. * @arg @ref LL_DMA_CHANNEL_5
  1618. * @arg @ref LL_DMA_CHANNEL_6
  1619. * @arg @ref LL_DMA_CHANNEL_7
  1620. * @retval None
  1621. */
  1622. __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1623. {
  1624. SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
  1625. }
  1626. /**
  1627. * @brief Enable Half transfer interrupt.
  1628. * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
  1629. * @param DMAx DMAx Instance
  1630. * @param Channel This parameter can be one of the following values:
  1631. * @arg @ref LL_DMA_CHANNEL_1
  1632. * @arg @ref LL_DMA_CHANNEL_2
  1633. * @arg @ref LL_DMA_CHANNEL_3
  1634. * @arg @ref LL_DMA_CHANNEL_4
  1635. * @arg @ref LL_DMA_CHANNEL_5
  1636. * @arg @ref LL_DMA_CHANNEL_6
  1637. * @arg @ref LL_DMA_CHANNEL_7
  1638. * @retval None
  1639. */
  1640. __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1641. {
  1642. SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
  1643. }
  1644. /**
  1645. * @brief Enable Transfer error interrupt.
  1646. * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
  1647. * @param DMAx DMAx Instance
  1648. * @param Channel This parameter can be one of the following values:
  1649. * @arg @ref LL_DMA_CHANNEL_1
  1650. * @arg @ref LL_DMA_CHANNEL_2
  1651. * @arg @ref LL_DMA_CHANNEL_3
  1652. * @arg @ref LL_DMA_CHANNEL_4
  1653. * @arg @ref LL_DMA_CHANNEL_5
  1654. * @arg @ref LL_DMA_CHANNEL_6
  1655. * @arg @ref LL_DMA_CHANNEL_7
  1656. * @retval None
  1657. */
  1658. __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1659. {
  1660. SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
  1661. }
  1662. /**
  1663. * @brief Disable Transfer complete interrupt.
  1664. * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
  1665. * @param DMAx DMAx Instance
  1666. * @param Channel This parameter can be one of the following values:
  1667. * @arg @ref LL_DMA_CHANNEL_1
  1668. * @arg @ref LL_DMA_CHANNEL_2
  1669. * @arg @ref LL_DMA_CHANNEL_3
  1670. * @arg @ref LL_DMA_CHANNEL_4
  1671. * @arg @ref LL_DMA_CHANNEL_5
  1672. * @arg @ref LL_DMA_CHANNEL_6
  1673. * @arg @ref LL_DMA_CHANNEL_7
  1674. * @retval None
  1675. */
  1676. __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1677. {
  1678. CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
  1679. }
  1680. /**
  1681. * @brief Disable Half transfer interrupt.
  1682. * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
  1683. * @param DMAx DMAx Instance
  1684. * @param Channel This parameter can be one of the following values:
  1685. * @arg @ref LL_DMA_CHANNEL_1
  1686. * @arg @ref LL_DMA_CHANNEL_2
  1687. * @arg @ref LL_DMA_CHANNEL_3
  1688. * @arg @ref LL_DMA_CHANNEL_4
  1689. * @arg @ref LL_DMA_CHANNEL_5
  1690. * @arg @ref LL_DMA_CHANNEL_6
  1691. * @arg @ref LL_DMA_CHANNEL_7
  1692. * @retval None
  1693. */
  1694. __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1695. {
  1696. CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
  1697. }
  1698. /**
  1699. * @brief Disable Transfer error interrupt.
  1700. * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
  1701. * @param DMAx DMAx Instance
  1702. * @param Channel This parameter can be one of the following values:
  1703. * @arg @ref LL_DMA_CHANNEL_1
  1704. * @arg @ref LL_DMA_CHANNEL_2
  1705. * @arg @ref LL_DMA_CHANNEL_3
  1706. * @arg @ref LL_DMA_CHANNEL_4
  1707. * @arg @ref LL_DMA_CHANNEL_5
  1708. * @arg @ref LL_DMA_CHANNEL_6
  1709. * @arg @ref LL_DMA_CHANNEL_7
  1710. * @retval None
  1711. */
  1712. __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1713. {
  1714. CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
  1715. }
  1716. /**
  1717. * @brief Check if Transfer complete Interrupt is enabled.
  1718. * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
  1719. * @param DMAx DMAx Instance
  1720. * @param Channel This parameter can be one of the following values:
  1721. * @arg @ref LL_DMA_CHANNEL_1
  1722. * @arg @ref LL_DMA_CHANNEL_2
  1723. * @arg @ref LL_DMA_CHANNEL_3
  1724. * @arg @ref LL_DMA_CHANNEL_4
  1725. * @arg @ref LL_DMA_CHANNEL_5
  1726. * @arg @ref LL_DMA_CHANNEL_6
  1727. * @arg @ref LL_DMA_CHANNEL_7
  1728. * @retval State of bit (1 or 0).
  1729. */
  1730. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1731. {
  1732. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1733. DMA_CCR_TCIE) == (DMA_CCR_TCIE));
  1734. }
  1735. /**
  1736. * @brief Check if Half transfer Interrupt is enabled.
  1737. * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
  1738. * @param DMAx DMAx Instance
  1739. * @param Channel This parameter can be one of the following values:
  1740. * @arg @ref LL_DMA_CHANNEL_1
  1741. * @arg @ref LL_DMA_CHANNEL_2
  1742. * @arg @ref LL_DMA_CHANNEL_3
  1743. * @arg @ref LL_DMA_CHANNEL_4
  1744. * @arg @ref LL_DMA_CHANNEL_5
  1745. * @arg @ref LL_DMA_CHANNEL_6
  1746. * @arg @ref LL_DMA_CHANNEL_7
  1747. * @retval State of bit (1 or 0).
  1748. */
  1749. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1750. {
  1751. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1752. DMA_CCR_HTIE) == (DMA_CCR_HTIE));
  1753. }
  1754. /**
  1755. * @brief Check if Transfer error Interrupt is enabled.
  1756. * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
  1757. * @param DMAx DMAx Instance
  1758. * @param Channel This parameter can be one of the following values:
  1759. * @arg @ref LL_DMA_CHANNEL_1
  1760. * @arg @ref LL_DMA_CHANNEL_2
  1761. * @arg @ref LL_DMA_CHANNEL_3
  1762. * @arg @ref LL_DMA_CHANNEL_4
  1763. * @arg @ref LL_DMA_CHANNEL_5
  1764. * @arg @ref LL_DMA_CHANNEL_6
  1765. * @arg @ref LL_DMA_CHANNEL_7
  1766. * @retval State of bit (1 or 0).
  1767. */
  1768. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1769. {
  1770. return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1771. DMA_CCR_TEIE) == (DMA_CCR_TEIE));
  1772. }
  1773. /**
  1774. * @}
  1775. */
  1776. #if defined(USE_FULL_LL_DRIVER)
  1777. /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
  1778. * @{
  1779. */
  1780. uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
  1781. uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
  1782. void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
  1783. /**
  1784. * @}
  1785. */
  1786. #endif /* USE_FULL_LL_DRIVER */
  1787. /**
  1788. * @}
  1789. */
  1790. /**
  1791. * @}
  1792. */
  1793. #endif /* DMA1 || DMA2 */
  1794. /**
  1795. * @}
  1796. */
  1797. #ifdef __cplusplus
  1798. }
  1799. #endif
  1800. #endif /* __STM32F1xx_LL_DMA_H */
  1801. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/