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stm32f1xx_ll_dac.h 61KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_dac.h
  4. * @author MCD Application Team
  5. * @brief Header file of DAC LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32F1xx_LL_DAC_H
  21. #define STM32F1xx_LL_DAC_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f1xx.h"
  27. /** @addtogroup STM32F1xx_LL_Driver
  28. * @{
  29. */
  30. #if defined(DAC)
  31. /** @defgroup DAC_LL DAC
  32. * @{
  33. */
  34. /* Private types -------------------------------------------------------------*/
  35. /* Private variables ---------------------------------------------------------*/
  36. /* Private constants ---------------------------------------------------------*/
  37. /** @defgroup DAC_LL_Private_Constants DAC Private Constants
  38. * @{
  39. */
  40. /* Internal masks for DAC channels definition */
  41. /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
  42. /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
  43. /* - channel bits position into register SWTRIG */
  44. /* - channel register offset of data holding register DHRx */
  45. /* - channel register offset of data output register DORx */
  46. #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
  47. #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
  48. #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
  49. #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
  50. #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
  51. #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
  52. #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
  53. #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  54. #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  55. #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
  56. #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  57. #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  58. #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
  59. #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
  60. #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
  61. #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
  62. #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
  63. #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
  64. #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
  65. #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
  66. #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
  67. #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
  68. #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
  69. #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  70. #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  71. #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
  72. /* DAC registers bits positions */
  73. #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
  74. #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
  75. #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
  76. /* Miscellaneous data */
  77. #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
  78. /**
  79. * @}
  80. */
  81. /* Private macros ------------------------------------------------------------*/
  82. /** @defgroup DAC_LL_Private_Macros DAC Private Macros
  83. * @{
  84. */
  85. /**
  86. * @brief Driver macro reserved for internal use: set a pointer to
  87. * a register from a register basis from which an offset
  88. * is applied.
  89. * @param __REG__ Register basis from which the offset is applied.
  90. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
  91. * @retval Pointer to register address
  92. */
  93. #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
  94. ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
  95. /**
  96. * @}
  97. */
  98. /* Exported types ------------------------------------------------------------*/
  99. #if defined(USE_FULL_LL_DRIVER)
  100. /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
  101. * @{
  102. */
  103. /**
  104. * @brief Structure definition of some features of DAC instance.
  105. */
  106. typedef struct
  107. {
  108. uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
  109. This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
  110. This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
  111. uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
  112. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
  113. This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
  114. uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
  115. If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
  116. If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
  117. @note If waveform automatic generation mode is disabled, this parameter is discarded.
  118. This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
  119. depending on the wave automatic generation selected. */
  120. uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
  121. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
  122. This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
  123. } LL_DAC_InitTypeDef;
  124. /**
  125. * @}
  126. */
  127. #endif /* USE_FULL_LL_DRIVER */
  128. /* Exported constants --------------------------------------------------------*/
  129. /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
  130. * @{
  131. */
  132. /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
  133. * @brief Flags defines which can be used with LL_DAC_ReadReg function
  134. * @{
  135. */
  136. /* DAC channel 1 flags */
  137. #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
  138. /* DAC channel 2 flags */
  139. #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
  140. /**
  141. * @}
  142. */
  143. /** @defgroup DAC_LL_EC_IT DAC interruptions
  144. * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
  145. * @{
  146. */
  147. #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
  148. #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
  149. /**
  150. * @}
  151. */
  152. /** @defgroup DAC_LL_EC_CHANNEL DAC channels
  153. * @{
  154. */
  155. #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
  156. #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
  157. /**
  158. * @}
  159. */
  160. /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
  161. * @{
  162. */
  163. #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
  164. #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
  165. #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
  166. #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
  167. #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
  168. #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
  169. #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
  170. #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
  171. #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
  172. #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
  173. /**
  174. * @}
  175. */
  176. /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
  177. * @{
  178. */
  179. #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
  180. #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
  181. #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
  182. /**
  183. * @}
  184. */
  185. /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
  186. * @{
  187. */
  188. #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
  189. #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
  190. #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
  191. #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
  192. #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
  193. #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
  194. #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
  195. #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
  196. #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
  197. #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
  198. #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
  199. #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
  200. /**
  201. * @}
  202. */
  203. /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
  204. * @{
  205. */
  206. #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
  207. #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
  208. #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
  209. #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
  210. #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
  211. #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
  212. #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
  213. #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
  214. #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
  215. #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
  216. #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
  217. #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
  218. /**
  219. * @}
  220. */
  221. /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
  222. * @{
  223. */
  224. #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
  225. #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
  226. /**
  227. * @}
  228. */
  229. /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
  230. * @{
  231. */
  232. #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
  233. #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
  234. /**
  235. * @}
  236. */
  237. /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
  238. * @{
  239. */
  240. /* List of DAC registers intended to be used (most commonly) with */
  241. /* DMA transfer. */
  242. /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
  243. #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
  244. #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
  245. #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
  246. /**
  247. * @}
  248. */
  249. /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
  250. * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
  251. * not timeout values.
  252. * For details on delays values, refer to descriptions in source code
  253. * above each literal definition.
  254. * @{
  255. */
  256. /* Delay for DAC channel voltage settling time from DAC channel startup */
  257. /* (transition from disable to enable). */
  258. /* Note: DAC channel startup time depends on board application environment: */
  259. /* impedance connected to DAC channel output. */
  260. /* The delay below is specified under conditions: */
  261. /* - voltage maximum transition (lowest to highest value) */
  262. /* - until voltage reaches final value +-1LSB */
  263. /* - DAC channel output buffer enabled */
  264. /* - load impedance of 5kOhm (min), 50pF (max) */
  265. /* Literal set to maximum value (refer to device datasheet, */
  266. /* parameter "tWAKEUP"). */
  267. /* Unit: us */
  268. #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
  269. /* Delay for DAC channel voltage settling time. */
  270. /* Note: DAC channel startup time depends on board application environment: */
  271. /* impedance connected to DAC channel output. */
  272. /* The delay below is specified under conditions: */
  273. /* - voltage maximum transition (lowest to highest value) */
  274. /* - until voltage reaches final value +-1LSB */
  275. /* - DAC channel output buffer enabled */
  276. /* - load impedance of 5kOhm min, 50pF max */
  277. /* Literal set to maximum value (refer to device datasheet, */
  278. /* parameter "tSETTLING"). */
  279. /* Unit: us */
  280. #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
  281. /**
  282. * @}
  283. */
  284. /**
  285. * @}
  286. */
  287. /* Exported macro ------------------------------------------------------------*/
  288. /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
  289. * @{
  290. */
  291. /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
  292. * @{
  293. */
  294. /**
  295. * @brief Write a value in DAC register
  296. * @param __INSTANCE__ DAC Instance
  297. * @param __REG__ Register to be written
  298. * @param __VALUE__ Value to be written in the register
  299. * @retval None
  300. */
  301. #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  302. /**
  303. * @brief Read a value in DAC register
  304. * @param __INSTANCE__ DAC Instance
  305. * @param __REG__ Register to be read
  306. * @retval Register value
  307. */
  308. #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  309. /**
  310. * @}
  311. */
  312. /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
  313. * @{
  314. */
  315. /**
  316. * @brief Helper macro to get DAC channel number in decimal format
  317. * from literals LL_DAC_CHANNEL_x.
  318. * Example:
  319. * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
  320. * will return decimal number "1".
  321. * @note The input can be a value from functions where a channel
  322. * number is returned.
  323. * @param __CHANNEL__ This parameter can be one of the following values:
  324. * @arg @ref LL_DAC_CHANNEL_1
  325. * @arg @ref LL_DAC_CHANNEL_2
  326. * @retval 1...2
  327. */
  328. #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
  329. ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
  330. /**
  331. * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
  332. * from number in decimal format.
  333. * Example:
  334. * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
  335. * will return a data equivalent to "LL_DAC_CHANNEL_1".
  336. * @note If the input parameter does not correspond to a DAC channel,
  337. * this macro returns value '0'.
  338. * @param __DECIMAL_NB__ 1...2
  339. * @retval Returned value can be one of the following values:
  340. * @arg @ref LL_DAC_CHANNEL_1
  341. * @arg @ref LL_DAC_CHANNEL_2
  342. */
  343. #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
  344. (((__DECIMAL_NB__) == 1U) \
  345. ? ( \
  346. LL_DAC_CHANNEL_1 \
  347. ) \
  348. : \
  349. (((__DECIMAL_NB__) == 2U) \
  350. ? ( \
  351. LL_DAC_CHANNEL_2 \
  352. ) \
  353. : \
  354. ( \
  355. 0U \
  356. ) \
  357. ) \
  358. )
  359. /**
  360. * @brief Helper macro to define the DAC conversion data full-scale digital
  361. * value corresponding to the selected DAC resolution.
  362. * @note DAC conversion data full-scale corresponds to voltage range
  363. * determined by analog voltage references Vref+ and Vref-
  364. * (refer to reference manual).
  365. * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
  366. * @arg @ref LL_DAC_RESOLUTION_12B
  367. * @arg @ref LL_DAC_RESOLUTION_8B
  368. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  369. */
  370. #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
  371. ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
  372. /**
  373. * @brief Helper macro to calculate the DAC conversion data (unit: digital
  374. * value) corresponding to a voltage (unit: mVolt).
  375. * @note This helper macro is intended to provide input data in voltage
  376. * rather than digital value,
  377. * to be used with LL DAC functions such as
  378. * @ref LL_DAC_ConvertData12RightAligned().
  379. * @note Analog reference voltage (Vref+) must be either known from
  380. * user board environment or can be calculated using ADC measurement
  381. * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
  382. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
  383. * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
  384. * (unit: mVolt).
  385. * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
  386. * @arg @ref LL_DAC_RESOLUTION_12B
  387. * @arg @ref LL_DAC_RESOLUTION_8B
  388. * @retval DAC conversion data (unit: digital value)
  389. */
  390. #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
  391. __DAC_VOLTAGE__,\
  392. __DAC_RESOLUTION__) \
  393. ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
  394. / (__VREFANALOG_VOLTAGE__) \
  395. )
  396. /**
  397. * @}
  398. */
  399. /**
  400. * @}
  401. */
  402. /* Exported functions --------------------------------------------------------*/
  403. /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
  404. * @{
  405. */
  406. /**
  407. * @brief Set the conversion trigger source for the selected DAC channel.
  408. * @note For conversion trigger source to be effective, DAC trigger
  409. * must be enabled using function @ref LL_DAC_EnableTrigger().
  410. * @note To set conversion trigger source, DAC channel must be disabled.
  411. * Otherwise, the setting is discarded.
  412. * @note Availability of parameters of trigger sources from timer
  413. * depends on timers availability on the selected device.
  414. * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
  415. * CR TSEL2 LL_DAC_SetTriggerSource
  416. * @param DACx DAC instance
  417. * @param DAC_Channel This parameter can be one of the following values:
  418. * @arg @ref LL_DAC_CHANNEL_1
  419. * @arg @ref LL_DAC_CHANNEL_2
  420. * @param TriggerSource This parameter can be one of the following values:
  421. * @arg @ref LL_DAC_TRIG_SOFTWARE
  422. * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
  423. * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
  424. * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
  425. * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
  426. * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
  427. * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
  428. * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
  429. * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
  430. * @retval None
  431. */
  432. __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
  433. {
  434. MODIFY_REG(DACx->CR,
  435. DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  436. TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  437. }
  438. /**
  439. * @brief Get the conversion trigger source for the selected DAC channel.
  440. * @note For conversion trigger source to be effective, DAC trigger
  441. * must be enabled using function @ref LL_DAC_EnableTrigger().
  442. * @note Availability of parameters of trigger sources from timer
  443. * depends on timers availability on the selected device.
  444. * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
  445. * CR TSEL2 LL_DAC_GetTriggerSource
  446. * @param DACx DAC instance
  447. * @param DAC_Channel This parameter can be one of the following values:
  448. * @arg @ref LL_DAC_CHANNEL_1
  449. * @arg @ref LL_DAC_CHANNEL_2
  450. * @retval Returned value can be one of the following values:
  451. * @arg @ref LL_DAC_TRIG_SOFTWARE
  452. * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
  453. * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
  454. * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
  455. * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
  456. * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
  457. * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
  458. * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
  459. * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
  460. */
  461. __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  462. {
  463. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  464. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  465. );
  466. }
  467. /**
  468. * @brief Set the waveform automatic generation mode
  469. * for the selected DAC channel.
  470. * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
  471. * CR WAVE2 LL_DAC_SetWaveAutoGeneration
  472. * @param DACx DAC instance
  473. * @param DAC_Channel This parameter can be one of the following values:
  474. * @arg @ref LL_DAC_CHANNEL_1
  475. * @arg @ref LL_DAC_CHANNEL_2
  476. * @param WaveAutoGeneration This parameter can be one of the following values:
  477. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
  478. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
  479. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  480. * @retval None
  481. */
  482. __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
  483. {
  484. MODIFY_REG(DACx->CR,
  485. DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  486. WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  487. }
  488. /**
  489. * @brief Get the waveform automatic generation mode
  490. * for the selected DAC channel.
  491. * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
  492. * CR WAVE2 LL_DAC_GetWaveAutoGeneration
  493. * @param DACx DAC instance
  494. * @param DAC_Channel This parameter can be one of the following values:
  495. * @arg @ref LL_DAC_CHANNEL_1
  496. * @arg @ref LL_DAC_CHANNEL_2
  497. * @retval Returned value can be one of the following values:
  498. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
  499. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
  500. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  501. */
  502. __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  503. {
  504. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  505. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  506. );
  507. }
  508. /**
  509. * @brief Set the noise waveform generation for the selected DAC channel:
  510. * Noise mode and parameters LFSR (linear feedback shift register).
  511. * @note For wave generation to be effective, DAC channel
  512. * wave generation mode must be enabled using
  513. * function @ref LL_DAC_SetWaveAutoGeneration().
  514. * @note This setting can be set when the selected DAC channel is disabled
  515. * (otherwise, the setting operation is ignored).
  516. * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
  517. * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
  518. * @param DACx DAC instance
  519. * @param DAC_Channel This parameter can be one of the following values:
  520. * @arg @ref LL_DAC_CHANNEL_1
  521. * @arg @ref LL_DAC_CHANNEL_2
  522. * @param NoiseLFSRMask This parameter can be one of the following values:
  523. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
  524. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  525. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  526. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  527. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  528. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  529. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  530. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  531. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  532. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  533. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  534. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
  535. * @retval None
  536. */
  537. __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
  538. {
  539. MODIFY_REG(DACx->CR,
  540. DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  541. NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  542. }
  543. /**
  544. * @brief Get the noise waveform generation for the selected DAC channel:
  545. * Noise mode and parameters LFSR (linear feedback shift register).
  546. * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
  547. * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
  548. * @param DACx DAC instance
  549. * @param DAC_Channel This parameter can be one of the following values:
  550. * @arg @ref LL_DAC_CHANNEL_1
  551. * @arg @ref LL_DAC_CHANNEL_2
  552. * @retval Returned value can be one of the following values:
  553. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
  554. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  555. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  556. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  557. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  558. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  559. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  560. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  561. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  562. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  563. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  564. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
  565. */
  566. __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  567. {
  568. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  569. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  570. );
  571. }
  572. /**
  573. * @brief Set the triangle waveform generation for the selected DAC channel:
  574. * triangle mode and amplitude.
  575. * @note For wave generation to be effective, DAC channel
  576. * wave generation mode must be enabled using
  577. * function @ref LL_DAC_SetWaveAutoGeneration().
  578. * @note This setting can be set when the selected DAC channel is disabled
  579. * (otherwise, the setting operation is ignored).
  580. * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
  581. * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
  582. * @param DACx DAC instance
  583. * @param DAC_Channel This parameter can be one of the following values:
  584. * @arg @ref LL_DAC_CHANNEL_1
  585. * @arg @ref LL_DAC_CHANNEL_2
  586. * @param TriangleAmplitude This parameter can be one of the following values:
  587. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
  588. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
  589. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
  590. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
  591. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
  592. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
  593. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
  594. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
  595. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
  596. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
  597. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
  598. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
  599. * @retval None
  600. */
  601. __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
  602. uint32_t TriangleAmplitude)
  603. {
  604. MODIFY_REG(DACx->CR,
  605. DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  606. TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  607. }
  608. /**
  609. * @brief Get the triangle waveform generation for the selected DAC channel:
  610. * triangle mode and amplitude.
  611. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
  612. * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
  613. * @param DACx DAC instance
  614. * @param DAC_Channel This parameter can be one of the following values:
  615. * @arg @ref LL_DAC_CHANNEL_1
  616. * @arg @ref LL_DAC_CHANNEL_2
  617. * @retval Returned value can be one of the following values:
  618. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
  619. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
  620. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
  621. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
  622. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
  623. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
  624. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
  625. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
  626. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
  627. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
  628. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
  629. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
  630. */
  631. __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  632. {
  633. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  634. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  635. );
  636. }
  637. /**
  638. * @brief Set the output buffer for the selected DAC channel.
  639. * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
  640. * CR BOFF2 LL_DAC_SetOutputBuffer
  641. * @param DACx DAC instance
  642. * @param DAC_Channel This parameter can be one of the following values:
  643. * @arg @ref LL_DAC_CHANNEL_1
  644. * @arg @ref LL_DAC_CHANNEL_2
  645. * @param OutputBuffer This parameter can be one of the following values:
  646. * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
  647. * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
  648. * @retval None
  649. */
  650. __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
  651. {
  652. MODIFY_REG(DACx->CR,
  653. DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  654. OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  655. }
  656. /**
  657. * @brief Get the output buffer state for the selected DAC channel.
  658. * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
  659. * CR BOFF2 LL_DAC_GetOutputBuffer
  660. * @param DACx DAC instance
  661. * @param DAC_Channel This parameter can be one of the following values:
  662. * @arg @ref LL_DAC_CHANNEL_1
  663. * @arg @ref LL_DAC_CHANNEL_2
  664. * @retval Returned value can be one of the following values:
  665. * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
  666. * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
  667. */
  668. __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  669. {
  670. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  671. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  672. );
  673. }
  674. /**
  675. * @}
  676. */
  677. /** @defgroup DAC_LL_EF_DMA_Management DMA Management
  678. * @{
  679. */
  680. /**
  681. * @brief Enable DAC DMA transfer request of the selected channel.
  682. * @note To configure DMA source address (peripheral address),
  683. * use function @ref LL_DAC_DMA_GetRegAddr().
  684. * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
  685. * CR DMAEN2 LL_DAC_EnableDMAReq
  686. * @param DACx DAC instance
  687. * @param DAC_Channel This parameter can be one of the following values:
  688. * @arg @ref LL_DAC_CHANNEL_1
  689. * @arg @ref LL_DAC_CHANNEL_2
  690. * @retval None
  691. */
  692. __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  693. {
  694. SET_BIT(DACx->CR,
  695. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  696. }
  697. /**
  698. * @brief Disable DAC DMA transfer request of the selected channel.
  699. * @note To configure DMA source address (peripheral address),
  700. * use function @ref LL_DAC_DMA_GetRegAddr().
  701. * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
  702. * CR DMAEN2 LL_DAC_DisableDMAReq
  703. * @param DACx DAC instance
  704. * @param DAC_Channel This parameter can be one of the following values:
  705. * @arg @ref LL_DAC_CHANNEL_1
  706. * @arg @ref LL_DAC_CHANNEL_2
  707. * @retval None
  708. */
  709. __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  710. {
  711. CLEAR_BIT(DACx->CR,
  712. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  713. }
  714. /**
  715. * @brief Get DAC DMA transfer request state of the selected channel.
  716. * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
  717. * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
  718. * CR DMAEN2 LL_DAC_IsDMAReqEnabled
  719. * @param DACx DAC instance
  720. * @param DAC_Channel This parameter can be one of the following values:
  721. * @arg @ref LL_DAC_CHANNEL_1
  722. * @arg @ref LL_DAC_CHANNEL_2
  723. * @retval State of bit (1 or 0).
  724. */
  725. __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  726. {
  727. return ((READ_BIT(DACx->CR,
  728. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  729. == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
  730. }
  731. /**
  732. * @brief Function to help to configure DMA transfer to DAC: retrieve the
  733. * DAC register address from DAC instance and a list of DAC registers
  734. * intended to be used (most commonly) with DMA transfer.
  735. * @note These DAC registers are data holding registers:
  736. * when DAC conversion is requested, DAC generates a DMA transfer
  737. * request to have data available in DAC data holding registers.
  738. * @note This macro is intended to be used with LL DMA driver, refer to
  739. * function "LL_DMA_ConfigAddresses()".
  740. * Example:
  741. * LL_DMA_ConfigAddresses(DMA1,
  742. * LL_DMA_CHANNEL_1,
  743. * (uint32_t)&< array or variable >,
  744. * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
  745. * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
  746. * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  747. * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  748. * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  749. * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
  750. * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
  751. * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
  752. * @param DACx DAC instance
  753. * @param DAC_Channel This parameter can be one of the following values:
  754. * @arg @ref LL_DAC_CHANNEL_1
  755. * @arg @ref LL_DAC_CHANNEL_2
  756. * @param Register This parameter can be one of the following values:
  757. * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  758. * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  759. * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
  760. * @retval DAC register address
  761. */
  762. __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
  763. {
  764. /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
  765. /* DAC channel selected. */
  766. return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
  767. ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
  768. }
  769. /**
  770. * @}
  771. */
  772. /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
  773. * @{
  774. */
  775. /**
  776. * @brief Enable DAC selected channel.
  777. * @rmtoll CR EN1 LL_DAC_Enable\n
  778. * CR EN2 LL_DAC_Enable
  779. * @note After enable from off state, DAC channel requires a delay
  780. * for output voltage to reach accuracy +/- 1 LSB.
  781. * Refer to device datasheet, parameter "tWAKEUP".
  782. * @param DACx DAC instance
  783. * @param DAC_Channel This parameter can be one of the following values:
  784. * @arg @ref LL_DAC_CHANNEL_1
  785. * @arg @ref LL_DAC_CHANNEL_2
  786. * @retval None
  787. */
  788. __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  789. {
  790. SET_BIT(DACx->CR,
  791. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  792. }
  793. /**
  794. * @brief Disable DAC selected channel.
  795. * @rmtoll CR EN1 LL_DAC_Disable\n
  796. * CR EN2 LL_DAC_Disable
  797. * @param DACx DAC instance
  798. * @param DAC_Channel This parameter can be one of the following values:
  799. * @arg @ref LL_DAC_CHANNEL_1
  800. * @arg @ref LL_DAC_CHANNEL_2
  801. * @retval None
  802. */
  803. __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  804. {
  805. CLEAR_BIT(DACx->CR,
  806. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  807. }
  808. /**
  809. * @brief Get DAC enable state of the selected channel.
  810. * (0: DAC channel is disabled, 1: DAC channel is enabled)
  811. * @rmtoll CR EN1 LL_DAC_IsEnabled\n
  812. * CR EN2 LL_DAC_IsEnabled
  813. * @param DACx DAC instance
  814. * @param DAC_Channel This parameter can be one of the following values:
  815. * @arg @ref LL_DAC_CHANNEL_1
  816. * @arg @ref LL_DAC_CHANNEL_2
  817. * @retval State of bit (1 or 0).
  818. */
  819. __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  820. {
  821. return ((READ_BIT(DACx->CR,
  822. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  823. == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
  824. }
  825. /**
  826. * @brief Enable DAC trigger of the selected channel.
  827. * @note - If DAC trigger is disabled, DAC conversion is performed
  828. * automatically once the data holding register is updated,
  829. * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
  830. * @ref LL_DAC_ConvertData12RightAligned(), ...
  831. * - If DAC trigger is enabled, DAC conversion is performed
  832. * only when a hardware of software trigger event is occurring.
  833. * Select trigger source using
  834. * function @ref LL_DAC_SetTriggerSource().
  835. * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
  836. * CR TEN2 LL_DAC_EnableTrigger
  837. * @param DACx DAC instance
  838. * @param DAC_Channel This parameter can be one of the following values:
  839. * @arg @ref LL_DAC_CHANNEL_1
  840. * @arg @ref LL_DAC_CHANNEL_2
  841. * @retval None
  842. */
  843. __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  844. {
  845. SET_BIT(DACx->CR,
  846. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  847. }
  848. /**
  849. * @brief Disable DAC trigger of the selected channel.
  850. * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
  851. * CR TEN2 LL_DAC_DisableTrigger
  852. * @param DACx DAC instance
  853. * @param DAC_Channel This parameter can be one of the following values:
  854. * @arg @ref LL_DAC_CHANNEL_1
  855. * @arg @ref LL_DAC_CHANNEL_2
  856. * @retval None
  857. */
  858. __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  859. {
  860. CLEAR_BIT(DACx->CR,
  861. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  862. }
  863. /**
  864. * @brief Get DAC trigger state of the selected channel.
  865. * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
  866. * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
  867. * CR TEN2 LL_DAC_IsTriggerEnabled
  868. * @param DACx DAC instance
  869. * @param DAC_Channel This parameter can be one of the following values:
  870. * @arg @ref LL_DAC_CHANNEL_1
  871. * @arg @ref LL_DAC_CHANNEL_2
  872. * @retval State of bit (1 or 0).
  873. */
  874. __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  875. {
  876. return ((READ_BIT(DACx->CR,
  877. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  878. == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
  879. }
  880. /**
  881. * @brief Trig DAC conversion by software for the selected DAC channel.
  882. * @note Preliminarily, DAC trigger must be set to software trigger
  883. * using function
  884. * @ref LL_DAC_Init()
  885. * @ref LL_DAC_SetTriggerSource()
  886. * with parameter "LL_DAC_TRIGGER_SOFTWARE".
  887. * and DAC trigger must be enabled using
  888. * function @ref LL_DAC_EnableTrigger().
  889. * @note For devices featuring DAC with 2 channels: this function
  890. * can perform a SW start of both DAC channels simultaneously.
  891. * Two channels can be selected as parameter.
  892. * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
  893. * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
  894. * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
  895. * @param DACx DAC instance
  896. * @param DAC_Channel This parameter can a combination of the following values:
  897. * @arg @ref LL_DAC_CHANNEL_1
  898. * @arg @ref LL_DAC_CHANNEL_2
  899. * @retval None
  900. */
  901. __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  902. {
  903. SET_BIT(DACx->SWTRIGR,
  904. (DAC_Channel & DAC_SWTR_CHX_MASK));
  905. }
  906. /**
  907. * @brief Set the data to be loaded in the data holding register
  908. * in format 12 bits left alignment (LSB aligned on bit 0),
  909. * for the selected DAC channel.
  910. * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
  911. * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
  912. * @param DACx DAC instance
  913. * @param DAC_Channel This parameter can be one of the following values:
  914. * @arg @ref LL_DAC_CHANNEL_1
  915. * @arg @ref LL_DAC_CHANNEL_2
  916. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
  917. * @retval None
  918. */
  919. __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  920. {
  921. __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
  922. MODIFY_REG(*preg,
  923. DAC_DHR12R1_DACC1DHR,
  924. Data);
  925. }
  926. /**
  927. * @brief Set the data to be loaded in the data holding register
  928. * in format 12 bits left alignment (MSB aligned on bit 15),
  929. * for the selected DAC channel.
  930. * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
  931. * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
  932. * @param DACx DAC instance
  933. * @param DAC_Channel This parameter can be one of the following values:
  934. * @arg @ref LL_DAC_CHANNEL_1
  935. * @arg @ref LL_DAC_CHANNEL_2
  936. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
  937. * @retval None
  938. */
  939. __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  940. {
  941. __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
  942. MODIFY_REG(*preg,
  943. DAC_DHR12L1_DACC1DHR,
  944. Data);
  945. }
  946. /**
  947. * @brief Set the data to be loaded in the data holding register
  948. * in format 8 bits left alignment (LSB aligned on bit 0),
  949. * for the selected DAC channel.
  950. * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
  951. * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
  952. * @param DACx DAC instance
  953. * @param DAC_Channel This parameter can be one of the following values:
  954. * @arg @ref LL_DAC_CHANNEL_1
  955. * @arg @ref LL_DAC_CHANNEL_2
  956. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
  957. * @retval None
  958. */
  959. __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  960. {
  961. __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
  962. MODIFY_REG(*preg,
  963. DAC_DHR8R1_DACC1DHR,
  964. Data);
  965. }
  966. /**
  967. * @brief Set the data to be loaded in the data holding register
  968. * in format 12 bits left alignment (LSB aligned on bit 0),
  969. * for both DAC channels.
  970. * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
  971. * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
  972. * @param DACx DAC instance
  973. * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
  974. * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
  975. * @retval None
  976. */
  977. __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
  978. uint32_t DataChannel2)
  979. {
  980. MODIFY_REG(DACx->DHR12RD,
  981. (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
  982. ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
  983. }
  984. /**
  985. * @brief Set the data to be loaded in the data holding register
  986. * in format 12 bits left alignment (MSB aligned on bit 15),
  987. * for both DAC channels.
  988. * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
  989. * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
  990. * @param DACx DAC instance
  991. * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
  992. * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
  993. * @retval None
  994. */
  995. __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
  996. uint32_t DataChannel2)
  997. {
  998. /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
  999. /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
  1000. /* the 4 LSB must be taken into account for the shift value. */
  1001. MODIFY_REG(DACx->DHR12LD,
  1002. (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
  1003. ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
  1004. }
  1005. /**
  1006. * @brief Set the data to be loaded in the data holding register
  1007. * in format 8 bits left alignment (LSB aligned on bit 0),
  1008. * for both DAC channels.
  1009. * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
  1010. * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
  1011. * @param DACx DAC instance
  1012. * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
  1013. * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
  1014. * @retval None
  1015. */
  1016. __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
  1017. uint32_t DataChannel2)
  1018. {
  1019. MODIFY_REG(DACx->DHR8RD,
  1020. (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
  1021. ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
  1022. }
  1023. /**
  1024. * @brief Retrieve output data currently generated for the selected DAC channel.
  1025. * @note Whatever alignment and resolution settings
  1026. * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
  1027. * @ref LL_DAC_ConvertData12RightAligned(), ...),
  1028. * output data format is 12 bits right aligned (LSB aligned on bit 0).
  1029. * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
  1030. * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
  1031. * @param DACx DAC instance
  1032. * @param DAC_Channel This parameter can be one of the following values:
  1033. * @arg @ref LL_DAC_CHANNEL_1
  1034. * @arg @ref LL_DAC_CHANNEL_2
  1035. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1036. */
  1037. __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  1038. {
  1039. __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
  1040. return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
  1041. }
  1042. /**
  1043. * @}
  1044. */
  1045. /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
  1046. * @{
  1047. */
  1048. #if defined(DAC_SR_DMAUDR1)
  1049. /**
  1050. * @brief Get DAC underrun flag for DAC channel 1
  1051. * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
  1052. * @param DACx DAC instance
  1053. * @retval State of bit (1 or 0).
  1054. */
  1055. __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
  1056. {
  1057. return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
  1058. }
  1059. #endif /* DAC_SR_DMAUDR1 */
  1060. #if defined(DAC_SR_DMAUDR2)
  1061. /**
  1062. * @brief Get DAC underrun flag for DAC channel 2
  1063. * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
  1064. * @param DACx DAC instance
  1065. * @retval State of bit (1 or 0).
  1066. */
  1067. __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
  1068. {
  1069. return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
  1070. }
  1071. #endif /* DAC_SR_DMAUDR2 */
  1072. #if defined(DAC_SR_DMAUDR1)
  1073. /**
  1074. * @brief Clear DAC underrun flag for DAC channel 1
  1075. * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
  1076. * @param DACx DAC instance
  1077. * @retval None
  1078. */
  1079. __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
  1080. {
  1081. WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
  1082. }
  1083. #endif /* DAC_SR_DMAUDR1 */
  1084. #if defined(DAC_SR_DMAUDR2)
  1085. /**
  1086. * @brief Clear DAC underrun flag for DAC channel 2
  1087. * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
  1088. * @param DACx DAC instance
  1089. * @retval None
  1090. */
  1091. __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
  1092. {
  1093. WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
  1094. }
  1095. #endif /* DAC_SR_DMAUDR2 */
  1096. /**
  1097. * @}
  1098. */
  1099. /** @defgroup DAC_LL_EF_IT_Management IT management
  1100. * @{
  1101. */
  1102. #if defined(DAC_CR_DMAUDRIE1)
  1103. /**
  1104. * @brief Enable DMA underrun interrupt for DAC channel 1
  1105. * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
  1106. * @param DACx DAC instance
  1107. * @retval None
  1108. */
  1109. __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
  1110. {
  1111. SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
  1112. }
  1113. #endif /* DAC_CR_DMAUDRIE1 */
  1114. #if defined(DAC_CR_DMAUDRIE2)
  1115. /**
  1116. * @brief Enable DMA underrun interrupt for DAC channel 2
  1117. * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
  1118. * @param DACx DAC instance
  1119. * @retval None
  1120. */
  1121. __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
  1122. {
  1123. SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
  1124. }
  1125. #endif /* DAC_CR_DMAUDRIE2 */
  1126. #if defined(DAC_CR_DMAUDRIE1)
  1127. /**
  1128. * @brief Disable DMA underrun interrupt for DAC channel 1
  1129. * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
  1130. * @param DACx DAC instance
  1131. * @retval None
  1132. */
  1133. __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
  1134. {
  1135. CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
  1136. }
  1137. #endif /* DAC_CR_DMAUDRIE1 */
  1138. #if defined(DAC_CR_DMAUDRIE2)
  1139. /**
  1140. * @brief Disable DMA underrun interrupt for DAC channel 2
  1141. * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
  1142. * @param DACx DAC instance
  1143. * @retval None
  1144. */
  1145. __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
  1146. {
  1147. CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
  1148. }
  1149. #endif /* DAC_CR_DMAUDRIE2 */
  1150. #if defined(DAC_CR_DMAUDRIE1)
  1151. /**
  1152. * @brief Get DMA underrun interrupt for DAC channel 1
  1153. * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
  1154. * @param DACx DAC instance
  1155. * @retval State of bit (1 or 0).
  1156. */
  1157. __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
  1158. {
  1159. return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
  1160. }
  1161. #endif /* DAC_CR_DMAUDRIE1 */
  1162. #if defined(DAC_CR_DMAUDRIE2)
  1163. /**
  1164. * @brief Get DMA underrun interrupt for DAC channel 2
  1165. * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
  1166. * @param DACx DAC instance
  1167. * @retval State of bit (1 or 0).
  1168. */
  1169. __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
  1170. {
  1171. return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
  1172. }
  1173. #endif /* DAC_CR_DMAUDRIE2 */
  1174. /**
  1175. * @}
  1176. */
  1177. #if defined(USE_FULL_LL_DRIVER)
  1178. /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
  1179. * @{
  1180. */
  1181. ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
  1182. ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
  1183. void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
  1184. /**
  1185. * @}
  1186. */
  1187. #endif /* USE_FULL_LL_DRIVER */
  1188. /**
  1189. * @}
  1190. */
  1191. /**
  1192. * @}
  1193. */
  1194. #endif /* DAC */
  1195. /**
  1196. * @}
  1197. */
  1198. #ifdef __cplusplus
  1199. }
  1200. #endif
  1201. #endif /* STM32F1xx_LL_DAC_H */
  1202. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/