Projet voilier 4IRA1 Arnaud Vergnet Marino Benassai Bastien Picco Yohan Simard
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

stm32f1xx_ll_cortex.h 24KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640
  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_cortex.h
  4. * @author MCD Application Team
  5. * @brief Header file of CORTEX LL module.
  6. @verbatim
  7. ==============================================================================
  8. ##### How to use this driver #####
  9. ==============================================================================
  10. [..]
  11. The LL CORTEX driver contains a set of generic APIs that can be
  12. used by user:
  13. (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
  14. functions
  15. (+) Low power mode configuration (SCB register of Cortex-MCU)
  16. (+) MPU API to configure and enable regions
  17. (MPU services provided only on some devices)
  18. (+) API to access to MCU info (CPUID register)
  19. (+) API to enable fault handler (SHCSR accesses)
  20. @endverbatim
  21. ******************************************************************************
  22. * @attention
  23. *
  24. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  25. * All rights reserved.</center></h2>
  26. *
  27. * This software component is licensed by ST under BSD 3-Clause license,
  28. * the "License"; You may not use this file except in compliance with the
  29. * License. You may obtain a copy of the License at:
  30. * opensource.org/licenses/BSD-3-Clause
  31. *
  32. ******************************************************************************
  33. */
  34. /* Define to prevent recursive inclusion -------------------------------------*/
  35. #ifndef __STM32F1xx_LL_CORTEX_H
  36. #define __STM32F1xx_LL_CORTEX_H
  37. #ifdef __cplusplus
  38. extern "C" {
  39. #endif
  40. /* Includes ------------------------------------------------------------------*/
  41. #include "stm32f1xx.h"
  42. /** @addtogroup STM32F1xx_LL_Driver
  43. * @{
  44. */
  45. /** @defgroup CORTEX_LL CORTEX
  46. * @{
  47. */
  48. /* Private types -------------------------------------------------------------*/
  49. /* Private variables ---------------------------------------------------------*/
  50. /* Private constants ---------------------------------------------------------*/
  51. /* Private macros ------------------------------------------------------------*/
  52. /* Exported types ------------------------------------------------------------*/
  53. /* Exported constants --------------------------------------------------------*/
  54. /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
  55. * @{
  56. */
  57. /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
  58. * @{
  59. */
  60. #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
  61. #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
  62. /**
  63. * @}
  64. */
  65. /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
  66. * @{
  67. */
  68. #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
  69. #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
  70. #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
  71. /**
  72. * @}
  73. */
  74. #if __MPU_PRESENT
  75. /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
  76. * @{
  77. */
  78. #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
  79. #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
  80. #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
  81. #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
  82. /**
  83. * @}
  84. */
  85. /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
  86. * @{
  87. */
  88. #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
  89. #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
  90. #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
  91. #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
  92. #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
  93. #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
  94. #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
  95. #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
  96. /**
  97. * @}
  98. */
  99. /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
  100. * @{
  101. */
  102. #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
  103. #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
  104. #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
  105. #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
  106. #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
  107. #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
  108. #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
  109. #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
  110. #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
  111. #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
  112. #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
  113. #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
  114. #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
  115. #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
  116. #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
  117. #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
  118. #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
  119. #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
  120. #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
  121. #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
  122. #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
  123. #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
  124. #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
  125. #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
  126. #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
  127. #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
  128. #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
  129. #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
  130. /**
  131. * @}
  132. */
  133. /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
  134. * @{
  135. */
  136. #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
  137. #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
  138. #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
  139. #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
  140. #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
  141. #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
  142. /**
  143. * @}
  144. */
  145. /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
  146. * @{
  147. */
  148. #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
  149. #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
  150. #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
  151. #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
  152. /**
  153. * @}
  154. */
  155. /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
  156. * @{
  157. */
  158. #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
  159. #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
  160. /**
  161. * @}
  162. */
  163. /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
  164. * @{
  165. */
  166. #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
  167. #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
  168. /**
  169. * @}
  170. */
  171. /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
  172. * @{
  173. */
  174. #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
  175. #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
  176. /**
  177. * @}
  178. */
  179. /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
  180. * @{
  181. */
  182. #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
  183. #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
  184. /**
  185. * @}
  186. */
  187. #endif /* __MPU_PRESENT */
  188. /**
  189. * @}
  190. */
  191. /* Exported macro ------------------------------------------------------------*/
  192. /* Exported functions --------------------------------------------------------*/
  193. /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
  194. * @{
  195. */
  196. /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
  197. * @{
  198. */
  199. /**
  200. * @brief This function checks if the Systick counter flag is active or not.
  201. * @note It can be used in timeout function on application side.
  202. * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
  203. * @retval State of bit (1 or 0).
  204. */
  205. __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
  206. {
  207. return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
  208. }
  209. /**
  210. * @brief Configures the SysTick clock source
  211. * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
  212. * @param Source This parameter can be one of the following values:
  213. * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  214. * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
  215. * @retval None
  216. */
  217. __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
  218. {
  219. if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
  220. {
  221. SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
  222. }
  223. else
  224. {
  225. CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
  226. }
  227. }
  228. /**
  229. * @brief Get the SysTick clock source
  230. * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
  231. * @retval Returned value can be one of the following values:
  232. * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  233. * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
  234. */
  235. __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
  236. {
  237. return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
  238. }
  239. /**
  240. * @brief Enable SysTick exception request
  241. * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
  242. * @retval None
  243. */
  244. __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
  245. {
  246. SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
  247. }
  248. /**
  249. * @brief Disable SysTick exception request
  250. * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
  251. * @retval None
  252. */
  253. __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
  254. {
  255. CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
  256. }
  257. /**
  258. * @brief Checks if the SYSTICK interrupt is enabled or disabled.
  259. * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
  260. * @retval State of bit (1 or 0).
  261. */
  262. __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
  263. {
  264. return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
  265. }
  266. /**
  267. * @}
  268. */
  269. /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
  270. * @{
  271. */
  272. /**
  273. * @brief Processor uses sleep as its low power mode
  274. * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
  275. * @retval None
  276. */
  277. __STATIC_INLINE void LL_LPM_EnableSleep(void)
  278. {
  279. /* Clear SLEEPDEEP bit of Cortex System Control Register */
  280. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  281. }
  282. /**
  283. * @brief Processor uses deep sleep as its low power mode
  284. * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
  285. * @retval None
  286. */
  287. __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
  288. {
  289. /* Set SLEEPDEEP bit of Cortex System Control Register */
  290. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  291. }
  292. /**
  293. * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
  294. * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
  295. * empty main application.
  296. * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
  297. * @retval None
  298. */
  299. __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
  300. {
  301. /* Set SLEEPONEXIT bit of Cortex System Control Register */
  302. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  303. }
  304. /**
  305. * @brief Do not sleep when returning to Thread mode.
  306. * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
  307. * @retval None
  308. */
  309. __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
  310. {
  311. /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  312. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  313. }
  314. /**
  315. * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
  316. * processor.
  317. * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
  318. * @retval None
  319. */
  320. __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
  321. {
  322. /* Set SEVEONPEND bit of Cortex System Control Register */
  323. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  324. }
  325. /**
  326. * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
  327. * excluded
  328. * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
  329. * @retval None
  330. */
  331. __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
  332. {
  333. /* Clear SEVEONPEND bit of Cortex System Control Register */
  334. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  335. }
  336. /**
  337. * @}
  338. */
  339. /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
  340. * @{
  341. */
  342. /**
  343. * @brief Enable a fault in System handler control register (SHCSR)
  344. * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
  345. * @param Fault This parameter can be a combination of the following values:
  346. * @arg @ref LL_HANDLER_FAULT_USG
  347. * @arg @ref LL_HANDLER_FAULT_BUS
  348. * @arg @ref LL_HANDLER_FAULT_MEM
  349. * @retval None
  350. */
  351. __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
  352. {
  353. /* Enable the system handler fault */
  354. SET_BIT(SCB->SHCSR, Fault);
  355. }
  356. /**
  357. * @brief Disable a fault in System handler control register (SHCSR)
  358. * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
  359. * @param Fault This parameter can be a combination of the following values:
  360. * @arg @ref LL_HANDLER_FAULT_USG
  361. * @arg @ref LL_HANDLER_FAULT_BUS
  362. * @arg @ref LL_HANDLER_FAULT_MEM
  363. * @retval None
  364. */
  365. __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
  366. {
  367. /* Disable the system handler fault */
  368. CLEAR_BIT(SCB->SHCSR, Fault);
  369. }
  370. /**
  371. * @}
  372. */
  373. /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
  374. * @{
  375. */
  376. /**
  377. * @brief Get Implementer code
  378. * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
  379. * @retval Value should be equal to 0x41 for ARM
  380. */
  381. __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
  382. {
  383. return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
  384. }
  385. /**
  386. * @brief Get Variant number (The r value in the rnpn product revision identifier)
  387. * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
  388. * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
  389. */
  390. __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
  391. {
  392. return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
  393. }
  394. /**
  395. * @brief Get Constant number
  396. * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
  397. * @retval Value should be equal to 0xF for Cortex-M3 devices
  398. */
  399. __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
  400. {
  401. return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
  402. }
  403. /**
  404. * @brief Get Part number
  405. * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
  406. * @retval Value should be equal to 0xC23 for Cortex-M3
  407. */
  408. __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
  409. {
  410. return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
  411. }
  412. /**
  413. * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
  414. * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
  415. * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
  416. */
  417. __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
  418. {
  419. return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
  420. }
  421. /**
  422. * @}
  423. */
  424. #if __MPU_PRESENT
  425. /** @defgroup CORTEX_LL_EF_MPU MPU
  426. * @{
  427. */
  428. /**
  429. * @brief Enable MPU with input options
  430. * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
  431. * @param Options This parameter can be one of the following values:
  432. * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  433. * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
  434. * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
  435. * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
  436. * @retval None
  437. */
  438. __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
  439. {
  440. /* Enable the MPU*/
  441. WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
  442. /* Ensure MPU settings take effects */
  443. __DSB();
  444. /* Sequence instruction fetches using update settings */
  445. __ISB();
  446. }
  447. /**
  448. * @brief Disable MPU
  449. * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
  450. * @retval None
  451. */
  452. __STATIC_INLINE void LL_MPU_Disable(void)
  453. {
  454. /* Make sure outstanding transfers are done */
  455. __DMB();
  456. /* Disable MPU*/
  457. WRITE_REG(MPU->CTRL, 0U);
  458. }
  459. /**
  460. * @brief Check if MPU is enabled or not
  461. * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
  462. * @retval State of bit (1 or 0).
  463. */
  464. __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
  465. {
  466. return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
  467. }
  468. /**
  469. * @brief Enable a MPU region
  470. * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
  471. * @param Region This parameter can be one of the following values:
  472. * @arg @ref LL_MPU_REGION_NUMBER0
  473. * @arg @ref LL_MPU_REGION_NUMBER1
  474. * @arg @ref LL_MPU_REGION_NUMBER2
  475. * @arg @ref LL_MPU_REGION_NUMBER3
  476. * @arg @ref LL_MPU_REGION_NUMBER4
  477. * @arg @ref LL_MPU_REGION_NUMBER5
  478. * @arg @ref LL_MPU_REGION_NUMBER6
  479. * @arg @ref LL_MPU_REGION_NUMBER7
  480. * @retval None
  481. */
  482. __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
  483. {
  484. /* Set Region number */
  485. WRITE_REG(MPU->RNR, Region);
  486. /* Enable the MPU region */
  487. SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
  488. }
  489. /**
  490. * @brief Configure and enable a region
  491. * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
  492. * MPU_RBAR REGION LL_MPU_ConfigRegion\n
  493. * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
  494. * MPU_RASR XN LL_MPU_ConfigRegion\n
  495. * MPU_RASR AP LL_MPU_ConfigRegion\n
  496. * MPU_RASR S LL_MPU_ConfigRegion\n
  497. * MPU_RASR C LL_MPU_ConfigRegion\n
  498. * MPU_RASR B LL_MPU_ConfigRegion\n
  499. * MPU_RASR SIZE LL_MPU_ConfigRegion
  500. * @param Region This parameter can be one of the following values:
  501. * @arg @ref LL_MPU_REGION_NUMBER0
  502. * @arg @ref LL_MPU_REGION_NUMBER1
  503. * @arg @ref LL_MPU_REGION_NUMBER2
  504. * @arg @ref LL_MPU_REGION_NUMBER3
  505. * @arg @ref LL_MPU_REGION_NUMBER4
  506. * @arg @ref LL_MPU_REGION_NUMBER5
  507. * @arg @ref LL_MPU_REGION_NUMBER6
  508. * @arg @ref LL_MPU_REGION_NUMBER7
  509. * @param Address Value of region base address
  510. * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
  511. * @param Attributes This parameter can be a combination of the following values:
  512. * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
  513. * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
  514. * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
  515. * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
  516. * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
  517. * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
  518. * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
  519. * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
  520. * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
  521. * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
  522. * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
  523. * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
  524. * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
  525. * @retval None
  526. */
  527. __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
  528. {
  529. /* Set Region number */
  530. WRITE_REG(MPU->RNR, Region);
  531. /* Set base address */
  532. WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
  533. /* Configure MPU */
  534. WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
  535. }
  536. /**
  537. * @brief Disable a region
  538. * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
  539. * MPU_RASR ENABLE LL_MPU_DisableRegion
  540. * @param Region This parameter can be one of the following values:
  541. * @arg @ref LL_MPU_REGION_NUMBER0
  542. * @arg @ref LL_MPU_REGION_NUMBER1
  543. * @arg @ref LL_MPU_REGION_NUMBER2
  544. * @arg @ref LL_MPU_REGION_NUMBER3
  545. * @arg @ref LL_MPU_REGION_NUMBER4
  546. * @arg @ref LL_MPU_REGION_NUMBER5
  547. * @arg @ref LL_MPU_REGION_NUMBER6
  548. * @arg @ref LL_MPU_REGION_NUMBER7
  549. * @retval None
  550. */
  551. __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
  552. {
  553. /* Set Region number */
  554. WRITE_REG(MPU->RNR, Region);
  555. /* Disable the MPU region */
  556. CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
  557. }
  558. /**
  559. * @}
  560. */
  561. #endif /* __MPU_PRESENT */
  562. /**
  563. * @}
  564. */
  565. /**
  566. * @}
  567. */
  568. /**
  569. * @}
  570. */
  571. #ifdef __cplusplus
  572. }
  573. #endif
  574. #endif /* __STM32F1xx_LL_CORTEX_H */
  575. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/