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stm32f1xx_ll_adc.h 223KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_adc.h
  4. * @author MCD Application Team
  5. * @brief Header file of ADC LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef __STM32F1xx_LL_ADC_H
  21. #define __STM32F1xx_LL_ADC_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f1xx.h"
  27. /** @addtogroup STM32F1xx_LL_Driver
  28. * @{
  29. */
  30. #if defined (ADC1) || defined (ADC2) || defined (ADC3)
  31. /** @defgroup ADC_LL ADC
  32. * @{
  33. */
  34. /* Private types -------------------------------------------------------------*/
  35. /* Private variables ---------------------------------------------------------*/
  36. /* Private constants ---------------------------------------------------------*/
  37. /** @defgroup ADC_LL_Private_Constants ADC Private Constants
  38. * @{
  39. */
  40. /* Internal mask for ADC group regular sequencer: */
  41. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
  42. /* - sequencer register offset */
  43. /* - sequencer rank bits position into the selected register */
  44. /* Internal register offset for ADC group regular sequencer configuration */
  45. /* (offset placed into a spare area of literal definition) */
  46. #define ADC_SQR1_REGOFFSET 0x00000000U
  47. #define ADC_SQR2_REGOFFSET 0x00000100U
  48. #define ADC_SQR3_REGOFFSET 0x00000200U
  49. #define ADC_SQR4_REGOFFSET 0x00000300U
  50. #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
  51. #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
  52. /* Definition of ADC group regular sequencer bits information to be inserted */
  53. /* into ADC group regular sequencer ranks literals definition. */
  54. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
  55. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
  56. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
  57. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
  58. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
  59. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
  60. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
  61. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
  62. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
  63. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
  64. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
  65. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
  66. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
  67. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
  68. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
  69. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
  70. /* Internal mask for ADC group injected sequencer: */
  71. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
  72. /* - data register offset */
  73. /* - offset register offset */
  74. /* - sequencer rank bits position into the selected register */
  75. /* Internal register offset for ADC group injected data register */
  76. /* (offset placed into a spare area of literal definition) */
  77. #define ADC_JDR1_REGOFFSET 0x00000000U
  78. #define ADC_JDR2_REGOFFSET 0x00000100U
  79. #define ADC_JDR3_REGOFFSET 0x00000200U
  80. #define ADC_JDR4_REGOFFSET 0x00000300U
  81. /* Internal register offset for ADC group injected offset configuration */
  82. /* (offset placed into a spare area of literal definition) */
  83. #define ADC_JOFR1_REGOFFSET 0x00000000U
  84. #define ADC_JOFR2_REGOFFSET 0x00001000U
  85. #define ADC_JOFR3_REGOFFSET 0x00002000U
  86. #define ADC_JOFR4_REGOFFSET 0x00003000U
  87. #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
  88. #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
  89. #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
  90. /* Internal mask for ADC channel: */
  91. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
  92. /* - channel identifier defined by number */
  93. /* - channel differentiation between external channels (connected to */
  94. /* GPIO pins) and internal channels (connected to internal paths) */
  95. /* - channel sampling time defined by SMPRx register offset */
  96. /* and SMPx bits positions into SMPRx register */
  97. #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
  98. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
  99. #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
  100. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
  101. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
  102. /* Channel differentiation between external and internal channels */
  103. #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
  104. #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
  105. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
  106. /* Internal register offset for ADC channel sampling time configuration */
  107. /* (offset placed into a spare area of literal definition) */
  108. #define ADC_SMPR1_REGOFFSET 0x00000000U
  109. #define ADC_SMPR2_REGOFFSET 0x02000000U
  110. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
  111. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
  112. #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
  113. /* Definition of channels ID number information to be inserted into */
  114. /* channels literals definition. */
  115. #define ADC_CHANNEL_0_NUMBER 0x00000000U
  116. #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
  117. #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
  118. #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  119. #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
  120. #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
  121. #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
  122. #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  123. #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
  124. #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
  125. #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
  126. #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  127. #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
  128. #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
  129. #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
  130. #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  131. #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
  132. #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
  133. /* Definition of channels sampling time information to be inserted into */
  134. /* channels literals definition. */
  135. #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
  136. #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
  137. #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
  138. #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
  139. #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
  140. #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
  141. #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
  142. #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
  143. #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
  144. #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
  145. #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
  146. #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
  147. #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
  148. #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
  149. #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
  150. #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
  151. #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
  152. #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
  153. /* Internal mask for ADC analog watchdog: */
  154. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
  155. /* (concatenation of multiple bits used in different analog watchdogs, */
  156. /* (feature of several watchdogs not available on all STM32 families)). */
  157. /* - analog watchdog 1: monitored channel defined by number, */
  158. /* selection of ADC group (ADC groups regular and-or injected). */
  159. /* Internal register offset for ADC analog watchdog channel configuration */
  160. #define ADC_AWD_CR1_REGOFFSET 0x00000000U
  161. #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
  162. #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
  163. #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
  164. /* Internal register offset for ADC analog watchdog threshold configuration */
  165. #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
  166. #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
  167. #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
  168. /* ADC registers bits positions */
  169. #define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
  170. /**
  171. * @}
  172. */
  173. /* Private macros ------------------------------------------------------------*/
  174. /** @defgroup ADC_LL_Private_Macros ADC Private Macros
  175. * @{
  176. */
  177. /**
  178. * @brief Driver macro reserved for internal use: isolate bits with the
  179. * selected mask and shift them to the register LSB
  180. * (shift mask on register position bit 0).
  181. * @param __BITS__ Bits in register 32 bits
  182. * @param __MASK__ Mask in register 32 bits
  183. * @retval Bits in register 32 bits
  184. */
  185. #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
  186. (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
  187. /**
  188. * @brief Driver macro reserved for internal use: set a pointer to
  189. * a register from a register basis from which an offset
  190. * is applied.
  191. * @param __REG__ Register basis from which the offset is applied.
  192. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
  193. * @retval Pointer to register address
  194. */
  195. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
  196. ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
  197. /**
  198. * @}
  199. */
  200. /* Exported types ------------------------------------------------------------*/
  201. #if defined(USE_FULL_LL_DRIVER)
  202. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
  203. * @{
  204. */
  205. /**
  206. * @brief Structure definition of some features of ADC common parameters
  207. * and multimode
  208. * (all ADC instances belonging to the same ADC common instance).
  209. * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
  210. * is conditioned to ADC instances state (all ADC instances
  211. * sharing the same ADC common instance):
  212. * All ADC instances sharing the same ADC common instance must be
  213. * disabled.
  214. */
  215. typedef struct
  216. {
  217. uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
  218. This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
  219. This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
  220. } LL_ADC_CommonInitTypeDef;
  221. /**
  222. * @brief Structure definition of some features of ADC instance.
  223. * @note These parameters have an impact on ADC scope: ADC instance.
  224. * Affects both group regular and group injected (availability
  225. * of ADC group injected depends on STM32 families).
  226. * Refer to corresponding unitary functions into
  227. * @ref ADC_LL_EF_Configuration_ADC_Instance .
  228. * @note The setting of these parameters by function @ref LL_ADC_Init()
  229. * is conditioned to ADC state:
  230. * ADC instance must be disabled.
  231. * This condition is applied to all ADC features, for efficiency
  232. * and compatibility over all STM32 families. However, the different
  233. * features can be set under different ADC state conditions
  234. * (setting possible with ADC enabled without conversion on going,
  235. * ADC enabled with conversion on going, ...)
  236. * Each feature can be updated afterwards with a unitary function
  237. * and potentially with ADC in a different state than disabled,
  238. * refer to description of each function for setting
  239. * conditioned to ADC state.
  240. */
  241. typedef struct
  242. {
  243. uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
  244. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
  245. This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
  246. uint32_t SequencersScanMode; /*!< Set ADC scan selection.
  247. This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
  248. This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
  249. } LL_ADC_InitTypeDef;
  250. /**
  251. * @brief Structure definition of some features of ADC group regular.
  252. * @note These parameters have an impact on ADC scope: ADC group regular.
  253. * Refer to corresponding unitary functions into
  254. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  255. * (functions with prefix "REG").
  256. * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
  257. * is conditioned to ADC state:
  258. * ADC instance must be disabled.
  259. * This condition is applied to all ADC features, for efficiency
  260. * and compatibility over all STM32 families. However, the different
  261. * features can be set under different ADC state conditions
  262. * (setting possible with ADC enabled without conversion on going,
  263. * ADC enabled with conversion on going, ...)
  264. * Each feature can be updated afterwards with a unitary function
  265. * and potentially with ADC in a different state than disabled,
  266. * refer to description of each function for setting
  267. * conditioned to ADC state.
  268. */
  269. typedef struct
  270. {
  271. uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
  272. This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
  273. @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
  274. (only trigger polarity available on this STM32 serie).
  275. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
  276. uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
  277. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
  278. @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
  279. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
  280. uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
  281. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
  282. @note This parameter has an effect only if group regular sequencer is enabled
  283. (scan length of 2 ranks or more).
  284. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
  285. uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
  286. This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
  287. Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
  288. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
  289. uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
  290. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
  291. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
  292. } LL_ADC_REG_InitTypeDef;
  293. /**
  294. * @brief Structure definition of some features of ADC group injected.
  295. * @note These parameters have an impact on ADC scope: ADC group injected.
  296. * Refer to corresponding unitary functions into
  297. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  298. * (functions with prefix "INJ").
  299. * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
  300. * is conditioned to ADC state:
  301. * ADC instance must be disabled.
  302. * This condition is applied to all ADC features, for efficiency
  303. * and compatibility over all STM32 families. However, the different
  304. * features can be set under different ADC state conditions
  305. * (setting possible with ADC enabled without conversion on going,
  306. * ADC enabled with conversion on going, ...)
  307. * Each feature can be updated afterwards with a unitary function
  308. * and potentially with ADC in a different state than disabled,
  309. * refer to description of each function for setting
  310. * conditioned to ADC state.
  311. */
  312. typedef struct
  313. {
  314. uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
  315. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
  316. @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
  317. (only trigger polarity available on this STM32 serie).
  318. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
  319. uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
  320. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
  321. @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
  322. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
  323. uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
  324. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
  325. @note This parameter has an effect only if group injected sequencer is enabled
  326. (scan length of 2 ranks or more).
  327. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
  328. uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
  329. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
  330. Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
  331. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
  332. } LL_ADC_INJ_InitTypeDef;
  333. /**
  334. * @}
  335. */
  336. #endif /* USE_FULL_LL_DRIVER */
  337. /* Exported constants --------------------------------------------------------*/
  338. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
  339. * @{
  340. */
  341. /** @defgroup ADC_LL_EC_FLAG ADC flags
  342. * @brief Flags defines which can be used with LL_ADC_ReadReg function
  343. * @{
  344. */
  345. #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
  346. #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
  347. #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
  348. #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
  349. #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
  350. #if defined(ADC_MULTIMODE_SUPPORT)
  351. #define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
  352. #define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
  353. #define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
  354. #define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
  355. #define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
  356. #define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
  357. #endif
  358. /**
  359. * @}
  360. */
  361. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
  362. * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
  363. * @{
  364. */
  365. #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
  366. #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
  367. #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
  368. /**
  369. * @}
  370. */
  371. /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
  372. * @{
  373. */
  374. /* List of ADC registers intended to be used (most commonly) with */
  375. /* DMA transfer. */
  376. /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
  377. #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
  378. #if defined(ADC_MULTIMODE_SUPPORT)
  379. #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
  380. #endif
  381. /**
  382. * @}
  383. */
  384. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
  385. * @{
  386. */
  387. /* Note: Other measurement paths to internal channels may be available */
  388. /* (connections to other peripherals). */
  389. /* If they are not listed below, they do not require any specific */
  390. /* path enable. In this case, Access to measurement path is done */
  391. /* only by selecting the corresponding ADC internal channel. */
  392. #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
  393. #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
  394. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
  395. /**
  396. * @}
  397. */
  398. /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
  399. * @{
  400. */
  401. #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
  402. /**
  403. * @}
  404. */
  405. /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
  406. * @{
  407. */
  408. #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
  409. #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
  410. /**
  411. * @}
  412. */
  413. /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
  414. * @{
  415. */
  416. #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
  417. #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
  418. /**
  419. * @}
  420. */
  421. /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
  422. * @{
  423. */
  424. #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
  425. #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
  426. #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
  427. /**
  428. * @}
  429. */
  430. /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
  431. * @{
  432. */
  433. #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
  434. #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
  435. #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
  436. #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
  437. #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
  438. #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
  439. #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
  440. #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
  441. #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
  442. #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
  443. #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
  444. #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
  445. #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
  446. #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
  447. #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
  448. #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
  449. #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
  450. #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
  451. #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */
  452. #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
  453. /**
  454. * @}
  455. */
  456. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
  457. * @{
  458. */
  459. /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
  460. #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */
  461. #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  462. /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
  463. #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  464. #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  465. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  466. #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
  467. #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  468. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
  469. #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
  470. /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
  471. /* XL-density devices. */
  472. /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
  473. /* A remap of trigger must be done at top level (refer to */
  474. /* AFIO peripheral). */
  475. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/
  476. #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
  477. #if defined (STM32F103xE) || defined (STM32F103xG)
  478. /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
  479. #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  480. #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  481. #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  482. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
  483. #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  484. #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  485. #endif
  486. /**
  487. * @}
  488. */
  489. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
  490. * @{
  491. */
  492. #define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */
  493. /**
  494. * @}
  495. */
  496. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
  497. * @{
  498. */
  499. #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
  500. #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
  501. /**
  502. * @}
  503. */
  504. /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
  505. * @{
  506. */
  507. #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
  508. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
  509. /**
  510. * @}
  511. */
  512. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
  513. * @{
  514. */
  515. #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
  516. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
  517. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
  518. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
  519. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
  520. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
  521. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
  522. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
  523. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
  524. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
  525. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
  526. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
  527. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
  528. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
  529. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
  530. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
  531. /**
  532. * @}
  533. */
  534. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
  535. * @{
  536. */
  537. #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
  538. #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
  539. #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
  540. #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
  541. #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
  542. #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
  543. #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
  544. #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
  545. #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
  546. /**
  547. * @}
  548. */
  549. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
  550. * @{
  551. */
  552. #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
  553. #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
  554. #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
  555. #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
  556. #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
  557. #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
  558. #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
  559. #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
  560. #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
  561. #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
  562. #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
  563. #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
  564. #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
  565. #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
  566. #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
  567. #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
  568. /**
  569. * @}
  570. */
  571. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
  572. * @{
  573. */
  574. /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
  575. #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */
  576. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
  577. #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  578. /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
  579. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
  580. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  581. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  582. #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
  583. #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
  584. #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
  585. /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
  586. /* XL-density devices. */
  587. /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
  588. /* A remap of trigger must be done at top level (refer to */
  589. /* AFIO peripheral). */
  590. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */
  591. #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
  592. #if defined (STM32F103xE) || defined (STM32F103xG)
  593. /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
  594. #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  595. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  596. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  597. #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
  598. #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  599. #endif
  600. /**
  601. * @}
  602. */
  603. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
  604. * @{
  605. */
  606. #define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */
  607. /**
  608. * @}
  609. */
  610. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
  611. * @{
  612. */
  613. #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
  614. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
  615. /**
  616. * @}
  617. */
  618. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
  619. * @{
  620. */
  621. #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
  622. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
  623. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
  624. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
  625. /**
  626. * @}
  627. */
  628. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
  629. * @{
  630. */
  631. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
  632. #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
  633. /**
  634. * @}
  635. */
  636. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
  637. * @{
  638. */
  639. #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
  640. #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
  641. #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
  642. #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
  643. /**
  644. * @}
  645. */
  646. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
  647. * @{
  648. */
  649. #define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
  650. #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
  651. #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
  652. #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
  653. #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
  654. #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
  655. #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
  656. #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
  657. /**
  658. * @}
  659. */
  660. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
  661. * @{
  662. */
  663. #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
  664. /**
  665. * @}
  666. */
  667. /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
  668. * @{
  669. */
  670. #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
  671. #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
  672. #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
  673. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
  674. #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
  675. #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
  676. #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
  677. #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
  678. #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
  679. #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
  680. #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
  681. #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
  682. #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
  683. #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
  684. #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
  685. #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
  686. #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
  687. #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
  688. #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
  689. #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
  690. #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
  691. #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
  692. #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
  693. #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
  694. #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
  695. #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
  696. #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
  697. #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
  698. #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
  699. #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
  700. #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
  701. #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
  702. #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
  703. #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
  704. #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
  705. #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
  706. #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
  707. #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
  708. #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
  709. #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
  710. #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
  711. #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
  712. #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
  713. #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
  714. #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
  715. #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
  716. #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
  717. #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
  718. #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
  719. #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
  720. #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
  721. #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
  722. #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
  723. #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
  724. #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
  725. #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
  726. #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
  727. #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
  728. #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
  729. #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
  730. #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
  731. #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
  732. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
  733. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
  734. /**
  735. * @}
  736. */
  737. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
  738. * @{
  739. */
  740. #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
  741. #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
  742. /**
  743. * @}
  744. */
  745. #if !defined(ADC_MULTIMODE_SUPPORT)
  746. /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
  747. * @{
  748. */
  749. #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
  750. /**
  751. * @}
  752. */
  753. #endif
  754. #if defined(ADC_MULTIMODE_SUPPORT)
  755. /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
  756. * @{
  757. */
  758. #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
  759. #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
  760. #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */
  761. #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
  762. #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
  763. #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
  764. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
  765. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
  766. #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */
  767. #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */
  768. /**
  769. * @}
  770. */
  771. /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
  772. * @{
  773. */
  774. #define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */
  775. #define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */
  776. #define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
  777. /**
  778. * @}
  779. */
  780. #endif /* ADC_MULTIMODE_SUPPORT */
  781. /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
  782. * @note Only ADC IP HW delays are defined in ADC LL driver driver,
  783. * not timeout values.
  784. * For details on delays values, refer to descriptions in source code
  785. * above each literal definition.
  786. * @{
  787. */
  788. /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
  789. /* not timeout values. */
  790. /* Timeout values for ADC operations are dependent to device clock */
  791. /* configuration (system clock versus ADC clock), */
  792. /* and therefore must be defined in user application. */
  793. /* Indications for estimation of ADC timeout delays, for this */
  794. /* STM32 serie: */
  795. /* - ADC enable time: maximum delay is 1us */
  796. /* (refer to device datasheet, parameter "tSTAB") */
  797. /* - ADC conversion time: duration depending on ADC clock and ADC */
  798. /* configuration. */
  799. /* (refer to device reference manual, section "Timing") */
  800. /* Delay for temperature sensor stabilization time. */
  801. /* Literal set to maximum value (refer to device datasheet, */
  802. /* parameter "tSTART"). */
  803. /* Unit: us */
  804. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */
  805. /* Delay required between ADC disable and ADC calibration start. */
  806. /* Note: On this STM32 serie, before starting a calibration, */
  807. /* ADC must be disabled. */
  808. /* A minimum number of ADC clock cycles are required */
  809. /* between ADC disable state and calibration start. */
  810. /* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
  811. /* Wait time can be computed in user application by waiting for the */
  812. /* equivalent number of CPU cycles, by taking into account */
  813. /* ratio of CPU clock versus ADC clock prescalers. */
  814. /* Unit: ADC clock cycles. */
  815. #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */
  816. /* Delay required between end of ADC Enable and the start of ADC calibration. */
  817. /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
  818. /* are required between the end of ADC enable and the start of ADC */
  819. /* calibration. */
  820. /* Wait time can be computed in user application by waiting for the */
  821. /* equivalent number of CPU cycles, by taking into account */
  822. /* ratio of CPU clock versus ADC clock prescalers. */
  823. /* Unit: ADC clock cycles. */
  824. #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */
  825. /**
  826. * @}
  827. */
  828. /**
  829. * @}
  830. */
  831. /* Exported macro ------------------------------------------------------------*/
  832. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
  833. * @{
  834. */
  835. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
  836. * @{
  837. */
  838. /**
  839. * @brief Write a value in ADC register
  840. * @param __INSTANCE__ ADC Instance
  841. * @param __REG__ Register to be written
  842. * @param __VALUE__ Value to be written in the register
  843. * @retval None
  844. */
  845. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  846. /**
  847. * @brief Read a value in ADC register
  848. * @param __INSTANCE__ ADC Instance
  849. * @param __REG__ Register to be read
  850. * @retval Register value
  851. */
  852. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  853. /**
  854. * @}
  855. */
  856. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
  857. * @{
  858. */
  859. /**
  860. * @brief Helper macro to get ADC channel number in decimal format
  861. * from literals LL_ADC_CHANNEL_x.
  862. * @note Example:
  863. * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
  864. * will return decimal number "4".
  865. * @note The input can be a value from functions where a channel
  866. * number is returned, either defined with number
  867. * or with bitfield (only one bit must be set).
  868. * @param __CHANNEL__ This parameter can be one of the following values:
  869. * @arg @ref LL_ADC_CHANNEL_0
  870. * @arg @ref LL_ADC_CHANNEL_1
  871. * @arg @ref LL_ADC_CHANNEL_2
  872. * @arg @ref LL_ADC_CHANNEL_3
  873. * @arg @ref LL_ADC_CHANNEL_4
  874. * @arg @ref LL_ADC_CHANNEL_5
  875. * @arg @ref LL_ADC_CHANNEL_6
  876. * @arg @ref LL_ADC_CHANNEL_7
  877. * @arg @ref LL_ADC_CHANNEL_8
  878. * @arg @ref LL_ADC_CHANNEL_9
  879. * @arg @ref LL_ADC_CHANNEL_10
  880. * @arg @ref LL_ADC_CHANNEL_11
  881. * @arg @ref LL_ADC_CHANNEL_12
  882. * @arg @ref LL_ADC_CHANNEL_13
  883. * @arg @ref LL_ADC_CHANNEL_14
  884. * @arg @ref LL_ADC_CHANNEL_15
  885. * @arg @ref LL_ADC_CHANNEL_16
  886. * @arg @ref LL_ADC_CHANNEL_17
  887. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  888. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  889. *
  890. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  891. * @retval Value between Min_Data=0 and Max_Data=18
  892. */
  893. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
  894. (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
  895. /**
  896. * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
  897. * from number in decimal format.
  898. * @note Example:
  899. * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
  900. * will return a data equivalent to "LL_ADC_CHANNEL_4".
  901. * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
  902. * @retval Returned value can be one of the following values:
  903. * @arg @ref LL_ADC_CHANNEL_0
  904. * @arg @ref LL_ADC_CHANNEL_1
  905. * @arg @ref LL_ADC_CHANNEL_2
  906. * @arg @ref LL_ADC_CHANNEL_3
  907. * @arg @ref LL_ADC_CHANNEL_4
  908. * @arg @ref LL_ADC_CHANNEL_5
  909. * @arg @ref LL_ADC_CHANNEL_6
  910. * @arg @ref LL_ADC_CHANNEL_7
  911. * @arg @ref LL_ADC_CHANNEL_8
  912. * @arg @ref LL_ADC_CHANNEL_9
  913. * @arg @ref LL_ADC_CHANNEL_10
  914. * @arg @ref LL_ADC_CHANNEL_11
  915. * @arg @ref LL_ADC_CHANNEL_12
  916. * @arg @ref LL_ADC_CHANNEL_13
  917. * @arg @ref LL_ADC_CHANNEL_14
  918. * @arg @ref LL_ADC_CHANNEL_15
  919. * @arg @ref LL_ADC_CHANNEL_16
  920. * @arg @ref LL_ADC_CHANNEL_17
  921. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  922. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  923. *
  924. * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
  925. * (1) For ADC channel read back from ADC register,
  926. * comparison with internal channel parameter to be done
  927. * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  928. */
  929. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
  930. (((__DECIMAL_NB__) <= 9U) \
  931. ? ( \
  932. ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
  933. (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
  934. ) \
  935. : \
  936. ( \
  937. ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
  938. (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
  939. ) \
  940. )
  941. /**
  942. * @brief Helper macro to determine whether the selected channel
  943. * corresponds to literal definitions of driver.
  944. * @note The different literal definitions of ADC channels are:
  945. * - ADC internal channel:
  946. * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  947. * - ADC external channel (channel connected to a GPIO pin):
  948. * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
  949. * @note The channel parameter must be a value defined from literal
  950. * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
  951. * LL_ADC_CHANNEL_TEMPSENSOR, ...),
  952. * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
  953. * must not be a value from functions where a channel number is
  954. * returned from ADC registers,
  955. * because internal and external channels share the same channel
  956. * number in ADC registers. The differentiation is made only with
  957. * parameters definitions of driver.
  958. * @param __CHANNEL__ This parameter can be one of the following values:
  959. * @arg @ref LL_ADC_CHANNEL_0
  960. * @arg @ref LL_ADC_CHANNEL_1
  961. * @arg @ref LL_ADC_CHANNEL_2
  962. * @arg @ref LL_ADC_CHANNEL_3
  963. * @arg @ref LL_ADC_CHANNEL_4
  964. * @arg @ref LL_ADC_CHANNEL_5
  965. * @arg @ref LL_ADC_CHANNEL_6
  966. * @arg @ref LL_ADC_CHANNEL_7
  967. * @arg @ref LL_ADC_CHANNEL_8
  968. * @arg @ref LL_ADC_CHANNEL_9
  969. * @arg @ref LL_ADC_CHANNEL_10
  970. * @arg @ref LL_ADC_CHANNEL_11
  971. * @arg @ref LL_ADC_CHANNEL_12
  972. * @arg @ref LL_ADC_CHANNEL_13
  973. * @arg @ref LL_ADC_CHANNEL_14
  974. * @arg @ref LL_ADC_CHANNEL_15
  975. * @arg @ref LL_ADC_CHANNEL_16
  976. * @arg @ref LL_ADC_CHANNEL_17
  977. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  978. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  979. *
  980. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  981. * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
  982. * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
  983. */
  984. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
  985. (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
  986. /**
  987. * @brief Helper macro to convert a channel defined from parameter
  988. * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
  989. * LL_ADC_CHANNEL_TEMPSENSOR, ...),
  990. * to its equivalent parameter definition of a ADC external channel
  991. * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
  992. * @note The channel parameter can be, additionally to a value
  993. * defined from parameter definition of a ADC internal channel
  994. * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
  995. * a value defined from parameter definition of
  996. * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
  997. * or a value from functions where a channel number is returned
  998. * from ADC registers.
  999. * @param __CHANNEL__ This parameter can be one of the following values:
  1000. * @arg @ref LL_ADC_CHANNEL_0
  1001. * @arg @ref LL_ADC_CHANNEL_1
  1002. * @arg @ref LL_ADC_CHANNEL_2
  1003. * @arg @ref LL_ADC_CHANNEL_3
  1004. * @arg @ref LL_ADC_CHANNEL_4
  1005. * @arg @ref LL_ADC_CHANNEL_5
  1006. * @arg @ref LL_ADC_CHANNEL_6
  1007. * @arg @ref LL_ADC_CHANNEL_7
  1008. * @arg @ref LL_ADC_CHANNEL_8
  1009. * @arg @ref LL_ADC_CHANNEL_9
  1010. * @arg @ref LL_ADC_CHANNEL_10
  1011. * @arg @ref LL_ADC_CHANNEL_11
  1012. * @arg @ref LL_ADC_CHANNEL_12
  1013. * @arg @ref LL_ADC_CHANNEL_13
  1014. * @arg @ref LL_ADC_CHANNEL_14
  1015. * @arg @ref LL_ADC_CHANNEL_15
  1016. * @arg @ref LL_ADC_CHANNEL_16
  1017. * @arg @ref LL_ADC_CHANNEL_17
  1018. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  1019. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  1020. *
  1021. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  1022. * @retval Returned value can be one of the following values:
  1023. * @arg @ref LL_ADC_CHANNEL_0
  1024. * @arg @ref LL_ADC_CHANNEL_1
  1025. * @arg @ref LL_ADC_CHANNEL_2
  1026. * @arg @ref LL_ADC_CHANNEL_3
  1027. * @arg @ref LL_ADC_CHANNEL_4
  1028. * @arg @ref LL_ADC_CHANNEL_5
  1029. * @arg @ref LL_ADC_CHANNEL_6
  1030. * @arg @ref LL_ADC_CHANNEL_7
  1031. * @arg @ref LL_ADC_CHANNEL_8
  1032. * @arg @ref LL_ADC_CHANNEL_9
  1033. * @arg @ref LL_ADC_CHANNEL_10
  1034. * @arg @ref LL_ADC_CHANNEL_11
  1035. * @arg @ref LL_ADC_CHANNEL_12
  1036. * @arg @ref LL_ADC_CHANNEL_13
  1037. * @arg @ref LL_ADC_CHANNEL_14
  1038. * @arg @ref LL_ADC_CHANNEL_15
  1039. * @arg @ref LL_ADC_CHANNEL_16
  1040. * @arg @ref LL_ADC_CHANNEL_17
  1041. */
  1042. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
  1043. ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
  1044. /**
  1045. * @brief Helper macro to determine whether the internal channel
  1046. * selected is available on the ADC instance selected.
  1047. * @note The channel parameter must be a value defined from parameter
  1048. * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
  1049. * LL_ADC_CHANNEL_TEMPSENSOR, ...),
  1050. * must not be a value defined from parameter definition of
  1051. * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
  1052. * or a value from functions where a channel number is
  1053. * returned from ADC registers,
  1054. * because internal and external channels share the same channel
  1055. * number in ADC registers. The differentiation is made only with
  1056. * parameters definitions of driver.
  1057. * @param __ADC_INSTANCE__ ADC instance
  1058. * @param __CHANNEL__ This parameter can be one of the following values:
  1059. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  1060. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  1061. *
  1062. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  1063. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
  1064. * Value "1" if the internal channel selected is available on the ADC instance selected.
  1065. */
  1066. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
  1067. (((__ADC_INSTANCE__) == ADC1) \
  1068. ? ( \
  1069. ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
  1070. ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
  1071. ) \
  1072. : \
  1073. (0U) \
  1074. )
  1075. /**
  1076. * @brief Helper macro to define ADC analog watchdog parameter:
  1077. * define a single channel to monitor with analog watchdog
  1078. * from sequencer channel and groups definition.
  1079. * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
  1080. * Example:
  1081. * LL_ADC_SetAnalogWDMonitChannels(
  1082. * ADC1, LL_ADC_AWD1,
  1083. * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
  1084. * @param __CHANNEL__ This parameter can be one of the following values:
  1085. * @arg @ref LL_ADC_CHANNEL_0
  1086. * @arg @ref LL_ADC_CHANNEL_1
  1087. * @arg @ref LL_ADC_CHANNEL_2
  1088. * @arg @ref LL_ADC_CHANNEL_3
  1089. * @arg @ref LL_ADC_CHANNEL_4
  1090. * @arg @ref LL_ADC_CHANNEL_5
  1091. * @arg @ref LL_ADC_CHANNEL_6
  1092. * @arg @ref LL_ADC_CHANNEL_7
  1093. * @arg @ref LL_ADC_CHANNEL_8
  1094. * @arg @ref LL_ADC_CHANNEL_9
  1095. * @arg @ref LL_ADC_CHANNEL_10
  1096. * @arg @ref LL_ADC_CHANNEL_11
  1097. * @arg @ref LL_ADC_CHANNEL_12
  1098. * @arg @ref LL_ADC_CHANNEL_13
  1099. * @arg @ref LL_ADC_CHANNEL_14
  1100. * @arg @ref LL_ADC_CHANNEL_15
  1101. * @arg @ref LL_ADC_CHANNEL_16
  1102. * @arg @ref LL_ADC_CHANNEL_17
  1103. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  1104. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  1105. *
  1106. * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
  1107. * (1) For ADC channel read back from ADC register,
  1108. * comparison with internal channel parameter to be done
  1109. * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  1110. * @param __GROUP__ This parameter can be one of the following values:
  1111. * @arg @ref LL_ADC_GROUP_REGULAR
  1112. * @arg @ref LL_ADC_GROUP_INJECTED
  1113. * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
  1114. * @retval Returned value can be one of the following values:
  1115. * @arg @ref LL_ADC_AWD_DISABLE
  1116. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
  1117. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
  1118. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  1119. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
  1120. * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
  1121. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
  1122. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
  1123. * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
  1124. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
  1125. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
  1126. * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
  1127. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
  1128. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
  1129. * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
  1130. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
  1131. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
  1132. * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
  1133. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
  1134. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
  1135. * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
  1136. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
  1137. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
  1138. * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
  1139. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
  1140. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
  1141. * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
  1142. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
  1143. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
  1144. * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
  1145. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
  1146. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
  1147. * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
  1148. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
  1149. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
  1150. * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
  1151. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
  1152. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
  1153. * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
  1154. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
  1155. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
  1156. * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
  1157. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
  1158. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
  1159. * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
  1160. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
  1161. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
  1162. * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
  1163. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
  1164. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
  1165. * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
  1166. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
  1167. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
  1168. * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
  1169. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
  1170. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
  1171. * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
  1172. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
  1173. * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
  1174. * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
  1175. * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  1176. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  1177. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  1178. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
  1179. *
  1180. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  1181. */
  1182. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
  1183. (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
  1184. ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
  1185. : \
  1186. ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
  1187. ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
  1188. : \
  1189. (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
  1190. )
  1191. /**
  1192. * @brief Helper macro to set the value of ADC analog watchdog threshold high
  1193. * or low in function of ADC resolution, when ADC resolution is
  1194. * different of 12 bits.
  1195. * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
  1196. * Example, with a ADC resolution of 8 bits, to set the value of
  1197. * analog watchdog threshold high (on 8 bits):
  1198. * LL_ADC_SetAnalogWDThresholds
  1199. * (< ADCx param >,
  1200. * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
  1201. * );
  1202. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1203. * @arg @ref LL_ADC_RESOLUTION_12B
  1204. * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
  1205. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1206. */
  1207. /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
  1208. /* This macro has been kept anyway for compatibility with other */
  1209. /* STM32 families featuring different ADC resolutions. */
  1210. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
  1211. ((__AWD_THRESHOLD__) << (0U))
  1212. /**
  1213. * @brief Helper macro to get the value of ADC analog watchdog threshold high
  1214. * or low in function of ADC resolution, when ADC resolution is
  1215. * different of 12 bits.
  1216. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
  1217. * Example, with a ADC resolution of 8 bits, to get the value of
  1218. * analog watchdog threshold high (on 8 bits):
  1219. * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
  1220. * (LL_ADC_RESOLUTION_8B,
  1221. * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
  1222. * );
  1223. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1224. * @arg @ref LL_ADC_RESOLUTION_12B
  1225. * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
  1226. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1227. */
  1228. /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
  1229. /* This macro has been kept anyway for compatibility with other */
  1230. /* STM32 families featuring different ADC resolutions. */
  1231. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
  1232. (__AWD_THRESHOLD_12_BITS__)
  1233. #if defined(ADC_MULTIMODE_SUPPORT)
  1234. /**
  1235. * @brief Helper macro to get the ADC multimode conversion data of ADC master
  1236. * or ADC slave from raw value with both ADC conversion data concatenated.
  1237. * @note This macro is intended to be used when multimode transfer by DMA
  1238. * is enabled.
  1239. * In this case the transferred data need to processed with this macro
  1240. * to separate the conversion data of ADC master and ADC slave.
  1241. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  1242. * @arg @ref LL_ADC_MULTI_MASTER
  1243. * @arg @ref LL_ADC_MULTI_SLAVE
  1244. * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
  1245. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1246. */
  1247. #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
  1248. (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
  1249. #endif
  1250. /**
  1251. * @brief Helper macro to select the ADC common instance
  1252. * to which is belonging the selected ADC instance.
  1253. * @note ADC common register instance can be used for:
  1254. * - Set parameters common to several ADC instances
  1255. * - Multimode (for devices with several ADC instances)
  1256. * Refer to functions having argument "ADCxy_COMMON" as parameter.
  1257. * @note On STM32F1, there is no common ADC instance.
  1258. * However, ADC instance ADC1 has a role of common ADC instance
  1259. * for ADC1 and ADC2:
  1260. * this instance is used to manage internal channels
  1261. * and multimode (these features are managed in ADC common
  1262. * instances on some other STM32 devices).
  1263. * ADC instance ADC3 (if available on the selected device)
  1264. * has no ADC common instance.
  1265. * @param __ADCx__ ADC instance
  1266. * @retval ADC common register instance
  1267. */
  1268. #if defined(ADC1) && defined(ADC2) && defined(ADC3)
  1269. #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
  1270. ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
  1271. ? ( \
  1272. (ADC12_COMMON) \
  1273. ) \
  1274. : \
  1275. ( \
  1276. (0U) \
  1277. ) \
  1278. )
  1279. #elif defined(ADC1) && defined(ADC2)
  1280. #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
  1281. (ADC12_COMMON)
  1282. #else
  1283. #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
  1284. (ADC1_COMMON)
  1285. #endif
  1286. /**
  1287. * @brief Helper macro to check if all ADC instances sharing the same
  1288. * ADC common instance are disabled.
  1289. * @note This check is required by functions with setting conditioned to
  1290. * ADC state:
  1291. * All ADC instances of the ADC common group must be disabled.
  1292. * Refer to functions having argument "ADCxy_COMMON" as parameter.
  1293. * @note On devices with only 1 ADC common instance, parameter of this macro
  1294. * is useless and can be ignored (parameter kept for compatibility
  1295. * with devices featuring several ADC common instances).
  1296. * @note On STM32F1, there is no common ADC instance.
  1297. * However, ADC instance ADC1 has a role of common ADC instance
  1298. * for ADC1 and ADC2:
  1299. * this instance is used to manage internal channels
  1300. * and multimode (these features are managed in ADC common
  1301. * instances on some other STM32 devices).
  1302. * ADC instance ADC3 (if available on the selected device)
  1303. * has no ADC common instance.
  1304. * @param __ADCXY_COMMON__ ADC common instance
  1305. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  1306. * @retval Value "0" if all ADC instances sharing the same ADC common instance
  1307. * are disabled.
  1308. * Value "1" if at least one ADC instance sharing the same ADC common instance
  1309. * is enabled.
  1310. */
  1311. #if defined(ADC1) && defined(ADC2) && defined(ADC3)
  1312. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
  1313. (((__ADCXY_COMMON__) == ADC12_COMMON) \
  1314. ? ( \
  1315. (LL_ADC_IsEnabled(ADC1) | \
  1316. LL_ADC_IsEnabled(ADC2) ) \
  1317. ) \
  1318. : \
  1319. ( \
  1320. LL_ADC_IsEnabled(ADC3) \
  1321. ) \
  1322. )
  1323. #elif defined(ADC1) && defined(ADC2)
  1324. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
  1325. (LL_ADC_IsEnabled(ADC1) | \
  1326. LL_ADC_IsEnabled(ADC2) )
  1327. #else
  1328. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
  1329. LL_ADC_IsEnabled(ADC1)
  1330. #endif
  1331. /**
  1332. * @brief Helper macro to define the ADC conversion data full-scale digital
  1333. * value corresponding to the selected ADC resolution.
  1334. * @note ADC conversion data full-scale corresponds to voltage range
  1335. * determined by analog voltage references Vref+ and Vref-
  1336. * (refer to reference manual).
  1337. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1338. * @arg @ref LL_ADC_RESOLUTION_12B
  1339. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  1340. */
  1341. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
  1342. (0xFFFU)
  1343. /**
  1344. * @brief Helper macro to calculate the voltage (unit: mVolt)
  1345. * corresponding to a ADC conversion data (unit: digital value).
  1346. * @note Analog reference voltage (Vref+) must be known from
  1347. * user board environment or can be calculated using ADC measurement.
  1348. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
  1349. * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
  1350. * (unit: digital value).
  1351. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1352. * @arg @ref LL_ADC_RESOLUTION_12B
  1353. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  1354. */
  1355. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
  1356. __ADC_DATA__,\
  1357. __ADC_RESOLUTION__) \
  1358. ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
  1359. / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
  1360. )
  1361. /**
  1362. * @brief Helper macro to calculate the temperature (unit: degree Celsius)
  1363. * from ADC conversion data of internal temperature sensor.
  1364. * @note Computation is using temperature sensor typical values
  1365. * (refer to device datasheet).
  1366. * @note Calculation formula:
  1367. * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
  1368. * / Avg_Slope + CALx_TEMP
  1369. * with TS_ADC_DATA = temperature sensor raw data measured by ADC
  1370. * (unit: digital value)
  1371. * Avg_Slope = temperature sensor slope
  1372. * (unit: uV/Degree Celsius)
  1373. * TS_TYP_CALx_VOLT = temperature sensor digital value at
  1374. * temperature CALx_TEMP (unit: mV)
  1375. * Caution: Calculation relevancy under reserve the temperature sensor
  1376. * of the current device has characteristics in line with
  1377. * datasheet typical values.
  1378. * If temperature sensor calibration values are available on
  1379. * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
  1380. * temperature calculation will be more accurate using
  1381. * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
  1382. * @note As calculation input, the analog reference voltage (Vref+) must be
  1383. * defined as it impacts the ADC LSB equivalent voltage.
  1384. * @note Analog reference voltage (Vref+) must be known from
  1385. * user board environment or can be calculated using ADC measurement.
  1386. * @note ADC measurement data must correspond to a resolution of 12bits
  1387. * (full scale digital value 4095). If not the case, the data must be
  1388. * preliminarily rescaled to an equivalent resolution of 12 bits.
  1389. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
  1390. * On STM32F1, refer to device datasheet parameter "Avg_Slope".
  1391. * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
  1392. * On STM32F1, refer to device datasheet parameter "V25".
  1393. * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
  1394. * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
  1395. * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
  1396. * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
  1397. * This parameter can be one of the following values:
  1398. * @arg @ref LL_ADC_RESOLUTION_12B
  1399. * @retval Temperature (unit: degree Celsius)
  1400. */
  1401. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
  1402. __TEMPSENSOR_TYP_CALX_V__,\
  1403. __TEMPSENSOR_CALX_TEMP__,\
  1404. __VREFANALOG_VOLTAGE__,\
  1405. __TEMPSENSOR_ADC_DATA__,\
  1406. __ADC_RESOLUTION__) \
  1407. ((( ( \
  1408. (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
  1409. * 1000) \
  1410. - \
  1411. (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
  1412. / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
  1413. * 1000) \
  1414. ) \
  1415. ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
  1416. ) + (__TEMPSENSOR_CALX_TEMP__) \
  1417. )
  1418. /**
  1419. * @}
  1420. */
  1421. /**
  1422. * @}
  1423. */
  1424. /* Exported functions --------------------------------------------------------*/
  1425. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
  1426. * @{
  1427. */
  1428. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
  1429. * @{
  1430. */
  1431. /* Note: LL ADC functions to set DMA transfer are located into sections of */
  1432. /* configuration of ADC instance, groups and multimode (if available): */
  1433. /* @ref LL_ADC_REG_SetDMATransfer(), ... */
  1434. /**
  1435. * @brief Function to help to configure DMA transfer from ADC: retrieve the
  1436. * ADC register address from ADC instance and a list of ADC registers
  1437. * intended to be used (most commonly) with DMA transfer.
  1438. * @note These ADC registers are data registers:
  1439. * when ADC conversion data is available in ADC data registers,
  1440. * ADC generates a DMA transfer request.
  1441. * @note This macro is intended to be used with LL DMA driver, refer to
  1442. * function "LL_DMA_ConfigAddresses()".
  1443. * Example:
  1444. * LL_DMA_ConfigAddresses(DMA1,
  1445. * LL_DMA_CHANNEL_1,
  1446. * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
  1447. * (uint32_t)&< array or variable >,
  1448. * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
  1449. * @note For devices with several ADC: in multimode, some devices
  1450. * use a different data register outside of ADC instance scope
  1451. * (common data register). This macro manages this register difference,
  1452. * only ADC instance has to be set as parameter.
  1453. * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
  1454. * capability, not ADC2 (ADC2 and ADC3 instances not available on
  1455. * all devices).
  1456. * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
  1457. * Therefore, the corresponding parameter of data transfer
  1458. * for multimode can be used only with ADC1 and ADC2.
  1459. * (ADC2 and ADC3 instances not available on all devices).
  1460. * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
  1461. * @param ADCx ADC instance
  1462. * @param Register This parameter can be one of the following values:
  1463. * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
  1464. * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
  1465. *
  1466. * (1) Available on devices with several ADC instances.
  1467. * @retval ADC register address
  1468. */
  1469. #if defined(ADC_MULTIMODE_SUPPORT)
  1470. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
  1471. {
  1472. register uint32_t data_reg_addr = 0U;
  1473. if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
  1474. {
  1475. /* Retrieve address of register DR */
  1476. data_reg_addr = (uint32_t)&(ADCx->DR);
  1477. }
  1478. else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
  1479. {
  1480. /* Retrieve address of register of multimode data */
  1481. data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
  1482. }
  1483. return data_reg_addr;
  1484. }
  1485. #else
  1486. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
  1487. {
  1488. /* Retrieve address of register DR */
  1489. return (uint32_t)&(ADCx->DR);
  1490. }
  1491. #endif
  1492. /**
  1493. * @}
  1494. */
  1495. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
  1496. * @{
  1497. */
  1498. /**
  1499. * @brief Set parameter common to several ADC: measurement path to internal
  1500. * channels (VrefInt, temperature sensor, ...).
  1501. * @note One or several values can be selected.
  1502. * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
  1503. * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
  1504. * @note Stabilization time of measurement path to internal channel:
  1505. * After enabling internal paths, before starting ADC conversion,
  1506. * a delay is required for internal voltage reference and
  1507. * temperature sensor stabilization time.
  1508. * Refer to device datasheet.
  1509. * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
  1510. * @note ADC internal channel sampling time constraint:
  1511. * For ADC conversion of internal channels,
  1512. * a sampling time minimum value is required.
  1513. * Refer to device datasheet.
  1514. * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
  1515. * @param ADCxy_COMMON ADC common instance
  1516. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  1517. * @param PathInternal This parameter can be a combination of the following values:
  1518. * @arg @ref LL_ADC_PATH_INTERNAL_NONE
  1519. * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
  1520. * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  1521. * @retval None
  1522. */
  1523. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
  1524. {
  1525. MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
  1526. }
  1527. /**
  1528. * @brief Get parameter common to several ADC: measurement path to internal
  1529. * channels (VrefInt, temperature sensor, ...).
  1530. * @note One or several values can be selected.
  1531. * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
  1532. * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
  1533. * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
  1534. * @param ADCxy_COMMON ADC common instance
  1535. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  1536. * @retval Returned value can be a combination of the following values:
  1537. * @arg @ref LL_ADC_PATH_INTERNAL_NONE
  1538. * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
  1539. * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  1540. */
  1541. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
  1542. {
  1543. return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
  1544. }
  1545. /**
  1546. * @}
  1547. */
  1548. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
  1549. * @{
  1550. */
  1551. /**
  1552. * @brief Set ADC conversion data alignment.
  1553. * @note Refer to reference manual for alignments formats
  1554. * dependencies to ADC resolutions.
  1555. * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
  1556. * @param ADCx ADC instance
  1557. * @param DataAlignment This parameter can be one of the following values:
  1558. * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
  1559. * @arg @ref LL_ADC_DATA_ALIGN_LEFT
  1560. * @retval None
  1561. */
  1562. __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
  1563. {
  1564. MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
  1565. }
  1566. /**
  1567. * @brief Get ADC conversion data alignment.
  1568. * @note Refer to reference manual for alignments formats
  1569. * dependencies to ADC resolutions.
  1570. * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
  1571. * @param ADCx ADC instance
  1572. * @retval Returned value can be one of the following values:
  1573. * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
  1574. * @arg @ref LL_ADC_DATA_ALIGN_LEFT
  1575. */
  1576. __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
  1577. {
  1578. return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
  1579. }
  1580. /**
  1581. * @brief Set ADC sequencers scan mode, for all ADC groups
  1582. * (group regular, group injected).
  1583. * @note According to sequencers scan mode :
  1584. * - If disabled: ADC conversion is performed in unitary conversion
  1585. * mode (one channel converted, that defined in rank 1).
  1586. * Configuration of sequencers of all ADC groups
  1587. * (sequencer scan length, ...) is discarded: equivalent to
  1588. * scan length of 1 rank.
  1589. * - If enabled: ADC conversions are performed in sequence conversions
  1590. * mode, according to configuration of sequencers of
  1591. * each ADC group (sequencer scan length, ...).
  1592. * Refer to function @ref LL_ADC_REG_SetSequencerLength()
  1593. * and to function @ref LL_ADC_INJ_SetSequencerLength().
  1594. * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
  1595. * @param ADCx ADC instance
  1596. * @param ScanMode This parameter can be one of the following values:
  1597. * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
  1598. * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
  1599. * @retval None
  1600. */
  1601. __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
  1602. {
  1603. MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
  1604. }
  1605. /**
  1606. * @brief Get ADC sequencers scan mode, for all ADC groups
  1607. * (group regular, group injected).
  1608. * @note According to sequencers scan mode :
  1609. * - If disabled: ADC conversion is performed in unitary conversion
  1610. * mode (one channel converted, that defined in rank 1).
  1611. * Configuration of sequencers of all ADC groups
  1612. * (sequencer scan length, ...) is discarded: equivalent to
  1613. * scan length of 1 rank.
  1614. * - If enabled: ADC conversions are performed in sequence conversions
  1615. * mode, according to configuration of sequencers of
  1616. * each ADC group (sequencer scan length, ...).
  1617. * Refer to function @ref LL_ADC_REG_SetSequencerLength()
  1618. * and to function @ref LL_ADC_INJ_SetSequencerLength().
  1619. * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
  1620. * @param ADCx ADC instance
  1621. * @retval Returned value can be one of the following values:
  1622. * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
  1623. * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
  1624. */
  1625. __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
  1626. {
  1627. return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
  1628. }
  1629. /**
  1630. * @}
  1631. */
  1632. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
  1633. * @{
  1634. */
  1635. /**
  1636. * @brief Set ADC group regular conversion trigger source:
  1637. * internal (SW start) or from external IP (timer event,
  1638. * external interrupt line).
  1639. * @note On this STM32 serie, external trigger is set with trigger polarity:
  1640. * rising edge (only trigger polarity available on this STM32 serie).
  1641. * @note Availability of parameters of trigger sources from timer
  1642. * depends on timers availability on the selected device.
  1643. * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
  1644. * @param ADCx ADC instance
  1645. * @param TriggerSource This parameter can be one of the following values:
  1646. * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
  1647. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
  1648. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
  1649. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
  1650. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
  1651. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
  1652. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
  1653. * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
  1654. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
  1655. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
  1656. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
  1657. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
  1658. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
  1659. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
  1660. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
  1661. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
  1662. *
  1663. * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
  1664. * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
  1665. * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
  1666. * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
  1667. * @retval None
  1668. */
  1669. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
  1670. {
  1671. /* Note: On this STM32 serie, ADC group regular external trigger edge */
  1672. /* is used to perform a ADC conversion start. */
  1673. /* This function does not set external trigger edge. */
  1674. /* This feature is set using function */
  1675. /* @ref LL_ADC_REG_StartConversionExtTrig(). */
  1676. MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
  1677. }
  1678. /**
  1679. * @brief Get ADC group regular conversion trigger source:
  1680. * internal (SW start) or from external IP (timer event,
  1681. * external interrupt line).
  1682. * @note To determine whether group regular trigger source is
  1683. * internal (SW start) or external, without detail
  1684. * of which peripheral is selected as external trigger,
  1685. * (equivalent to
  1686. * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
  1687. * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
  1688. * @note Availability of parameters of trigger sources from timer
  1689. * depends on timers availability on the selected device.
  1690. * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
  1691. * @param ADCx ADC instance
  1692. * @retval Returned value can be one of the following values:
  1693. * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
  1694. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
  1695. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
  1696. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
  1697. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
  1698. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
  1699. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
  1700. * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
  1701. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
  1702. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
  1703. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
  1704. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
  1705. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
  1706. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
  1707. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
  1708. * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
  1709. *
  1710. * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
  1711. * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
  1712. * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
  1713. * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
  1714. */
  1715. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
  1716. {
  1717. return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
  1718. }
  1719. /**
  1720. * @brief Get ADC group regular conversion trigger source internal (SW start)
  1721. or external.
  1722. * @note In case of group regular trigger source set to external trigger,
  1723. * to determine which peripheral is selected as external trigger,
  1724. * use function @ref LL_ADC_REG_GetTriggerSource().
  1725. * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
  1726. * @param ADCx ADC instance
  1727. * @retval Value "0" if trigger source external trigger
  1728. * Value "1" if trigger source SW start.
  1729. */
  1730. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
  1731. {
  1732. return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
  1733. }
  1734. /**
  1735. * @brief Set ADC group regular sequencer length and scan direction.
  1736. * @note Description of ADC group regular sequencer features:
  1737. * - For devices with sequencer fully configurable
  1738. * (function "LL_ADC_REG_SetSequencerRanks()" available):
  1739. * sequencer length and each rank affectation to a channel
  1740. * are configurable.
  1741. * This function performs configuration of:
  1742. * - Sequence length: Number of ranks in the scan sequence.
  1743. * - Sequence direction: Unless specified in parameters, sequencer
  1744. * scan direction is forward (from rank 1 to rank n).
  1745. * Sequencer ranks are selected using
  1746. * function "LL_ADC_REG_SetSequencerRanks()".
  1747. * - For devices with sequencer not fully configurable
  1748. * (function "LL_ADC_REG_SetSequencerChannels()" available):
  1749. * sequencer length and each rank affectation to a channel
  1750. * are defined by channel number.
  1751. * This function performs configuration of:
  1752. * - Sequence length: Number of ranks in the scan sequence is
  1753. * defined by number of channels set in the sequence,
  1754. * rank of each channel is fixed by channel HW number.
  1755. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  1756. * - Sequence direction: Unless specified in parameters, sequencer
  1757. * scan direction is forward (from lowest channel number to
  1758. * highest channel number).
  1759. * Sequencer ranks are selected using
  1760. * function "LL_ADC_REG_SetSequencerChannels()".
  1761. * @note On this STM32 serie, group regular sequencer configuration
  1762. * is conditioned to ADC instance sequencer mode.
  1763. * If ADC instance sequencer mode is disabled, sequencers of
  1764. * all groups (group regular, group injected) can be configured
  1765. * but their execution is disabled (limited to rank 1).
  1766. * Refer to function @ref LL_ADC_SetSequencersScanMode().
  1767. * @note Sequencer disabled is equivalent to sequencer of 1 rank:
  1768. * ADC conversion on only 1 channel.
  1769. * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
  1770. * @param ADCx ADC instance
  1771. * @param SequencerNbRanks This parameter can be one of the following values:
  1772. * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
  1773. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  1774. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  1775. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  1776. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  1777. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  1778. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  1779. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  1780. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  1781. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  1782. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  1783. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  1784. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  1785. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  1786. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  1787. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
  1788. * @retval None
  1789. */
  1790. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
  1791. {
  1792. MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
  1793. }
  1794. /**
  1795. * @brief Get ADC group regular sequencer length and scan direction.
  1796. * @note Description of ADC group regular sequencer features:
  1797. * - For devices with sequencer fully configurable
  1798. * (function "LL_ADC_REG_SetSequencerRanks()" available):
  1799. * sequencer length and each rank affectation to a channel
  1800. * are configurable.
  1801. * This function retrieves:
  1802. * - Sequence length: Number of ranks in the scan sequence.
  1803. * - Sequence direction: Unless specified in parameters, sequencer
  1804. * scan direction is forward (from rank 1 to rank n).
  1805. * Sequencer ranks are selected using
  1806. * function "LL_ADC_REG_SetSequencerRanks()".
  1807. * - For devices with sequencer not fully configurable
  1808. * (function "LL_ADC_REG_SetSequencerChannels()" available):
  1809. * sequencer length and each rank affectation to a channel
  1810. * are defined by channel number.
  1811. * This function retrieves:
  1812. * - Sequence length: Number of ranks in the scan sequence is
  1813. * defined by number of channels set in the sequence,
  1814. * rank of each channel is fixed by channel HW number.
  1815. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  1816. * - Sequence direction: Unless specified in parameters, sequencer
  1817. * scan direction is forward (from lowest channel number to
  1818. * highest channel number).
  1819. * Sequencer ranks are selected using
  1820. * function "LL_ADC_REG_SetSequencerChannels()".
  1821. * @note On this STM32 serie, group regular sequencer configuration
  1822. * is conditioned to ADC instance sequencer mode.
  1823. * If ADC instance sequencer mode is disabled, sequencers of
  1824. * all groups (group regular, group injected) can be configured
  1825. * but their execution is disabled (limited to rank 1).
  1826. * Refer to function @ref LL_ADC_SetSequencersScanMode().
  1827. * @note Sequencer disabled is equivalent to sequencer of 1 rank:
  1828. * ADC conversion on only 1 channel.
  1829. * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
  1830. * @param ADCx ADC instance
  1831. * @retval Returned value can be one of the following values:
  1832. * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
  1833. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  1834. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  1835. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  1836. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  1837. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  1838. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  1839. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  1840. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  1841. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  1842. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  1843. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  1844. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  1845. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  1846. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  1847. * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
  1848. */
  1849. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
  1850. {
  1851. return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
  1852. }
  1853. /**
  1854. * @brief Set ADC group regular sequencer discontinuous mode:
  1855. * sequence subdivided and scan conversions interrupted every selected
  1856. * number of ranks.
  1857. * @note It is not possible to enable both ADC group regular
  1858. * continuous mode and sequencer discontinuous mode.
  1859. * @note It is not possible to enable both ADC auto-injected mode
  1860. * and ADC group regular sequencer discontinuous mode.
  1861. * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
  1862. * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
  1863. * @param ADCx ADC instance
  1864. * @param SeqDiscont This parameter can be one of the following values:
  1865. * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
  1866. * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
  1867. * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
  1868. * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
  1869. * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
  1870. * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
  1871. * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
  1872. * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
  1873. * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
  1874. * @retval None
  1875. */
  1876. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
  1877. {
  1878. MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
  1879. }
  1880. /**
  1881. * @brief Get ADC group regular sequencer discontinuous mode:
  1882. * sequence subdivided and scan conversions interrupted every selected
  1883. * number of ranks.
  1884. * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
  1885. * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
  1886. * @param ADCx ADC instance
  1887. * @retval Returned value can be one of the following values:
  1888. * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
  1889. * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
  1890. * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
  1891. * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
  1892. * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
  1893. * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
  1894. * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
  1895. * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
  1896. * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
  1897. */
  1898. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
  1899. {
  1900. return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
  1901. }
  1902. /**
  1903. * @brief Set ADC group regular sequence: channel on the selected
  1904. * scan sequence rank.
  1905. * @note This function performs configuration of:
  1906. * - Channels ordering into each rank of scan sequence:
  1907. * whatever channel can be placed into whatever rank.
  1908. * @note On this STM32 serie, ADC group regular sequencer is
  1909. * fully configurable: sequencer length and each rank
  1910. * affectation to a channel are configurable.
  1911. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
  1912. * @note Depending on devices and packages, some channels may not be available.
  1913. * Refer to device datasheet for channels availability.
  1914. * @note On this STM32 serie, to measure internal channels (VrefInt,
  1915. * TempSensor, ...), measurement paths to internal channels must be
  1916. * enabled separately.
  1917. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
  1918. * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
  1919. * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
  1920. * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
  1921. * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
  1922. * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
  1923. * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
  1924. * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
  1925. * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
  1926. * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
  1927. * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
  1928. * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
  1929. * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
  1930. * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
  1931. * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
  1932. * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
  1933. * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
  1934. * @param ADCx ADC instance
  1935. * @param Rank This parameter can be one of the following values:
  1936. * @arg @ref LL_ADC_REG_RANK_1
  1937. * @arg @ref LL_ADC_REG_RANK_2
  1938. * @arg @ref LL_ADC_REG_RANK_3
  1939. * @arg @ref LL_ADC_REG_RANK_4
  1940. * @arg @ref LL_ADC_REG_RANK_5
  1941. * @arg @ref LL_ADC_REG_RANK_6
  1942. * @arg @ref LL_ADC_REG_RANK_7
  1943. * @arg @ref LL_ADC_REG_RANK_8
  1944. * @arg @ref LL_ADC_REG_RANK_9
  1945. * @arg @ref LL_ADC_REG_RANK_10
  1946. * @arg @ref LL_ADC_REG_RANK_11
  1947. * @arg @ref LL_ADC_REG_RANK_12
  1948. * @arg @ref LL_ADC_REG_RANK_13
  1949. * @arg @ref LL_ADC_REG_RANK_14
  1950. * @arg @ref LL_ADC_REG_RANK_15
  1951. * @arg @ref LL_ADC_REG_RANK_16
  1952. * @param Channel This parameter can be one of the following values:
  1953. * @arg @ref LL_ADC_CHANNEL_0
  1954. * @arg @ref LL_ADC_CHANNEL_1
  1955. * @arg @ref LL_ADC_CHANNEL_2
  1956. * @arg @ref LL_ADC_CHANNEL_3
  1957. * @arg @ref LL_ADC_CHANNEL_4
  1958. * @arg @ref LL_ADC_CHANNEL_5
  1959. * @arg @ref LL_ADC_CHANNEL_6
  1960. * @arg @ref LL_ADC_CHANNEL_7
  1961. * @arg @ref LL_ADC_CHANNEL_8
  1962. * @arg @ref LL_ADC_CHANNEL_9
  1963. * @arg @ref LL_ADC_CHANNEL_10
  1964. * @arg @ref LL_ADC_CHANNEL_11
  1965. * @arg @ref LL_ADC_CHANNEL_12
  1966. * @arg @ref LL_ADC_CHANNEL_13
  1967. * @arg @ref LL_ADC_CHANNEL_14
  1968. * @arg @ref LL_ADC_CHANNEL_15
  1969. * @arg @ref LL_ADC_CHANNEL_16
  1970. * @arg @ref LL_ADC_CHANNEL_17
  1971. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  1972. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  1973. *
  1974. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  1975. * @retval None
  1976. */
  1977. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
  1978. {
  1979. /* Set bits with content of parameter "Channel" with bits position */
  1980. /* in register and register position depending on parameter "Rank". */
  1981. /* Parameters "Rank" and "Channel" are used with masks because containing */
  1982. /* other bits reserved for other purpose. */
  1983. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
  1984. MODIFY_REG(*preg,
  1985. ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
  1986. (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
  1987. }
  1988. /**
  1989. * @brief Get ADC group regular sequence: channel on the selected
  1990. * scan sequence rank.
  1991. * @note On this STM32 serie, ADC group regular sequencer is
  1992. * fully configurable: sequencer length and each rank
  1993. * affectation to a channel are configurable.
  1994. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
  1995. * @note Depending on devices and packages, some channels may not be available.
  1996. * Refer to device datasheet for channels availability.
  1997. * @note Usage of the returned channel number:
  1998. * - To reinject this channel into another function LL_ADC_xxx:
  1999. * the returned channel number is only partly formatted on definition
  2000. * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
  2001. * with parts of literals LL_ADC_CHANNEL_x or using
  2002. * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2003. * Then the selected literal LL_ADC_CHANNEL_x can be used
  2004. * as parameter for another function.
  2005. * - To get the channel number in decimal format:
  2006. * process the returned value with the helper macro
  2007. * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2008. * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
  2009. * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
  2010. * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
  2011. * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
  2012. * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
  2013. * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
  2014. * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
  2015. * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
  2016. * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
  2017. * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
  2018. * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
  2019. * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
  2020. * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
  2021. * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
  2022. * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
  2023. * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
  2024. * @param ADCx ADC instance
  2025. * @param Rank This parameter can be one of the following values:
  2026. * @arg @ref LL_ADC_REG_RANK_1
  2027. * @arg @ref LL_ADC_REG_RANK_2
  2028. * @arg @ref LL_ADC_REG_RANK_3
  2029. * @arg @ref LL_ADC_REG_RANK_4
  2030. * @arg @ref LL_ADC_REG_RANK_5
  2031. * @arg @ref LL_ADC_REG_RANK_6
  2032. * @arg @ref LL_ADC_REG_RANK_7
  2033. * @arg @ref LL_ADC_REG_RANK_8
  2034. * @arg @ref LL_ADC_REG_RANK_9
  2035. * @arg @ref LL_ADC_REG_RANK_10
  2036. * @arg @ref LL_ADC_REG_RANK_11
  2037. * @arg @ref LL_ADC_REG_RANK_12
  2038. * @arg @ref LL_ADC_REG_RANK_13
  2039. * @arg @ref LL_ADC_REG_RANK_14
  2040. * @arg @ref LL_ADC_REG_RANK_15
  2041. * @arg @ref LL_ADC_REG_RANK_16
  2042. * @retval Returned value can be one of the following values:
  2043. * @arg @ref LL_ADC_CHANNEL_0
  2044. * @arg @ref LL_ADC_CHANNEL_1
  2045. * @arg @ref LL_ADC_CHANNEL_2
  2046. * @arg @ref LL_ADC_CHANNEL_3
  2047. * @arg @ref LL_ADC_CHANNEL_4
  2048. * @arg @ref LL_ADC_CHANNEL_5
  2049. * @arg @ref LL_ADC_CHANNEL_6
  2050. * @arg @ref LL_ADC_CHANNEL_7
  2051. * @arg @ref LL_ADC_CHANNEL_8
  2052. * @arg @ref LL_ADC_CHANNEL_9
  2053. * @arg @ref LL_ADC_CHANNEL_10
  2054. * @arg @ref LL_ADC_CHANNEL_11
  2055. * @arg @ref LL_ADC_CHANNEL_12
  2056. * @arg @ref LL_ADC_CHANNEL_13
  2057. * @arg @ref LL_ADC_CHANNEL_14
  2058. * @arg @ref LL_ADC_CHANNEL_15
  2059. * @arg @ref LL_ADC_CHANNEL_16
  2060. * @arg @ref LL_ADC_CHANNEL_17
  2061. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  2062. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  2063. *
  2064. * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
  2065. * (1) For ADC channel read back from ADC register,
  2066. * comparison with internal channel parameter to be done
  2067. * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  2068. */
  2069. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
  2070. {
  2071. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
  2072. return (uint32_t) (READ_BIT(*preg,
  2073. ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
  2074. >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
  2075. );
  2076. }
  2077. /**
  2078. * @brief Set ADC continuous conversion mode on ADC group regular.
  2079. * @note Description of ADC continuous conversion mode:
  2080. * - single mode: one conversion per trigger
  2081. * - continuous mode: after the first trigger, following
  2082. * conversions launched successively automatically.
  2083. * @note It is not possible to enable both ADC group regular
  2084. * continuous mode and sequencer discontinuous mode.
  2085. * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
  2086. * @param ADCx ADC instance
  2087. * @param Continuous This parameter can be one of the following values:
  2088. * @arg @ref LL_ADC_REG_CONV_SINGLE
  2089. * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
  2090. * @retval None
  2091. */
  2092. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
  2093. {
  2094. MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
  2095. }
  2096. /**
  2097. * @brief Get ADC continuous conversion mode on ADC group regular.
  2098. * @note Description of ADC continuous conversion mode:
  2099. * - single mode: one conversion per trigger
  2100. * - continuous mode: after the first trigger, following
  2101. * conversions launched successively automatically.
  2102. * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
  2103. * @param ADCx ADC instance
  2104. * @retval Returned value can be one of the following values:
  2105. * @arg @ref LL_ADC_REG_CONV_SINGLE
  2106. * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
  2107. */
  2108. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
  2109. {
  2110. return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
  2111. }
  2112. /**
  2113. * @brief Set ADC group regular conversion data transfer: no transfer or
  2114. * transfer by DMA, and DMA requests mode.
  2115. * @note If transfer by DMA selected, specifies the DMA requests
  2116. * mode:
  2117. * - Limited mode (One shot mode): DMA transfer requests are stopped
  2118. * when number of DMA data transfers (number of
  2119. * ADC conversions) is reached.
  2120. * This ADC mode is intended to be used with DMA mode non-circular.
  2121. * - Unlimited mode: DMA transfer requests are unlimited,
  2122. * whatever number of DMA data transfers (number of
  2123. * ADC conversions).
  2124. * This ADC mode is intended to be used with DMA mode circular.
  2125. * @note If ADC DMA requests mode is set to unlimited and DMA is set to
  2126. * mode non-circular:
  2127. * when DMA transfers size will be reached, DMA will stop transfers of
  2128. * ADC conversions data ADC will raise an overrun error
  2129. * (overrun flag and interruption if enabled).
  2130. * @note To configure DMA source address (peripheral address),
  2131. * use function @ref LL_ADC_DMA_GetRegAddr().
  2132. * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
  2133. * @param ADCx ADC instance
  2134. * @param DMATransfer This parameter can be one of the following values:
  2135. * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
  2136. * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
  2137. * @retval None
  2138. */
  2139. __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
  2140. {
  2141. MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
  2142. }
  2143. /**
  2144. * @brief Get ADC group regular conversion data transfer: no transfer or
  2145. * transfer by DMA, and DMA requests mode.
  2146. * @note If transfer by DMA selected, specifies the DMA requests
  2147. * mode:
  2148. * - Limited mode (One shot mode): DMA transfer requests are stopped
  2149. * when number of DMA data transfers (number of
  2150. * ADC conversions) is reached.
  2151. * This ADC mode is intended to be used with DMA mode non-circular.
  2152. * - Unlimited mode: DMA transfer requests are unlimited,
  2153. * whatever number of DMA data transfers (number of
  2154. * ADC conversions).
  2155. * This ADC mode is intended to be used with DMA mode circular.
  2156. * @note If ADC DMA requests mode is set to unlimited and DMA is set to
  2157. * mode non-circular:
  2158. * when DMA transfers size will be reached, DMA will stop transfers of
  2159. * ADC conversions data ADC will raise an overrun error
  2160. * (overrun flag and interruption if enabled).
  2161. * @note To configure DMA source address (peripheral address),
  2162. * use function @ref LL_ADC_DMA_GetRegAddr().
  2163. * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
  2164. * @param ADCx ADC instance
  2165. * @retval Returned value can be one of the following values:
  2166. * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
  2167. * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
  2168. */
  2169. __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
  2170. {
  2171. return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
  2172. }
  2173. /**
  2174. * @}
  2175. */
  2176. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
  2177. * @{
  2178. */
  2179. /**
  2180. * @brief Set ADC group injected conversion trigger source:
  2181. * internal (SW start) or from external IP (timer event,
  2182. * external interrupt line).
  2183. * @note On this STM32 serie, external trigger is set with trigger polarity:
  2184. * rising edge (only trigger polarity available on this STM32 serie).
  2185. * @note Availability of parameters of trigger sources from timer
  2186. * depends on timers availability on the selected device.
  2187. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
  2188. * @param ADCx ADC instance
  2189. * @param TriggerSource This parameter can be one of the following values:
  2190. * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
  2191. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
  2192. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
  2193. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
  2194. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
  2195. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
  2196. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
  2197. * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
  2198. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
  2199. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
  2200. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
  2201. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
  2202. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
  2203. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
  2204. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
  2205. *
  2206. * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
  2207. * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
  2208. * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
  2209. * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
  2210. * @retval None
  2211. */
  2212. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
  2213. {
  2214. /* Note: On this STM32 serie, ADC group injected external trigger edge */
  2215. /* is used to perform a ADC conversion start. */
  2216. /* This function does not set external trigger edge. */
  2217. /* This feature is set using function */
  2218. /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
  2219. MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
  2220. }
  2221. /**
  2222. * @brief Get ADC group injected conversion trigger source:
  2223. * internal (SW start) or from external IP (timer event,
  2224. * external interrupt line).
  2225. * @note To determine whether group injected trigger source is
  2226. * internal (SW start) or external, without detail
  2227. * of which peripheral is selected as external trigger,
  2228. * (equivalent to
  2229. * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
  2230. * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
  2231. * @note Availability of parameters of trigger sources from timer
  2232. * depends on timers availability on the selected device.
  2233. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
  2234. * @param ADCx ADC instance
  2235. * @retval Returned value can be one of the following values:
  2236. * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
  2237. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
  2238. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
  2239. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
  2240. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
  2241. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
  2242. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
  2243. * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
  2244. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
  2245. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
  2246. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
  2247. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
  2248. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
  2249. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
  2250. * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
  2251. *
  2252. * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
  2253. * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
  2254. * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
  2255. * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
  2256. */
  2257. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
  2258. {
  2259. return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
  2260. }
  2261. /**
  2262. * @brief Get ADC group injected conversion trigger source internal (SW start)
  2263. or external
  2264. * @note In case of group injected trigger source set to external trigger,
  2265. * to determine which peripheral is selected as external trigger,
  2266. * use function @ref LL_ADC_INJ_GetTriggerSource.
  2267. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
  2268. * @param ADCx ADC instance
  2269. * @retval Value "0" if trigger source external trigger
  2270. * Value "1" if trigger source SW start.
  2271. */
  2272. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
  2273. {
  2274. return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
  2275. }
  2276. /**
  2277. * @brief Set ADC group injected sequencer length and scan direction.
  2278. * @note This function performs configuration of:
  2279. * - Sequence length: Number of ranks in the scan sequence.
  2280. * - Sequence direction: Unless specified in parameters, sequencer
  2281. * scan direction is forward (from rank 1 to rank n).
  2282. * @note On this STM32 serie, group injected sequencer configuration
  2283. * is conditioned to ADC instance sequencer mode.
  2284. * If ADC instance sequencer mode is disabled, sequencers of
  2285. * all groups (group regular, group injected) can be configured
  2286. * but their execution is disabled (limited to rank 1).
  2287. * Refer to function @ref LL_ADC_SetSequencersScanMode().
  2288. * @note Sequencer disabled is equivalent to sequencer of 1 rank:
  2289. * ADC conversion on only 1 channel.
  2290. * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
  2291. * @param ADCx ADC instance
  2292. * @param SequencerNbRanks This parameter can be one of the following values:
  2293. * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
  2294. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  2295. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  2296. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
  2297. * @retval None
  2298. */
  2299. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
  2300. {
  2301. MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
  2302. }
  2303. /**
  2304. * @brief Get ADC group injected sequencer length and scan direction.
  2305. * @note This function retrieves:
  2306. * - Sequence length: Number of ranks in the scan sequence.
  2307. * - Sequence direction: Unless specified in parameters, sequencer
  2308. * scan direction is forward (from rank 1 to rank n).
  2309. * @note On this STM32 serie, group injected sequencer configuration
  2310. * is conditioned to ADC instance sequencer mode.
  2311. * If ADC instance sequencer mode is disabled, sequencers of
  2312. * all groups (group regular, group injected) can be configured
  2313. * but their execution is disabled (limited to rank 1).
  2314. * Refer to function @ref LL_ADC_SetSequencersScanMode().
  2315. * @note Sequencer disabled is equivalent to sequencer of 1 rank:
  2316. * ADC conversion on only 1 channel.
  2317. * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
  2318. * @param ADCx ADC instance
  2319. * @retval Returned value can be one of the following values:
  2320. * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
  2321. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  2322. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  2323. * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
  2324. */
  2325. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
  2326. {
  2327. return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
  2328. }
  2329. /**
  2330. * @brief Set ADC group injected sequencer discontinuous mode:
  2331. * sequence subdivided and scan conversions interrupted every selected
  2332. * number of ranks.
  2333. * @note It is not possible to enable both ADC group injected
  2334. * auto-injected mode and sequencer discontinuous mode.
  2335. * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
  2336. * @param ADCx ADC instance
  2337. * @param SeqDiscont This parameter can be one of the following values:
  2338. * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
  2339. * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
  2340. * @retval None
  2341. */
  2342. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
  2343. {
  2344. MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
  2345. }
  2346. /**
  2347. * @brief Get ADC group injected sequencer discontinuous mode:
  2348. * sequence subdivided and scan conversions interrupted every selected
  2349. * number of ranks.
  2350. * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
  2351. * @param ADCx ADC instance
  2352. * @retval Returned value can be one of the following values:
  2353. * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
  2354. * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
  2355. */
  2356. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
  2357. {
  2358. return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
  2359. }
  2360. /**
  2361. * @brief Set ADC group injected sequence: channel on the selected
  2362. * sequence rank.
  2363. * @note Depending on devices and packages, some channels may not be available.
  2364. * Refer to device datasheet for channels availability.
  2365. * @note On this STM32 serie, to measure internal channels (VrefInt,
  2366. * TempSensor, ...), measurement paths to internal channels must be
  2367. * enabled separately.
  2368. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
  2369. * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
  2370. * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
  2371. * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
  2372. * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
  2373. * @param ADCx ADC instance
  2374. * @param Rank This parameter can be one of the following values:
  2375. * @arg @ref LL_ADC_INJ_RANK_1
  2376. * @arg @ref LL_ADC_INJ_RANK_2
  2377. * @arg @ref LL_ADC_INJ_RANK_3
  2378. * @arg @ref LL_ADC_INJ_RANK_4
  2379. * @param Channel This parameter can be one of the following values:
  2380. * @arg @ref LL_ADC_CHANNEL_0
  2381. * @arg @ref LL_ADC_CHANNEL_1
  2382. * @arg @ref LL_ADC_CHANNEL_2
  2383. * @arg @ref LL_ADC_CHANNEL_3
  2384. * @arg @ref LL_ADC_CHANNEL_4
  2385. * @arg @ref LL_ADC_CHANNEL_5
  2386. * @arg @ref LL_ADC_CHANNEL_6
  2387. * @arg @ref LL_ADC_CHANNEL_7
  2388. * @arg @ref LL_ADC_CHANNEL_8
  2389. * @arg @ref LL_ADC_CHANNEL_9
  2390. * @arg @ref LL_ADC_CHANNEL_10
  2391. * @arg @ref LL_ADC_CHANNEL_11
  2392. * @arg @ref LL_ADC_CHANNEL_12
  2393. * @arg @ref LL_ADC_CHANNEL_13
  2394. * @arg @ref LL_ADC_CHANNEL_14
  2395. * @arg @ref LL_ADC_CHANNEL_15
  2396. * @arg @ref LL_ADC_CHANNEL_16
  2397. * @arg @ref LL_ADC_CHANNEL_17
  2398. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  2399. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  2400. *
  2401. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  2402. * @retval None
  2403. */
  2404. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
  2405. {
  2406. /* Set bits with content of parameter "Channel" with bits position */
  2407. /* in register depending on parameter "Rank". */
  2408. /* Parameters "Rank" and "Channel" are used with masks because containing */
  2409. /* other bits reserved for other purpose. */
  2410. register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
  2411. MODIFY_REG(ADCx->JSQR,
  2412. ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
  2413. (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
  2414. }
  2415. /**
  2416. * @brief Get ADC group injected sequence: channel on the selected
  2417. * sequence rank.
  2418. * @note Depending on devices and packages, some channels may not be available.
  2419. * Refer to device datasheet for channels availability.
  2420. * @note Usage of the returned channel number:
  2421. * - To reinject this channel into another function LL_ADC_xxx:
  2422. * the returned channel number is only partly formatted on definition
  2423. * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
  2424. * with parts of literals LL_ADC_CHANNEL_x or using
  2425. * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2426. * Then the selected literal LL_ADC_CHANNEL_x can be used
  2427. * as parameter for another function.
  2428. * - To get the channel number in decimal format:
  2429. * process the returned value with the helper macro
  2430. * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2431. * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
  2432. * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
  2433. * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
  2434. * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
  2435. * @param ADCx ADC instance
  2436. * @param Rank This parameter can be one of the following values:
  2437. * @arg @ref LL_ADC_INJ_RANK_1
  2438. * @arg @ref LL_ADC_INJ_RANK_2
  2439. * @arg @ref LL_ADC_INJ_RANK_3
  2440. * @arg @ref LL_ADC_INJ_RANK_4
  2441. * @retval Returned value can be one of the following values:
  2442. * @arg @ref LL_ADC_CHANNEL_0
  2443. * @arg @ref LL_ADC_CHANNEL_1
  2444. * @arg @ref LL_ADC_CHANNEL_2
  2445. * @arg @ref LL_ADC_CHANNEL_3
  2446. * @arg @ref LL_ADC_CHANNEL_4
  2447. * @arg @ref LL_ADC_CHANNEL_5
  2448. * @arg @ref LL_ADC_CHANNEL_6
  2449. * @arg @ref LL_ADC_CHANNEL_7
  2450. * @arg @ref LL_ADC_CHANNEL_8
  2451. * @arg @ref LL_ADC_CHANNEL_9
  2452. * @arg @ref LL_ADC_CHANNEL_10
  2453. * @arg @ref LL_ADC_CHANNEL_11
  2454. * @arg @ref LL_ADC_CHANNEL_12
  2455. * @arg @ref LL_ADC_CHANNEL_13
  2456. * @arg @ref LL_ADC_CHANNEL_14
  2457. * @arg @ref LL_ADC_CHANNEL_15
  2458. * @arg @ref LL_ADC_CHANNEL_16
  2459. * @arg @ref LL_ADC_CHANNEL_17
  2460. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  2461. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  2462. *
  2463. * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
  2464. * (1) For ADC channel read back from ADC register,
  2465. * comparison with internal channel parameter to be done
  2466. * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  2467. */
  2468. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
  2469. {
  2470. register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
  2471. return (uint32_t)(READ_BIT(ADCx->JSQR,
  2472. ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
  2473. >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
  2474. );
  2475. }
  2476. /**
  2477. * @brief Set ADC group injected conversion trigger:
  2478. * independent or from ADC group regular.
  2479. * @note This mode can be used to extend number of data registers
  2480. * updated after one ADC conversion trigger and with data
  2481. * permanently kept (not erased by successive conversions of scan of
  2482. * ADC sequencer ranks), up to 5 data registers:
  2483. * 1 data register on ADC group regular, 4 data registers
  2484. * on ADC group injected.
  2485. * @note If ADC group injected injected trigger source is set to an
  2486. * external trigger, this feature must be must be set to
  2487. * independent trigger.
  2488. * ADC group injected automatic trigger is compliant only with
  2489. * group injected trigger source set to SW start, without any
  2490. * further action on ADC group injected conversion start or stop:
  2491. * in this case, ADC group injected is controlled only
  2492. * from ADC group regular.
  2493. * @note It is not possible to enable both ADC group injected
  2494. * auto-injected mode and sequencer discontinuous mode.
  2495. * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
  2496. * @param ADCx ADC instance
  2497. * @param TrigAuto This parameter can be one of the following values:
  2498. * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
  2499. * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
  2500. * @retval None
  2501. */
  2502. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
  2503. {
  2504. MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
  2505. }
  2506. /**
  2507. * @brief Get ADC group injected conversion trigger:
  2508. * independent or from ADC group regular.
  2509. * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
  2510. * @param ADCx ADC instance
  2511. * @retval Returned value can be one of the following values:
  2512. * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
  2513. * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
  2514. */
  2515. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
  2516. {
  2517. return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
  2518. }
  2519. /**
  2520. * @brief Set ADC group injected offset.
  2521. * @note It sets:
  2522. * - ADC group injected rank to which the offset programmed
  2523. * will be applied
  2524. * - Offset level (offset to be subtracted from the raw
  2525. * converted data).
  2526. * Caution: Offset format is dependent to ADC resolution:
  2527. * offset has to be left-aligned on bit 11, the LSB (right bits)
  2528. * are set to 0.
  2529. * @note Offset cannot be enabled or disabled.
  2530. * To emulate offset disabled, set an offset value equal to 0.
  2531. * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
  2532. * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
  2533. * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
  2534. * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
  2535. * @param ADCx ADC instance
  2536. * @param Rank This parameter can be one of the following values:
  2537. * @arg @ref LL_ADC_INJ_RANK_1
  2538. * @arg @ref LL_ADC_INJ_RANK_2
  2539. * @arg @ref LL_ADC_INJ_RANK_3
  2540. * @arg @ref LL_ADC_INJ_RANK_4
  2541. * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
  2542. * @retval None
  2543. */
  2544. __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
  2545. {
  2546. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
  2547. MODIFY_REG(*preg,
  2548. ADC_JOFR1_JOFFSET1,
  2549. OffsetLevel);
  2550. }
  2551. /**
  2552. * @brief Get ADC group injected offset.
  2553. * @note It gives offset level (offset to be subtracted from the raw converted data).
  2554. * Caution: Offset format is dependent to ADC resolution:
  2555. * offset has to be left-aligned on bit 11, the LSB (right bits)
  2556. * are set to 0.
  2557. * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
  2558. * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
  2559. * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
  2560. * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
  2561. * @param ADCx ADC instance
  2562. * @param Rank This parameter can be one of the following values:
  2563. * @arg @ref LL_ADC_INJ_RANK_1
  2564. * @arg @ref LL_ADC_INJ_RANK_2
  2565. * @arg @ref LL_ADC_INJ_RANK_3
  2566. * @arg @ref LL_ADC_INJ_RANK_4
  2567. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  2568. */
  2569. __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
  2570. {
  2571. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
  2572. return (uint32_t)(READ_BIT(*preg,
  2573. ADC_JOFR1_JOFFSET1)
  2574. );
  2575. }
  2576. /**
  2577. * @}
  2578. */
  2579. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
  2580. * @{
  2581. */
  2582. /**
  2583. * @brief Set sampling time of the selected ADC channel
  2584. * Unit: ADC clock cycles.
  2585. * @note On this device, sampling time is on channel scope: independently
  2586. * of channel mapped on ADC group regular or injected.
  2587. * @note In case of internal channel (VrefInt, TempSensor, ...) to be
  2588. * converted:
  2589. * sampling time constraints must be respected (sampling time can be
  2590. * adjusted in function of ADC clock frequency and sampling time
  2591. * setting).
  2592. * Refer to device datasheet for timings values (parameters TS_vrefint,
  2593. * TS_temp, ...).
  2594. * @note Conversion time is the addition of sampling time and processing time.
  2595. * Refer to reference manual for ADC processing time of
  2596. * this STM32 serie.
  2597. * @note In case of ADC conversion of internal channel (VrefInt,
  2598. * temperature sensor, ...), a sampling time minimum value
  2599. * is required.
  2600. * Refer to device datasheet.
  2601. * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
  2602. * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
  2603. * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
  2604. * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
  2605. * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
  2606. * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
  2607. * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
  2608. * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
  2609. * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
  2610. * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
  2611. * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
  2612. * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
  2613. * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
  2614. * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
  2615. * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
  2616. * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
  2617. * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
  2618. * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
  2619. * @param ADCx ADC instance
  2620. * @param Channel This parameter can be one of the following values:
  2621. * @arg @ref LL_ADC_CHANNEL_0
  2622. * @arg @ref LL_ADC_CHANNEL_1
  2623. * @arg @ref LL_ADC_CHANNEL_2
  2624. * @arg @ref LL_ADC_CHANNEL_3
  2625. * @arg @ref LL_ADC_CHANNEL_4
  2626. * @arg @ref LL_ADC_CHANNEL_5
  2627. * @arg @ref LL_ADC_CHANNEL_6
  2628. * @arg @ref LL_ADC_CHANNEL_7
  2629. * @arg @ref LL_ADC_CHANNEL_8
  2630. * @arg @ref LL_ADC_CHANNEL_9
  2631. * @arg @ref LL_ADC_CHANNEL_10
  2632. * @arg @ref LL_ADC_CHANNEL_11
  2633. * @arg @ref LL_ADC_CHANNEL_12
  2634. * @arg @ref LL_ADC_CHANNEL_13
  2635. * @arg @ref LL_ADC_CHANNEL_14
  2636. * @arg @ref LL_ADC_CHANNEL_15
  2637. * @arg @ref LL_ADC_CHANNEL_16
  2638. * @arg @ref LL_ADC_CHANNEL_17
  2639. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  2640. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  2641. *
  2642. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  2643. * @param SamplingTime This parameter can be one of the following values:
  2644. * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
  2645. * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
  2646. * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
  2647. * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
  2648. * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
  2649. * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
  2650. * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
  2651. * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
  2652. * @retval None
  2653. */
  2654. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
  2655. {
  2656. /* Set bits with content of parameter "SamplingTime" with bits position */
  2657. /* in register and register position depending on parameter "Channel". */
  2658. /* Parameter "Channel" is used with masks because containing */
  2659. /* other bits reserved for other purpose. */
  2660. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
  2661. MODIFY_REG(*preg,
  2662. ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
  2663. SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
  2664. }
  2665. /**
  2666. * @brief Get sampling time of the selected ADC channel
  2667. * Unit: ADC clock cycles.
  2668. * @note On this device, sampling time is on channel scope: independently
  2669. * of channel mapped on ADC group regular or injected.
  2670. * @note Conversion time is the addition of sampling time and processing time.
  2671. * Refer to reference manual for ADC processing time of
  2672. * this STM32 serie.
  2673. * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
  2674. * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
  2675. * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
  2676. * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
  2677. * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
  2678. * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
  2679. * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
  2680. * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
  2681. * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
  2682. * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
  2683. * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
  2684. * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
  2685. * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
  2686. * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
  2687. * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
  2688. * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
  2689. * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
  2690. * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
  2691. * @param ADCx ADC instance
  2692. * @param Channel This parameter can be one of the following values:
  2693. * @arg @ref LL_ADC_CHANNEL_0
  2694. * @arg @ref LL_ADC_CHANNEL_1
  2695. * @arg @ref LL_ADC_CHANNEL_2
  2696. * @arg @ref LL_ADC_CHANNEL_3
  2697. * @arg @ref LL_ADC_CHANNEL_4
  2698. * @arg @ref LL_ADC_CHANNEL_5
  2699. * @arg @ref LL_ADC_CHANNEL_6
  2700. * @arg @ref LL_ADC_CHANNEL_7
  2701. * @arg @ref LL_ADC_CHANNEL_8
  2702. * @arg @ref LL_ADC_CHANNEL_9
  2703. * @arg @ref LL_ADC_CHANNEL_10
  2704. * @arg @ref LL_ADC_CHANNEL_11
  2705. * @arg @ref LL_ADC_CHANNEL_12
  2706. * @arg @ref LL_ADC_CHANNEL_13
  2707. * @arg @ref LL_ADC_CHANNEL_14
  2708. * @arg @ref LL_ADC_CHANNEL_15
  2709. * @arg @ref LL_ADC_CHANNEL_16
  2710. * @arg @ref LL_ADC_CHANNEL_17
  2711. * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
  2712. * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
  2713. *
  2714. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  2715. * @retval Returned value can be one of the following values:
  2716. * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
  2717. * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
  2718. * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
  2719. * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
  2720. * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
  2721. * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
  2722. * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
  2723. * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
  2724. */
  2725. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
  2726. {
  2727. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
  2728. return (uint32_t)(READ_BIT(*preg,
  2729. ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
  2730. >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
  2731. );
  2732. }
  2733. /**
  2734. * @}
  2735. */
  2736. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
  2737. * @{
  2738. */
  2739. /**
  2740. * @brief Set ADC analog watchdog monitored channels:
  2741. * a single channel or all channels,
  2742. * on ADC groups regular and-or injected.
  2743. * @note Once monitored channels are selected, analog watchdog
  2744. * is enabled.
  2745. * @note In case of need to define a single channel to monitor
  2746. * with analog watchdog from sequencer channel definition,
  2747. * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
  2748. * @note On this STM32 serie, there is only 1 kind of analog watchdog
  2749. * instance:
  2750. * - AWD standard (instance AWD1):
  2751. * - channels monitored: can monitor 1 channel or all channels.
  2752. * - groups monitored: ADC groups regular and-or injected.
  2753. * - resolution: resolution is not limited (corresponds to
  2754. * ADC resolution configured).
  2755. * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
  2756. * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
  2757. * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
  2758. * @param ADCx ADC instance
  2759. * @param AWDChannelGroup This parameter can be one of the following values:
  2760. * @arg @ref LL_ADC_AWD_DISABLE
  2761. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
  2762. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
  2763. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  2764. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
  2765. * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
  2766. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
  2767. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
  2768. * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
  2769. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
  2770. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
  2771. * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
  2772. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
  2773. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
  2774. * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
  2775. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
  2776. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
  2777. * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
  2778. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
  2779. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
  2780. * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
  2781. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
  2782. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
  2783. * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
  2784. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
  2785. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
  2786. * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
  2787. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
  2788. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
  2789. * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
  2790. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
  2791. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
  2792. * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
  2793. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
  2794. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
  2795. * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
  2796. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
  2797. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
  2798. * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
  2799. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
  2800. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
  2801. * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
  2802. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
  2803. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
  2804. * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
  2805. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
  2806. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
  2807. * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
  2808. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
  2809. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
  2810. * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
  2811. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
  2812. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
  2813. * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
  2814. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
  2815. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
  2816. * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
  2817. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
  2818. * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
  2819. * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
  2820. * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  2821. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  2822. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  2823. * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
  2824. *
  2825. * (1) On STM32F1, parameter available only on ADC instance: ADC1.
  2826. * @retval None
  2827. */
  2828. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
  2829. {
  2830. MODIFY_REG(ADCx->CR1,
  2831. (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
  2832. AWDChannelGroup);
  2833. }
  2834. /**
  2835. * @brief Get ADC analog watchdog monitored channel.
  2836. * @note Usage of the returned channel number:
  2837. * - To reinject this channel into another function LL_ADC_xxx:
  2838. * the returned channel number is only partly formatted on definition
  2839. * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
  2840. * with parts of literals LL_ADC_CHANNEL_x or using
  2841. * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2842. * Then the selected literal LL_ADC_CHANNEL_x can be used
  2843. * as parameter for another function.
  2844. * - To get the channel number in decimal format:
  2845. * process the returned value with the helper macro
  2846. * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
  2847. * Applicable only when the analog watchdog is set to monitor
  2848. * one channel.
  2849. * @note On this STM32 serie, there is only 1 kind of analog watchdog
  2850. * instance:
  2851. * - AWD standard (instance AWD1):
  2852. * - channels monitored: can monitor 1 channel or all channels.
  2853. * - groups monitored: ADC groups regular and-or injected.
  2854. * - resolution: resolution is not limited (corresponds to
  2855. * ADC resolution configured).
  2856. * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
  2857. * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
  2858. * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
  2859. * @param ADCx ADC instance
  2860. * @retval Returned value can be one of the following values:
  2861. * @arg @ref LL_ADC_AWD_DISABLE
  2862. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
  2863. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
  2864. * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  2865. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
  2866. * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
  2867. * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
  2868. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
  2869. * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
  2870. * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
  2871. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
  2872. * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
  2873. * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
  2874. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
  2875. * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
  2876. * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
  2877. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
  2878. * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
  2879. * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
  2880. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
  2881. * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
  2882. * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
  2883. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
  2884. * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
  2885. * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
  2886. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
  2887. * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
  2888. * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
  2889. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
  2890. * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
  2891. * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
  2892. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
  2893. * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
  2894. * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
  2895. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
  2896. * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
  2897. * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
  2898. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
  2899. * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
  2900. * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
  2901. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
  2902. * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
  2903. * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
  2904. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
  2905. * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
  2906. * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
  2907. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
  2908. * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
  2909. * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
  2910. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
  2911. * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
  2912. * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
  2913. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
  2914. * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
  2915. * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
  2916. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
  2917. * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
  2918. * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
  2919. */
  2920. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
  2921. {
  2922. return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
  2923. }
  2924. /**
  2925. * @brief Set ADC analog watchdog threshold value of threshold
  2926. * high or low.
  2927. * @note On this STM32 serie, there is only 1 kind of analog watchdog
  2928. * instance:
  2929. * - AWD standard (instance AWD1):
  2930. * - channels monitored: can monitor 1 channel or all channels.
  2931. * - groups monitored: ADC groups regular and-or injected.
  2932. * - resolution: resolution is not limited (corresponds to
  2933. * ADC resolution configured).
  2934. * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
  2935. * LTR LT LL_ADC_SetAnalogWDThresholds
  2936. * @param ADCx ADC instance
  2937. * @param AWDThresholdsHighLow This parameter can be one of the following values:
  2938. * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
  2939. * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
  2940. * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
  2941. * @retval None
  2942. */
  2943. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
  2944. {
  2945. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
  2946. MODIFY_REG(*preg,
  2947. ADC_HTR_HT,
  2948. AWDThresholdValue);
  2949. }
  2950. /**
  2951. * @brief Get ADC analog watchdog threshold value of threshold high or
  2952. * threshold low.
  2953. * @note In case of ADC resolution different of 12 bits,
  2954. * analog watchdog thresholds data require a specific shift.
  2955. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
  2956. * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
  2957. * LTR LT LL_ADC_GetAnalogWDThresholds
  2958. * @param ADCx ADC instance
  2959. * @param AWDThresholdsHighLow This parameter can be one of the following values:
  2960. * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
  2961. * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
  2962. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  2963. */
  2964. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
  2965. {
  2966. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
  2967. return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
  2968. }
  2969. /**
  2970. * @}
  2971. */
  2972. /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
  2973. * @{
  2974. */
  2975. #if defined(ADC_MULTIMODE_SUPPORT)
  2976. /**
  2977. * @brief Set ADC multimode configuration to operate in independent mode
  2978. * or multimode (for devices with several ADC instances).
  2979. * @note If multimode configuration: the selected ADC instance is
  2980. * either master or slave depending on hardware.
  2981. * Refer to reference manual.
  2982. * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode
  2983. * @param ADCxy_COMMON ADC common instance
  2984. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  2985. * @param Multimode This parameter can be one of the following values:
  2986. * @arg @ref LL_ADC_MULTI_INDEPENDENT
  2987. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
  2988. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
  2989. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
  2990. * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
  2991. * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
  2992. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  2993. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  2994. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
  2995. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
  2996. * @retval None
  2997. */
  2998. __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
  2999. {
  3000. MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
  3001. }
  3002. /**
  3003. * @brief Get ADC multimode configuration to operate in independent mode
  3004. * or multimode (for devices with several ADC instances).
  3005. * @note If multimode configuration: the selected ADC instance is
  3006. * either master or slave depending on hardware.
  3007. * Refer to reference manual.
  3008. * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode
  3009. * @param ADCxy_COMMON ADC common instance
  3010. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3011. * @retval Returned value can be one of the following values:
  3012. * @arg @ref LL_ADC_MULTI_INDEPENDENT
  3013. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
  3014. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
  3015. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
  3016. * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
  3017. * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
  3018. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  3019. * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  3020. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
  3021. * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
  3022. */
  3023. __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
  3024. {
  3025. return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
  3026. }
  3027. #endif /* ADC_MULTIMODE_SUPPORT */
  3028. /**
  3029. * @}
  3030. */
  3031. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
  3032. * @{
  3033. */
  3034. /**
  3035. * @brief Enable the selected ADC instance.
  3036. * @note On this STM32 serie, after ADC enable, a delay for
  3037. * ADC internal analog stabilization is required before performing a
  3038. * ADC conversion start.
  3039. * Refer to device datasheet, parameter tSTAB.
  3040. * @rmtoll CR2 ADON LL_ADC_Enable
  3041. * @param ADCx ADC instance
  3042. * @retval None
  3043. */
  3044. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
  3045. {
  3046. SET_BIT(ADCx->CR2, ADC_CR2_ADON);
  3047. }
  3048. /**
  3049. * @brief Disable the selected ADC instance.
  3050. * @rmtoll CR2 ADON LL_ADC_Disable
  3051. * @param ADCx ADC instance
  3052. * @retval None
  3053. */
  3054. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
  3055. {
  3056. CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
  3057. }
  3058. /**
  3059. * @brief Get the selected ADC instance enable state.
  3060. * @rmtoll CR2 ADON LL_ADC_IsEnabled
  3061. * @param ADCx ADC instance
  3062. * @retval 0: ADC is disabled, 1: ADC is enabled.
  3063. */
  3064. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
  3065. {
  3066. return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
  3067. }
  3068. /**
  3069. * @brief Start ADC calibration in the mode single-ended
  3070. * or differential (for devices with differential mode available).
  3071. * @note On this STM32 serie, before starting a calibration,
  3072. * ADC must be disabled.
  3073. * A minimum number of ADC clock cycles are required
  3074. * between ADC disable state and calibration start.
  3075. * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
  3076. * @note On this STM32 serie, hardware prerequisite before starting a calibration:
  3077. the ADC must have been in power-on state for at least
  3078. two ADC clock cycles.
  3079. * @rmtoll CR2 CAL LL_ADC_StartCalibration
  3080. * @param ADCx ADC instance
  3081. * @retval None
  3082. */
  3083. __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
  3084. {
  3085. SET_BIT(ADCx->CR2, ADC_CR2_CAL);
  3086. }
  3087. /**
  3088. * @brief Get ADC calibration state.
  3089. * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
  3090. * @param ADCx ADC instance
  3091. * @retval 0: calibration complete, 1: calibration in progress.
  3092. */
  3093. __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
  3094. {
  3095. return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
  3096. }
  3097. /**
  3098. * @}
  3099. */
  3100. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
  3101. * @{
  3102. */
  3103. /**
  3104. * @brief Start ADC group regular conversion.
  3105. * @note On this STM32 serie, this function is relevant only for
  3106. * internal trigger (SW start), not for external trigger:
  3107. * - If ADC trigger has been set to software start, ADC conversion
  3108. * starts immediately.
  3109. * - If ADC trigger has been set to external trigger, ADC conversion
  3110. * start must be performed using function
  3111. * @ref LL_ADC_REG_StartConversionExtTrig().
  3112. * (if external trigger edge would have been set during ADC other
  3113. * settings, ADC conversion would start at trigger event
  3114. * as soon as ADC is enabled).
  3115. * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
  3116. * @param ADCx ADC instance
  3117. * @retval None
  3118. */
  3119. __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
  3120. {
  3121. SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
  3122. }
  3123. /**
  3124. * @brief Start ADC group regular conversion from external trigger.
  3125. * @note ADC conversion will start at next trigger event (on the selected
  3126. * trigger edge) following the ADC start conversion command.
  3127. * @note On this STM32 serie, this function is relevant for
  3128. * ADC conversion start from external trigger.
  3129. * If internal trigger (SW start) is needed, perform ADC conversion
  3130. * start using function @ref LL_ADC_REG_StartConversionSWStart().
  3131. * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
  3132. * @param ExternalTriggerEdge This parameter can be one of the following values:
  3133. * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
  3134. * @param ADCx ADC instance
  3135. * @retval None
  3136. */
  3137. __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
  3138. {
  3139. SET_BIT(ADCx->CR2, ExternalTriggerEdge);
  3140. }
  3141. /**
  3142. * @brief Stop ADC group regular conversion from external trigger.
  3143. * @note No more ADC conversion will start at next trigger event
  3144. * following the ADC stop conversion command.
  3145. * If a conversion is on-going, it will be completed.
  3146. * @note On this STM32 serie, there is no specific command
  3147. * to stop a conversion on-going or to stop ADC converting
  3148. * in continuous mode. These actions can be performed
  3149. * using function @ref LL_ADC_Disable().
  3150. * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
  3151. * @param ADCx ADC instance
  3152. * @retval None
  3153. */
  3154. __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
  3155. {
  3156. CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG);
  3157. }
  3158. /**
  3159. * @brief Get ADC group regular conversion data, range fit for
  3160. * all ADC configurations: all ADC resolutions and
  3161. * all oversampling increased data width (for devices
  3162. * with feature oversampling).
  3163. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
  3164. * @param ADCx ADC instance
  3165. * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
  3166. */
  3167. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
  3168. {
  3169. return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
  3170. }
  3171. /**
  3172. * @brief Get ADC group regular conversion data, range fit for
  3173. * ADC resolution 12 bits.
  3174. * @note For devices with feature oversampling: Oversampling
  3175. * can increase data width, function for extended range
  3176. * may be needed: @ref LL_ADC_REG_ReadConversionData32.
  3177. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
  3178. * @param ADCx ADC instance
  3179. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  3180. */
  3181. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
  3182. {
  3183. return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
  3184. }
  3185. #if defined(ADC_MULTIMODE_SUPPORT)
  3186. /**
  3187. * @brief Get ADC multimode conversion data of ADC master, ADC slave
  3188. * or raw data with ADC master and slave concatenated.
  3189. * @note If raw data with ADC master and slave concatenated is retrieved,
  3190. * a macro is available to get the conversion data of
  3191. * ADC master or ADC slave: see helper macro
  3192. * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
  3193. * (however this macro is mainly intended for multimode
  3194. * transfer by DMA, because this function can do the same
  3195. * by getting multimode conversion data of ADC master or ADC slave
  3196. * separately).
  3197. * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n
  3198. * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
  3199. * @param ADCx ADC instance
  3200. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3201. * @param ConversionData This parameter can be one of the following values:
  3202. * @arg @ref LL_ADC_MULTI_MASTER
  3203. * @arg @ref LL_ADC_MULTI_SLAVE
  3204. * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
  3205. * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
  3206. */
  3207. __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
  3208. {
  3209. return (uint32_t)(READ_BIT(ADCx->DR,
  3210. ADC_DR_ADC2DATA)
  3211. >> POSITION_VAL(ConversionData)
  3212. );
  3213. }
  3214. #endif /* ADC_MULTIMODE_SUPPORT */
  3215. /**
  3216. * @}
  3217. */
  3218. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
  3219. * @{
  3220. */
  3221. /**
  3222. * @brief Start ADC group injected conversion.
  3223. * @note On this STM32 serie, this function is relevant only for
  3224. * internal trigger (SW start), not for external trigger:
  3225. * - If ADC trigger has been set to software start, ADC conversion
  3226. * starts immediately.
  3227. * - If ADC trigger has been set to external trigger, ADC conversion
  3228. * start must be performed using function
  3229. * @ref LL_ADC_INJ_StartConversionExtTrig().
  3230. * (if external trigger edge would have been set during ADC other
  3231. * settings, ADC conversion would start at trigger event
  3232. * as soon as ADC is enabled).
  3233. * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
  3234. * @param ADCx ADC instance
  3235. * @retval None
  3236. */
  3237. __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
  3238. {
  3239. SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
  3240. }
  3241. /**
  3242. * @brief Start ADC group injected conversion from external trigger.
  3243. * @note ADC conversion will start at next trigger event (on the selected
  3244. * trigger edge) following the ADC start conversion command.
  3245. * @note On this STM32 serie, this function is relevant for
  3246. * ADC conversion start from external trigger.
  3247. * If internal trigger (SW start) is needed, perform ADC conversion
  3248. * start using function @ref LL_ADC_INJ_StartConversionSWStart().
  3249. * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
  3250. * @param ExternalTriggerEdge This parameter can be one of the following values:
  3251. * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
  3252. * @param ADCx ADC instance
  3253. * @retval None
  3254. */
  3255. __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
  3256. {
  3257. SET_BIT(ADCx->CR2, ExternalTriggerEdge);
  3258. }
  3259. /**
  3260. * @brief Stop ADC group injected conversion from external trigger.
  3261. * @note No more ADC conversion will start at next trigger event
  3262. * following the ADC stop conversion command.
  3263. * If a conversion is on-going, it will be completed.
  3264. * @note On this STM32 serie, there is no specific command
  3265. * to stop a conversion on-going or to stop ADC converting
  3266. * in continuous mode. These actions can be performed
  3267. * using function @ref LL_ADC_Disable().
  3268. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
  3269. * @param ADCx ADC instance
  3270. * @retval None
  3271. */
  3272. __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
  3273. {
  3274. CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG);
  3275. }
  3276. /**
  3277. * @brief Get ADC group regular conversion data, range fit for
  3278. * all ADC configurations: all ADC resolutions and
  3279. * all oversampling increased data width (for devices
  3280. * with feature oversampling).
  3281. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
  3282. * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
  3283. * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
  3284. * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
  3285. * @param ADCx ADC instance
  3286. * @param Rank This parameter can be one of the following values:
  3287. * @arg @ref LL_ADC_INJ_RANK_1
  3288. * @arg @ref LL_ADC_INJ_RANK_2
  3289. * @arg @ref LL_ADC_INJ_RANK_3
  3290. * @arg @ref LL_ADC_INJ_RANK_4
  3291. * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
  3292. */
  3293. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
  3294. {
  3295. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
  3296. return (uint32_t)(READ_BIT(*preg,
  3297. ADC_JDR1_JDATA)
  3298. );
  3299. }
  3300. /**
  3301. * @brief Get ADC group injected conversion data, range fit for
  3302. * ADC resolution 12 bits.
  3303. * @note For devices with feature oversampling: Oversampling
  3304. * can increase data width, function for extended range
  3305. * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
  3306. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
  3307. * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
  3308. * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
  3309. * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
  3310. * @param ADCx ADC instance
  3311. * @param Rank This parameter can be one of the following values:
  3312. * @arg @ref LL_ADC_INJ_RANK_1
  3313. * @arg @ref LL_ADC_INJ_RANK_2
  3314. * @arg @ref LL_ADC_INJ_RANK_3
  3315. * @arg @ref LL_ADC_INJ_RANK_4
  3316. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  3317. */
  3318. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
  3319. {
  3320. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
  3321. return (uint16_t)(READ_BIT(*preg,
  3322. ADC_JDR1_JDATA)
  3323. );
  3324. }
  3325. /**
  3326. * @}
  3327. */
  3328. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
  3329. * @{
  3330. */
  3331. /**
  3332. * @brief Get flag ADC group regular end of sequence conversions.
  3333. * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
  3334. * @param ADCx ADC instance
  3335. * @retval State of bit (1 or 0).
  3336. */
  3337. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
  3338. {
  3339. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3340. /* end of unitary conversion. */
  3341. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3342. /* in other STM32 families). */
  3343. return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
  3344. }
  3345. /**
  3346. * @brief Get flag ADC group injected end of sequence conversions.
  3347. * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
  3348. * @param ADCx ADC instance
  3349. * @retval State of bit (1 or 0).
  3350. */
  3351. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
  3352. {
  3353. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3354. /* end of unitary conversion. */
  3355. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3356. /* in other STM32 families). */
  3357. return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
  3358. }
  3359. /**
  3360. * @brief Get flag ADC analog watchdog 1 flag
  3361. * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
  3362. * @param ADCx ADC instance
  3363. * @retval State of bit (1 or 0).
  3364. */
  3365. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
  3366. {
  3367. return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
  3368. }
  3369. /**
  3370. * @brief Clear flag ADC group regular end of sequence conversions.
  3371. * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
  3372. * @param ADCx ADC instance
  3373. * @retval None
  3374. */
  3375. __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
  3376. {
  3377. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3378. /* end of unitary conversion. */
  3379. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3380. /* in other STM32 families). */
  3381. WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
  3382. }
  3383. /**
  3384. * @brief Clear flag ADC group injected end of sequence conversions.
  3385. * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
  3386. * @param ADCx ADC instance
  3387. * @retval None
  3388. */
  3389. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
  3390. {
  3391. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3392. /* end of unitary conversion. */
  3393. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3394. /* in other STM32 families). */
  3395. WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
  3396. }
  3397. /**
  3398. * @brief Clear flag ADC analog watchdog 1.
  3399. * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
  3400. * @param ADCx ADC instance
  3401. * @retval None
  3402. */
  3403. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
  3404. {
  3405. WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
  3406. }
  3407. #if defined(ADC_MULTIMODE_SUPPORT)
  3408. /**
  3409. * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
  3410. * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS
  3411. * @param ADCxy_COMMON ADC common instance
  3412. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3413. * @retval State of bit (1 or 0).
  3414. */
  3415. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
  3416. {
  3417. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3418. /* end of unitary conversion. */
  3419. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3420. /* in other STM32 families). */
  3421. return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
  3422. }
  3423. /**
  3424. * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
  3425. * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS
  3426. * @param ADCxy_COMMON ADC common instance
  3427. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3428. * @retval State of bit (1 or 0).
  3429. */
  3430. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
  3431. {
  3432. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3433. /* end of unitary conversion. */
  3434. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3435. /* in other STM32 families). */
  3436. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
  3437. return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
  3438. }
  3439. /**
  3440. * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
  3441. * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
  3442. * @param ADCxy_COMMON ADC common instance
  3443. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3444. * @retval State of bit (1 or 0).
  3445. */
  3446. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
  3447. {
  3448. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3449. /* end of unitary conversion. */
  3450. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3451. /* in other STM32 families). */
  3452. return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
  3453. }
  3454. /**
  3455. * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
  3456. * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
  3457. * @param ADCxy_COMMON ADC common instance
  3458. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3459. * @retval State of bit (1 or 0).
  3460. */
  3461. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
  3462. {
  3463. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3464. /* end of unitary conversion. */
  3465. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3466. /* in other STM32 families). */
  3467. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
  3468. return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
  3469. }
  3470. /**
  3471. * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
  3472. * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1
  3473. * @param ADCxy_COMMON ADC common instance
  3474. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3475. * @retval State of bit (1 or 0).
  3476. */
  3477. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
  3478. {
  3479. return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
  3480. }
  3481. /**
  3482. * @brief Get flag multimode analog watchdog 1 of the ADC slave.
  3483. * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
  3484. * @param ADCxy_COMMON ADC common instance
  3485. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  3486. * @retval State of bit (1 or 0).
  3487. */
  3488. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
  3489. {
  3490. register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
  3491. return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
  3492. }
  3493. #endif /* ADC_MULTIMODE_SUPPORT */
  3494. /**
  3495. * @}
  3496. */
  3497. /** @defgroup ADC_LL_EF_IT_Management ADC IT management
  3498. * @{
  3499. */
  3500. /**
  3501. * @brief Enable interruption ADC group regular end of sequence conversions.
  3502. * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
  3503. * @param ADCx ADC instance
  3504. * @retval None
  3505. */
  3506. __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
  3507. {
  3508. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3509. /* end of unitary conversion. */
  3510. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3511. /* in other STM32 families). */
  3512. SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
  3513. }
  3514. /**
  3515. * @brief Enable interruption ADC group injected end of sequence conversions.
  3516. * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
  3517. * @param ADCx ADC instance
  3518. * @retval None
  3519. */
  3520. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
  3521. {
  3522. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3523. /* end of unitary conversion. */
  3524. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3525. /* in other STM32 families). */
  3526. SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
  3527. }
  3528. /**
  3529. * @brief Enable interruption ADC analog watchdog 1.
  3530. * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
  3531. * @param ADCx ADC instance
  3532. * @retval None
  3533. */
  3534. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
  3535. {
  3536. SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
  3537. }
  3538. /**
  3539. * @brief Disable interruption ADC group regular end of sequence conversions.
  3540. * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
  3541. * @param ADCx ADC instance
  3542. * @retval None
  3543. */
  3544. __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
  3545. {
  3546. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3547. /* end of unitary conversion. */
  3548. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3549. /* in other STM32 families). */
  3550. CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
  3551. }
  3552. /**
  3553. * @brief Disable interruption ADC group injected end of sequence conversions.
  3554. * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
  3555. * @param ADCx ADC instance
  3556. * @retval None
  3557. */
  3558. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
  3559. {
  3560. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3561. /* end of unitary conversion. */
  3562. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3563. /* in other STM32 families). */
  3564. CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
  3565. }
  3566. /**
  3567. * @brief Disable interruption ADC analog watchdog 1.
  3568. * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
  3569. * @param ADCx ADC instance
  3570. * @retval None
  3571. */
  3572. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
  3573. {
  3574. CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
  3575. }
  3576. /**
  3577. * @brief Get state of interruption ADC group regular end of sequence conversions
  3578. * (0: interrupt disabled, 1: interrupt enabled).
  3579. * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
  3580. * @param ADCx ADC instance
  3581. * @retval State of bit (1 or 0).
  3582. */
  3583. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
  3584. {
  3585. /* Note: on this STM32 serie, there is no flag ADC group regular */
  3586. /* end of unitary conversion. */
  3587. /* Flag noted as "EOC" is corresponding to flag "EOS" */
  3588. /* in other STM32 families). */
  3589. return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
  3590. }
  3591. /**
  3592. * @brief Get state of interruption ADC group injected end of sequence conversions
  3593. * (0: interrupt disabled, 1: interrupt enabled).
  3594. * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
  3595. * @param ADCx ADC instance
  3596. * @retval State of bit (1 or 0).
  3597. */
  3598. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
  3599. {
  3600. /* Note: on this STM32 serie, there is no flag ADC group injected */
  3601. /* end of unitary conversion. */
  3602. /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
  3603. /* in other STM32 families). */
  3604. return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
  3605. }
  3606. /**
  3607. * @brief Get state of interruption ADC analog watchdog 1
  3608. * (0: interrupt disabled, 1: interrupt enabled).
  3609. * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
  3610. * @param ADCx ADC instance
  3611. * @retval State of bit (1 or 0).
  3612. */
  3613. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
  3614. {
  3615. return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
  3616. }
  3617. /**
  3618. * @}
  3619. */
  3620. #if defined(USE_FULL_LL_DRIVER)
  3621. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
  3622. * @{
  3623. */
  3624. /* Initialization of some features of ADC common parameters and multimode */
  3625. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
  3626. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
  3627. void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
  3628. /* De-initialization of ADC instance, ADC group regular and ADC group injected */
  3629. /* (availability of ADC group injected depends on STM32 families) */
  3630. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
  3631. /* Initialization of some features of ADC instance */
  3632. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
  3633. void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
  3634. /* Initialization of some features of ADC instance and ADC group regular */
  3635. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
  3636. void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
  3637. /* Initialization of some features of ADC instance and ADC group injected */
  3638. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
  3639. void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
  3640. /**
  3641. * @}
  3642. */
  3643. #endif /* USE_FULL_LL_DRIVER */
  3644. /**
  3645. * @}
  3646. */
  3647. /**
  3648. * @}
  3649. */
  3650. #endif /* ADC1 || ADC2 || ADC3 */
  3651. /**
  3652. * @}
  3653. */
  3654. #ifdef __cplusplus
  3655. }
  3656. #endif
  3657. #endif /* __STM32F1xx_LL_ADC_H */
  3658. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/