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# Conflicts:
#	MyDrivers/Timer.c
#	MyDrivers/Timer.h
#	Services/RFReceiver.c
This commit is contained in:
Yohan Simard 2020-11-16 18:55:44 +01:00
commit 542722584d
41 changed files with 180 additions and 4408 deletions
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18
.gitignore vendored
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/
*.o
*.d
*.crf
!/README.md
!/Src/
!/Services/
!/MyDrivers/
!/LLDrivers/
/MDK-ARM/
!/Inc
!/.gitignore
/MDK-ARM/DebugConfig
/MDK-ARM/RTE
/MDK-ARM/NUCLEO-F103RB
/MDK-ARM/Project.uvguix.*
/MDK-ARM/EventRecorderStub.scvd
/MDK-ARM/startup_stm32f103xb.lst

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MDK-ARM/DebugConfig/NUCLEO-F103RB_STM32F103RB_1.0.0.dbgconf
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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

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MDK-ARM/DebugConfig/Simulateur_STM32F103RB_1.0.0.dbgconf
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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

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MDK-ARM/NUCLEO-F103RB/ExtDll.iex
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[EXTDLL]
Count=0

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MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.build_log.htm
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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.31.0.0
Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Toyoste Biencuit, a, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.31.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.31.0.0
Dialog DLL: DARMSTM.DLL V1.68.0.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.7.0
Dialog DLL: TARMSTM.DLL V1.66.0.0
<h2>Project:</h2>
C:\users\vergnet\My Documents\INSA\4A\Info Mat\projet_voilier\MDK-ARM\Project.uvprojx
Project File Date: 10/19/2020
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'Simulateur'
linking...
Program Size: Code=1464 RO-data=268 RW-data=28 ZI-data=1028
"NUCLEO-F103RB\NUCLEO-F103RB.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
ARM.CMSIS.5.7.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.4.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
Keil.STM32F1xx_DFP.2.3.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_Simulateur
C:\ARM\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
C:\ARM\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.4.0
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>

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MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.map
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Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]
==============================================================================
Section Cross References
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_Init1msTick) for LL_Init1msTick
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
main.o(i.main) refers to main.o(i.SystemClock_Config) for SystemClock_Config
main.o(i.main) refers to chrono.o(i.Chrono_Conf) for Chrono_Conf
main.o(i.main) refers to chrono.o(i.Chrono_Start) for Chrono_Start
chrono.o(i.Chrono_Conf) refers to timer.o(i.MyTimer_Conf) for MyTimer_Conf
chrono.o(i.Chrono_Conf) refers to timer.o(i.MyTimer_IT_Conf) for MyTimer_IT_Conf
chrono.o(i.Chrono_Conf) refers to timer.o(i.MyTimer_IT_Enable) for MyTimer_IT_Enable
chrono.o(i.Chrono_Conf) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Conf) refers to chrono.o(i.Chrono_Task_10ms) for Chrono_Task_10ms
chrono.o(i.Chrono_Read) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Reset) refers to timer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Reset) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Start) refers to timer.o(i.MyTimer_Start) for MyTimer_Start
chrono.o(i.Chrono_Start) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Stop) refers to timer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Stop) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Task_10ms) refers to chrono.o(.data) for Chrono_Time
timer.o(i.MyTimer_Conf) refers to timer.o(i.LL_APB1_GRP1_EnableClock) for LL_APB1_GRP1_EnableClock
timer.o(i.MyTimer_Conf) refers to stm32f1xx_ll_tim.o(i.LL_TIM_Init) for LL_TIM_Init
timer.o(i.MyTimer_Conf) refers to timer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
timer.o(i.MyTimer_Conf) refers to timer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
timer.o(i.MyTimer_IT_Conf) refers to timer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
timer.o(i.MyTimer_IT_Conf) refers to timer.o(.data) for Ptr_ItFct_TIM1
timer.o(i.MyTimer_IT_Disable) refers to timer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
timer.o(i.MyTimer_Stop) refers to timer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
timer.o(i.TIM1_UP_IRQHandler) refers to timer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
timer.o(i.TIM1_UP_IRQHandler) refers to timer.o(.data) for Ptr_ItFct_TIM1
timer.o(i.TIM2_IRQHandler) refers to timer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
timer.o(i.TIM2_IRQHandler) refers to timer.o(.data) for Ptr_ItFct_TIM2
timer.o(i.TIM3_IRQHandler) refers to timer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
timer.o(i.TIM3_IRQHandler) refers to timer.o(.data) for Ptr_ItFct_TIM3
timer.o(i.TIM4_IRQHandler) refers to timer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
timer.o(i.TIM4_IRQHandler) refers to timer.o(.data) for Ptr_ItFct_TIM4
stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) for RCC_GetPCLK1ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady) for LL_RCC_HSE_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady) for LL_RCC_HSI_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency) for UTILS_SetFlashLatency
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_tim.o(i.IC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC4Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset) for LL_APB1_GRP1_ForceReset
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset) for LL_APB1_GRP1_ReleaseReset
stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC1Config) for IC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC2Config) for IC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC3Config) for IC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC4Config) for IC4Config
stm32f1xx_ll_tim.o(i.LL_TIM_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC1Config) for OC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC2Config) for OC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC3Config) for OC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC4Config) for OC4Config
stm32f1xx_ll_tim.o(i.OC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.OC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC4Config) refers to main.o(i.assert_failed) for assert_failed
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.data) for SystemCoreClock
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(STACK) for __initial_sp
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(.text) for Reset_Handler
startup_stm32f103xb.o(RESET) refers to timer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
startup_stm32f103xb.o(RESET) refers to timer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
startup_stm32f103xb.o(RESET) refers to timer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
startup_stm32f103xb.o(RESET) refers to timer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
startup_stm32f103xb.o(.text) refers to system_stm32f1xx.o(i.SystemInit) for SystemInit
startup_stm32f103xb.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main
entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main
init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
==============================================================================
Removing Unused input sections from the image.
Removing main.o(.rev16_text), (4 bytes).
Removing main.o(.revsh_text), (4 bytes).
Removing main.o(.rrx_text), (6 bytes).
Removing chrono.o(.rev16_text), (4 bytes).
Removing chrono.o(.revsh_text), (4 bytes).
Removing chrono.o(.rrx_text), (6 bytes).
Removing chrono.o(i.Chrono_Read), (8 bytes).
Removing chrono.o(i.Chrono_Reset), (32 bytes).
Removing chrono.o(i.Chrono_Stop), (16 bytes).
Removing timer.o(.rev16_text), (4 bytes).
Removing timer.o(.revsh_text), (4 bytes).
Removing timer.o(.rrx_text), (6 bytes).
Removing timer.o(i.MyTimer_IT_Disable), (12 bytes).
Removing timer.o(i.MyTimer_Stop), (12 bytes).
Removing timer.o(.constdata), (35 bytes).
Removing stm32f1xx_ll_rcc.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit), (152 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq), (124 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq), (120 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq), (32 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq), (60 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS), (88 bytes).
Removing stm32f1xx_ll_utils.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE), (260 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI), (104 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS), (28 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_mDelay), (40 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem), (416 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency), (228 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency), (80 bytes).
Removing stm32f1xx_ll_tim.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_tim.o(i.IC1Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC2Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC3Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.IC4Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init), (312 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_DeInit), (192 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init), (688 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_StructInit), (36 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init), (396 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_StructInit), (12 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2), (4 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_StructInit), (20 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.OC1Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC2Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC3Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC4Config), (372 bytes).
Removing stm32f1xx_ll_tim.o(.constdata), (35 bytes).
Removing system_stm32f1xx.o(.rev16_text), (4 bytes).
Removing system_stm32f1xx.o(.revsh_text), (4 bytes).
Removing system_stm32f1xx.o(.rrx_text), (6 bytes).
Removing system_stm32f1xx.o(i.SystemCoreClockUpdate), (164 bytes).
Removing system_stm32f1xx.o(.constdata), (24 bytes).
Removing startup_stm32f103xb.o(HEAP), (512 bytes).
75 unused section(s) (total 7894 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../Src/main.c 0x00000000 Number 0 main.o ABSOLUTE
../Src/system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\MyDrivers\ADC.c 0x00000000 Number 0 adc.o ABSOLUTE
..\MyDrivers\GPIO.c 0x00000000 Number 0 gpio.o ABSOLUTE
..\MyDrivers\Timer.c 0x00000000 Number 0 timer.o ABSOLUTE
..\MyDrivers\USART.c 0x00000000 Number 0 usart.o ABSOLUTE
..\Services\Accelerometer.c 0x00000000 Number 0 accelerometer.o ABSOLUTE
..\Services\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
..\Services\DCMotor.c 0x00000000 Number 0 dcmotor.o ABSOLUTE
..\Services\IncrementalEncoder.c 0x00000000 Number 0 incrementalencoder.o ABSOLUTE
..\Services\RFEmitter.c 0x00000000 Number 0 rfemitter.o ABSOLUTE
..\Services\RFReceiver.c 0x00000000 Number 0 rfreceiver.o ABSOLUTE
..\Services\ServoMotor.c 0x00000000 Number 0 servomotor.o ABSOLUTE
..\Services\Voltage.c 0x00000000 Number 0 voltage.o ABSOLUTE
..\Src\Display.c 0x00000000 Number 0 display.o ABSOLUTE
..\Src\Orientation.c 0x00000000 Number 0 orientation.o ABSOLUTE
..\Src\Roll.c 0x00000000 Number 0 roll.o ABSOLUTE
..\Src\Sail.c 0x00000000 Number 0 sail.o ABSOLUTE
..\Src\main.c 0x00000000 Number 0 main.o ABSOLUTE
..\Src\system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\\MyDrivers\\Timer.c 0x00000000 Number 0 timer.o ABSOLUTE
..\\Services\\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
init.s 0x00000000 Number 0 init.o ABSOLUTE
startup_stm32f103xb.s 0x00000000 Number 0 startup_stm32f103xb.o ABSOLUTE
RESET 0x08000000 Section 236 startup_stm32f103xb.o(RESET)
.ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
.ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
.ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
.ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
.ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
.ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
.ARM.Collect$$$$0000000D 0x080000fc Section 0 entry10a.o(.ARM.Collect$$$$0000000D)
.ARM.Collect$$$$0000000F 0x080000fc Section 0 entry11a.o(.ARM.Collect$$$$0000000F)
.ARM.Collect$$$$00002712 0x080000fc Section 4 entry2.o(.ARM.Collect$$$$00002712)
__lit__00000000 0x080000fc Data 4 entry2.o(.ARM.Collect$$$$00002712)
.text 0x08000100 Section 36 startup_stm32f103xb.o(.text)
.text 0x08000124 Section 36 init.o(.text)
i.Chrono_Conf 0x08000148 Section 0 chrono.o(i.Chrono_Conf)
i.Chrono_Start 0x0800018c Section 0 chrono.o(i.Chrono_Start)
i.Chrono_Task_10ms 0x0800019c Section 0 chrono.o(i.Chrono_Task_10ms)
i.LL_APB1_GRP1_EnableClock 0x080001e4 Section 0 timer.o(i.LL_APB1_GRP1_EnableClock)
LL_APB1_GRP1_EnableClock 0x080001e5 Thumb Code 24 timer.o(i.LL_APB1_GRP1_EnableClock)
i.LL_Init1msTick 0x08000200 Section 0 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
i.LL_SetSystemCoreClock 0x0800021c Section 0 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
i.LL_TIM_ClearFlag_UPDATE 0x08000228 Section 0 timer.o(i.LL_TIM_ClearFlag_UPDATE)
LL_TIM_ClearFlag_UPDATE 0x08000229 Thumb Code 8 timer.o(i.LL_TIM_ClearFlag_UPDATE)
i.LL_TIM_DisableCounter 0x08000230 Section 0 timer.o(i.LL_TIM_DisableCounter)
LL_TIM_DisableCounter 0x08000231 Thumb Code 10 timer.o(i.LL_TIM_DisableCounter)
i.LL_TIM_DisableIT_UPDATE 0x0800023a Section 0 timer.o(i.LL_TIM_DisableIT_UPDATE)
LL_TIM_DisableIT_UPDATE 0x0800023b Thumb Code 10 timer.o(i.LL_TIM_DisableIT_UPDATE)
i.LL_TIM_Init 0x08000244 Section 0 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
i.MyTimer_Conf 0x08000358 Section 0 timer.o(i.MyTimer_Conf)
i.MyTimer_IT_Conf 0x080003dc Section 0 timer.o(i.MyTimer_IT_Conf)
i.MyTimer_IT_Enable 0x080004a4 Section 0 timer.o(i.MyTimer_IT_Enable)
i.MyTimer_Start 0x080004b2 Section 0 timer.o(i.MyTimer_Start)
i.SystemClock_Config 0x080004c0 Section 0 main.o(i.SystemClock_Config)
i.SystemInit 0x080005b0 Section 0 system_stm32f1xx.o(i.SystemInit)
i.TIM1_UP_IRQHandler 0x08000608 Section 0 timer.o(i.TIM1_UP_IRQHandler)
i.TIM2_IRQHandler 0x08000620 Section 0 timer.o(i.TIM2_IRQHandler)
i.TIM3_IRQHandler 0x08000638 Section 0 timer.o(i.TIM3_IRQHandler)
i.TIM4_IRQHandler 0x08000650 Section 0 timer.o(i.TIM4_IRQHandler)
i.__scatterload_copy 0x08000668 Section 14 handlers.o(i.__scatterload_copy)
i.__scatterload_null 0x08000676 Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x08000678 Section 14 handlers.o(i.__scatterload_zeroinit)
i.assert_failed 0x08000686 Section 0 main.o(i.assert_failed)
i.main 0x0800068c Section 0 main.o(i.main)
.data 0x20000000 Section 8 chrono.o(.data)
Chrono_Time 0x20000000 Data 3 chrono.o(.data)
Chrono_Timer 0x20000004 Data 4 chrono.o(.data)
.data 0x20000008 Section 16 timer.o(.data)
.data 0x20000018 Section 4 system_stm32f1xx.o(.data)
STACK 0x20000020 Section 1024 startup_stm32f103xb.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__decompress - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_microlib_exit - Undefined Weak Reference
__Vectors_Size 0x000000ec Number 0 startup_stm32f103xb.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_stm32f103xb.o(RESET)
__Vectors_End 0x080000ec Data 0 startup_stm32f103xb.o(RESET)
__main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
_main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
_main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
__main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
_main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
_main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
_main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
__rt_final_cpp 0x080000fd Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D)
__rt_final_exit 0x080000fd Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F)
Reset_Handler 0x08000101 Thumb Code 8 startup_stm32f103xb.o(.text)
NMI_Handler 0x08000109 Thumb Code 2 startup_stm32f103xb.o(.text)
HardFault_Handler 0x0800010b Thumb Code 2 startup_stm32f103xb.o(.text)
MemManage_Handler 0x0800010d Thumb Code 2 startup_stm32f103xb.o(.text)
BusFault_Handler 0x0800010f Thumb Code 2 startup_stm32f103xb.o(.text)
UsageFault_Handler 0x08000111 Thumb Code 2 startup_stm32f103xb.o(.text)
SVC_Handler 0x08000113 Thumb Code 2 startup_stm32f103xb.o(.text)
DebugMon_Handler 0x08000115 Thumb Code 2 startup_stm32f103xb.o(.text)
PendSV_Handler 0x08000117 Thumb Code 2 startup_stm32f103xb.o(.text)
SysTick_Handler 0x08000119 Thumb Code 2 startup_stm32f103xb.o(.text)
ADC1_2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_RX1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_SCE_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel6_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel7_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI15_10_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI9_5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
PVD_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RCC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_Alarm_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TAMPER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_BRK_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USBWakeUp_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_HP_CAN1_TX_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_LP_CAN1_RX0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
WWDG_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
__scatterload 0x08000125 Thumb Code 28 init.o(.text)
__scatterload_rt2 0x08000125 Thumb Code 0 init.o(.text)
Chrono_Conf 0x08000149 Thumb Code 54 chrono.o(i.Chrono_Conf)
Chrono_Start 0x0800018d Thumb Code 12 chrono.o(i.Chrono_Start)
Chrono_Task_10ms 0x0800019d Thumb Code 68 chrono.o(i.Chrono_Task_10ms)
LL_Init1msTick 0x08000201 Thumb Code 28 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
LL_SetSystemCoreClock 0x0800021d Thumb Code 6 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
LL_TIM_Init 0x08000245 Thumb Code 228 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
MyTimer_Conf 0x08000359 Thumb Code 118 timer.o(i.MyTimer_Conf)
MyTimer_IT_Conf 0x080003dd Thumb Code 166 timer.o(i.MyTimer_IT_Conf)
MyTimer_IT_Enable 0x080004a5 Thumb Code 14 timer.o(i.MyTimer_IT_Enable)
MyTimer_Start 0x080004b3 Thumb Code 14 timer.o(i.MyTimer_Start)
SystemClock_Config 0x080004c1 Thumb Code 226 main.o(i.SystemClock_Config)
SystemInit 0x080005b1 Thumb Code 70 system_stm32f1xx.o(i.SystemInit)
TIM1_UP_IRQHandler 0x08000609 Thumb Code 16 timer.o(i.TIM1_UP_IRQHandler)
TIM2_IRQHandler 0x08000621 Thumb Code 18 timer.o(i.TIM2_IRQHandler)
TIM3_IRQHandler 0x08000639 Thumb Code 16 timer.o(i.TIM3_IRQHandler)
TIM4_IRQHandler 0x08000651 Thumb Code 16 timer.o(i.TIM4_IRQHandler)
__scatterload_copy 0x08000669 Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x08000677 Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x08000679 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
assert_failed 0x08000687 Thumb Code 4 main.o(i.assert_failed)
main 0x0800068d Thumb Code 18 main.o(i.main)
Region$$Table$$Base 0x080006a4 Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x080006c4 Number 0 anon$$obj.o(Region$$Table)
Ptr_ItFct_TIM1 0x20000008 Data 4 timer.o(.data)
Ptr_ItFct_TIM2 0x2000000c Data 4 timer.o(.data)
Ptr_ItFct_TIM3 0x20000010 Data 4 timer.o(.data)
Ptr_ItFct_TIM4 0x20000014 Data 4 timer.o(.data)
SystemCoreClock 0x20000018 Data 4 system_stm32f1xx.o(.data)
__initial_sp 0x20000420 Data 0 startup_stm32f103xb.o(STACK)
==============================================================================
Memory Map of the image
Image Entry point : 0x080000ed
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000006e0, Max: 0x00020000, ABSOLUTE)
Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000006c4, Max: 0x00020000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x08000000 0x08000000 0x000000ec Data RO 753 RESET startup_stm32f103xb.o
0x080000ec 0x080000ec 0x00000000 Code RO 758 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
0x080000ec 0x080000ec 0x00000004 Code RO 761 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
0x080000f0 0x080000f0 0x00000004 Code RO 764 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
0x080000f4 0x080000f4 0x00000000 Code RO 766 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
0x080000f4 0x080000f4 0x00000000 Code RO 768 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
0x080000f4 0x080000f4 0x00000008 Code RO 769 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
0x080000fc 0x080000fc 0x00000000 Code RO 771 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o)
0x080000fc 0x080000fc 0x00000000 Code RO 773 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o)
0x080000fc 0x080000fc 0x00000004 Code RO 762 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
0x08000100 0x08000100 0x00000024 Code RO 754 .text startup_stm32f103xb.o
0x08000124 0x08000124 0x00000024 Code RO 775 .text mc_w.l(init.o)
0x08000148 0x08000148 0x00000044 Code RO 117 i.Chrono_Conf chrono.o
0x0800018c 0x0800018c 0x00000010 Code RO 120 i.Chrono_Start chrono.o
0x0800019c 0x0800019c 0x00000048 Code RO 122 i.Chrono_Task_10ms chrono.o
0x080001e4 0x080001e4 0x0000001c Code RO 239 i.LL_APB1_GRP1_EnableClock timer.o
0x08000200 0x08000200 0x0000001c Code RO 461 i.LL_Init1msTick stm32f1xx_ll_utils.o
0x0800021c 0x0800021c 0x0000000c Code RO 468 i.LL_SetSystemCoreClock stm32f1xx_ll_utils.o
0x08000228 0x08000228 0x00000008 Code RO 240 i.LL_TIM_ClearFlag_UPDATE timer.o
0x08000230 0x08000230 0x0000000a Code RO 241 i.LL_TIM_DisableCounter timer.o
0x0800023a 0x0800023a 0x0000000a Code RO 242 i.LL_TIM_DisableIT_UPDATE timer.o
0x08000244 0x08000244 0x00000114 Code RO 573 i.LL_TIM_Init stm32f1xx_ll_tim.o
0x08000358 0x08000358 0x00000084 Code RO 243 i.MyTimer_Conf timer.o
0x080003dc 0x080003dc 0x000000c8 Code RO 244 i.MyTimer_IT_Conf timer.o
0x080004a4 0x080004a4 0x0000000e Code RO 246 i.MyTimer_IT_Enable timer.o
0x080004b2 0x080004b2 0x0000000e Code RO 247 i.MyTimer_Start timer.o
0x080004c0 0x080004c0 0x000000f0 Code RO 4 i.SystemClock_Config main.o
0x080005b0 0x080005b0 0x00000058 Code RO 718 i.SystemInit system_stm32f1xx.o
0x08000608 0x08000608 0x00000018 Code RO 249 i.TIM1_UP_IRQHandler timer.o
0x08000620 0x08000620 0x00000018 Code RO 250 i.TIM2_IRQHandler timer.o
0x08000638 0x08000638 0x00000018 Code RO 251 i.TIM3_IRQHandler timer.o
0x08000650 0x08000650 0x00000018 Code RO 252 i.TIM4_IRQHandler timer.o
0x08000668 0x08000668 0x0000000e Code RO 779 i.__scatterload_copy mc_w.l(handlers.o)
0x08000676 0x08000676 0x00000002 Code RO 780 i.__scatterload_null mc_w.l(handlers.o)
0x08000678 0x08000678 0x0000000e Code RO 781 i.__scatterload_zeroinit mc_w.l(handlers.o)
0x08000686 0x08000686 0x00000004 Code RO 5 i.assert_failed main.o
0x0800068a 0x0800068a 0x00000002 PAD
0x0800068c 0x0800068c 0x00000018 Code RO 6 i.main main.o
0x080006a4 0x080006a4 0x00000020 Data RO 777 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080006c4, Size: 0x00000420, Max: 0x00005000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x20000000 0x080006c4 0x00000008 Data RW 123 .data chrono.o
0x20000008 0x080006cc 0x00000010 Data RW 254 .data timer.o
0x20000018 0x080006dc 0x00000004 Data RW 720 .data system_stm32f1xx.o
0x2000001c 0x080006e0 0x00000004 PAD
0x20000020 - 0x00000400 Zero RW 751 STACK startup_stm32f103xb.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
156 22 0 8 0 2000 chrono.o
268 20 0 0 0 356672 main.o
36 8 236 0 1024 780 startup_stm32f103xb.o
276 48 0 0 0 28994 stm32f1xx_ll_tim.o
40 6 0 0 0 2105 stm32f1xx_ll_utils.o
88 18 0 4 0 1171 system_stm32f1xx.o
512 82 0 16 0 59169 timer.o
----------------------------------------------------------------------
1378 204 268 28 1028 450891 Object Totals
0 0 32 0 0 0 (incl. Generated)
2 0 0 0 4 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
0 0 0 0 0 0 entry.o
0 0 0 0 0 0 entry10a.o
0 0 0 0 0 0 entry11a.o
8 4 0 0 0 0 entry2.o
4 0 0 0 0 0 entry5.o
0 0 0 0 0 0 entry7b.o
0 0 0 0 0 0 entry8b.o
8 4 0 0 0 0 entry9a.o
30 0 0 0 0 0 handlers.o
36 8 0 0 0 68 init.o
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
86 16 0 0 0 68 mc_w.l
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
1464 220 268 28 1028 450071 Grand Totals
1464 220 268 28 1028 450071 ELF Image Totals
1464 220 268 28 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 1732 ( 1.69kB)
Total RW Size (RW Data + ZI Data) 1056 ( 1.03kB)
Total ROM Size (Code + RO Data + RW Data) 1760 ( 1.72kB)
==============================================================================

16
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.sct
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@ -1,16 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00005000 { ; RW data
.ANY (+RW +ZI)
}
}

BIN
MDK-ARM/NUCLEO-F103RB/chrono.crf
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BIN
MDK-ARM/NUCLEO-F103RB/main.crf
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BIN
MDK-ARM/NUCLEO-F103RB/mytimer.crf
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BIN
MDK-ARM/NUCLEO-F103RB/stm32f1xx_it.crf
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2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_adc.d
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@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_adc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c
nucleo-f103rb\stm32f1xx_ll_adc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_crc.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_crc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c
nucleo-f103rb\stm32f1xx_ll_crc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dac.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_dac.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c
nucleo-f103rb\stm32f1xx_ll_dac.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dma.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_dma.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
nucleo-f103rb\stm32f1xx_ll_dma.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_exti.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_exti.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
nucleo-f103rb\stm32f1xx_ll_exti.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_gpio.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_gpio.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
nucleo-f103rb\stm32f1xx_ll_gpio.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_i2c.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_i2c.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c
nucleo-f103rb\stm32f1xx_ll_i2c.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_pwr.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_pwr.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
nucleo-f103rb\stm32f1xx_ll_pwr.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h

BIN
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_rcc.crf
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2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_rtc.d
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@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_rtc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c
nucleo-f103rb\stm32f1xx_ll_rtc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_spi.d
View file

@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_spi.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
nucleo-f103rb\stm32f1xx_ll_spi.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h

BIN
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_tim.crf
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Binary file not shown.

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_usart.d
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@ -1,2 +0,0 @@
nucleo-f103rb\stm32f1xx_ll_usart.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c
nucleo-f103rb\stm32f1xx_ll_usart.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h

BIN
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_utils.crf
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BIN
MDK-ARM/NUCLEO-F103RB/system_stm32f1xx.crf
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3385
MDK-ARM/Project.uvguix.trocache
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File diff suppressed because one or more lines are too long

178
MDK-ARM/Project.uvoptx
View file

@ -75,7 +75,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -114,7 +114,7 @@
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
@ -130,7 +130,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=100,127,658,622,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=204,363,702,652,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1045,583,1603,1080,0)(121=971,583,1529,1080,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=200,173,988,1026,0)(131=405,227,1193,1080,0)(132=161,47,949,900,0)(133=1013,172,1801,1025,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=320,247,1120,1026,0)(151=1120,301,1920,1080,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -145,7 +145,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</Name>
<Name>-UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -157,41 +157,87 @@
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>47</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219058</Address>
<LineNumber>41</LineNumber>
<EnabledFlag>0</EnabledFlag>
<Address>134220664</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<Filename>..\Services\Accelerometer.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\47</Expression>
<Expression>\\NUCLEO_F103RB\../Services/Accelerometer.c\41</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>44</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219052</Address>
<LineNumber>33</LineNumber>
<EnabledFlag>0</EnabledFlag>
<Address>134231164</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<Filename>..\Services\Accelerometer.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\44</Expression>
<Expression>\\NUCLEO_F103RB\../Services/Accelerometer.c\33</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>33</LineNumber>
<EnabledFlag>0</EnabledFlag>
<Address>134231194</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\Src\Sail.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/Sail.c\33</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>Main_Time</ItemText>
<ItemText>windAngle,0x0A</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>angleDeg,0x0A</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>volts</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>angleRad</ItemText>
</Ww>
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>value,0x0A</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>speed,0x0A</ItemText>
</Ww>
<Ww>
<count>6</count>
<WinNumber>1</WinNumber>
<ItemText>TIMx-&gt;CCR2</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>
@ -200,7 +246,7 @@
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
@ -236,6 +282,12 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<SystemViewers>
<Entry>
<Name>System Viewer\ADC2</Name>
<WinId>35905</WinId>
</Entry>
</SystemViewers>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>0</EnableFlashSeq>
@ -300,7 +352,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -345,7 +397,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=1554,213,1920,450,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=129,555,687,1080,0)(121=1509,217,1920,660,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=150,46,938,969,0)(133=1148,116,1732,908,0)(160=1046,190,1640,699,1)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=130,96,930,1019,0)(151=127,38,927,961,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=1554,213,1920,450,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=129,555,687,1080,0)(121=924,444,1482,969,1)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=150,46,938,969,0)(133=-13,526,775,1449,1)(160=1046,190,1640,699,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=130,96,930,1019,0)(151=127,38,927,961,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -382,89 +434,25 @@
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>20</LineNumber>
<LineNumber>51</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134226220</Address>
<Address>134221038</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>..\Services\RFEmitter.c</Filename>
<Filename>..\Src\Display.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Services/RFEmitter.c\20</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>43</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134231406</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\43</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>82</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134231536</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\82</Expression>
</Bp>
<Bp>
<Number>3</Number>
<Type>0</Type>
<LineNumber>44</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>4</Number>
<Type>0</Type>
<LineNumber>87</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
<Expression>\\NUCLEO_F103RB\../Src/Display.c\51</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>msCounter,0x0A</ItemText>
<ItemText>secCounter</ItemText>
</Ww>
<Ww>
<count>1</count>
@ -515,8 +503,8 @@
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aSer1>1</aSer1>
<aSer2>1</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
@ -525,12 +513,12 @@
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<aSer3>1</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aLa>1</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<aSer4>1</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
@ -553,7 +541,7 @@
<Wi>
<IntNumber>0</IntNumber>
<FirstString>((PORTB &amp; 0x00000100) &gt;&gt; 8 &amp; 0x100) &gt;&gt; 8</FirstString>
<SecondString>FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254422026203078303030303031303029203E3E2038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1700000000000000000000000000000000000000AE110008</SecondString>
<SecondString>FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254422026203078303030303031303029203E3E2038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1200000000000000000000000000000000000000AE110008</SecondString>
</Wi>
</LogicAnalyzers>
<SystemViewers>
@ -634,7 +622,7 @@
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Sail.c</PathWithFileName>

2
MDK-ARM/Project.uvprojx
View file

@ -10,7 +10,7 @@
<TargetName>NUCLEO-F103RB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>8</uAC6>
<TargetOption>
<TargetCommonOption>

20
MDK-ARM/RTE/_NUCLEO-F103RB/RTE_Components.h
View file

@ -1,20 +0,0 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'Project'
* Target: 'NUCLEO-F103RB'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

21
MDK-ARM/RTE/_Simulateur/RTE_Components.h
View file

@ -1,21 +0,0 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Project'
* Target: 'Simulateur'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

6
MyDrivers/ADC.c
View file

@ -19,8 +19,8 @@ void ADC_conf(ADC_TypeDef *adc)
adc->SQR1 &= ADC_SQR1_L;
// Calibration
adc->CR2 |= ADC_CR2_CAL_Msk;
while ((adc->CR2 & ADC_CR2_CAL_Msk));
// adc->CR2 |= ADC_CR2_CAL_Msk;
// while ((adc->CR2 & ADC_CR2_CAL_Msk));
}
@ -43,7 +43,7 @@ uint16_t ADC_readRaw(ADC_TypeDef *adc, int channel)
float ADC_convertToVolt(uint16_t value)
{
return ((double) value) / MAX_CONVERTED_VALUE * MAX_VOLTS;
return ((float) value) / MAX_CONVERTED_VALUE * MAX_VOLTS;
}

57
MyDrivers/Timer.c
View file

@ -44,16 +44,38 @@ void TIM4_IRQHandler(void)
(*it_callback_TIM4)();
}
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Timer_IT_enable(TIM_TypeDef * timer)
{
LL_TIM_EnableIT_UPDATE(timer);
}
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Timer_IT_disable(TIM_TypeDef * timer)
{
LL_TIM_DisableIT_UPDATE(timer);
}
/**
* @brief Configure le Timer consid<EFBFBD>r<EFBFBD> en interruption sur d<EFBFBD>bordement.
* @note A ce stade, les interruptions ne sont pas valid<EFBFBD>s (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction <EFBFBD> lancer sur interruption
* int Prio : priorit<EFBFBD> associ<EFBFBD>e <EFBFBD> l'interruption
* @retval None
*/
void Timer_IT_conf(TIM_TypeDef * timer, void (*it_callback) (void), int prio)
{
// affectation de la fonction
@ -84,16 +106,36 @@ void Timer_IT_conf(TIM_TypeDef * timer, void (*it_callback) (void), int prio)
* TIMER
***************************************************************************/
/**
* @brief D<EFBFBD>marre le timer consid<EFBFBD>r<EFBFBD> et active les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Timer_start(TIM_TypeDef * timer)
{
LL_TIM_EnableCounter(timer);
}
/**
* @brief Arr<EFBFBD>t le timer consid<EFBFBD>r<EFBFBD> et d<EFBFBD>sactive les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Timer_stop(TIM_TypeDef * timer)
{
LL_TIM_DisableCounter(timer);
}
/**
* @brief Active l'horloge et r<EFBFBD>gle l'ARR et le PSC du timer vis<EFBFBD>.
* @note Fonction <EFBFBD> lancer avant toute autre. Le timer n'est pas encore lanc<EFBFBD> (voir Timer_start)
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur <EFBFBD> placer dans ARR
* int Psc : valeur <EFBFBD> placer dans PSC
* @retval None
*/
void Timer_conf(TIM_TypeDef * timer, int arr, int psc)
{
LL_TIM_InitTypeDef init_struct;
@ -143,7 +185,7 @@ void Timer_pwmi_conf(TIM_TypeDef * TIMx, int channel)
// TIM_CCMR1_IC1F_0; Potentiellement utile, à voir plus tard
// On met le channel principal en rising edge, le secondaire en falling edge
TIMx->CCER &= ~TIM_CCER_CC1P;
TIMx->CCER &= ~TIM_CCER_CC1P;
TIMx->CCER |= TIM_CCER_CC2P;
TIMx->SMCR |= TIM_SMCR_TS_0 | TIM_SMCR_TS_2; //101
@ -154,7 +196,7 @@ void Timer_pwmi_conf(TIM_TypeDef * TIMx, int channel)
TIMx->CCMR1 |= TIM_CCMR1_CC1S_1;
TIMx->CCMR1 |= TIM_CCMR1_CC2S_0;
TIMx->CCER |= TIM_CCER_CC1P;
TIMx->CCER |= TIM_CCER_CC1P;
TIMx->CCER &= ~TIM_CCER_CC2P;
TIMx->SMCR |= TIM_SMCR_TS_1 | TIM_SMCR_TS_2; //110
@ -176,9 +218,10 @@ int Timer_pwmi_getPeriod(TIM_TypeDef * TIMx)
return TIMx->CCR1;
}
int Timer_pwmi_getDutyCycle(TIM_TypeDef * TIMx)
{
return TIMx->CCR2;
float Timer_pwmi_getDutyCycle(TIM_TypeDef * TIMx) {
const float arr = (float)LL_TIM_GetAutoReload(TIMx);
float duty_cycle = (float)TIMx->CCR2 / arr;
return duty_cycle;
}
/****************************************************************************
@ -237,7 +280,7 @@ float Timer_pwmo_getDutyCycle(TIM_TypeDef * timer, int channel)
void Timer_encoder_conf(TIM_TypeDef * timer)
{
Timer_conf(timer, 359, 0);
Timer_conf(timer, 719, 0); // 360 * 2 - 1
LL_TIM_ENCODER_InitTypeDef init_struct;
LL_TIM_ENCODER_StructInit(&init_struct);
@ -248,7 +291,7 @@ void Timer_encoder_conf(TIM_TypeDef * timer)
int Timer_encoder_getAngle(TIM_TypeDef * timer)
{
return LL_TIM_GetCounter(timer);
return LL_TIM_GetCounter(timer)/2;
}
enum CounterDirection Timer_encoder_getDirection(TIM_TypeDef * timer)

12
MyDrivers/Timer.h
View file

@ -16,7 +16,7 @@ enum CounterDirection {
/**
* @brief Autorise les interruptions
* @note
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
@ -24,7 +24,7 @@ void Timer_IT_enable(TIM_TypeDef * timer);
/**
* @brief Interdit les interruptions
* @note
* @note
* @param TIM_TypeDef Timer : indique le timer <EFBFBD> utiliser par le chronom<EFBFBD>tre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
@ -77,7 +77,7 @@ void Timer_conf(TIM_TypeDef * timer, int arr, int psc);
/**
* @brief Configure le timer en mode PWM input
* @note
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser : TIM1, TIM2, TIM3 ou TIM4
* int channel : Le channel utilisé par la PWM
* @retval None
@ -86,15 +86,15 @@ void Timer_pwmi_conf(TIM_TypeDef * timer, int channel);
/**
* @brief Récupère le duty cycle de la PWM donnée
* @note
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser
* @retval None
*/
int Timer_pwmi_getDutyCycle(TIM_TypeDef * timer);
float Timer_pwmi_getDutyCycle(TIM_TypeDef * timer);
/**
* @brief Récupère la période de la PWM donnée
* @note
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser
* @retval None
*/

12
Services/DCMotor.c
View file

@ -2,15 +2,23 @@
#include "math.h"
void DCMotor_conf(TIM_TypeDef * timer, int channel, GPIO_TypeDef * gpio, int pin)
{
{
//On règle la vitesse en valeur absolue, ici à 0
Timer_pwmo_conf(timer, channel, 50, 0);
// Configuration du GPIO
GPIO_conf(GPIOA, LL_GPIO_PIN_1, LL_GPIO_MODE_ALTERNATE, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PULL_UP);
//On règle le sens du moteur, ici sens direct (?)
GPIO_conf(gpio, pin, LL_GPIO_MODE_OUTPUT, LL_GPIO_OUTPUT_OPENDRAIN, LL_GPIO_PULL_DOWN);
GPIO_conf(gpio, pin, LL_GPIO_MODE_OUTPUT, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PULL_DOWN);
GPIO_setPin(gpio, pin, 0);
Timer_start(timer);
}
void DCMotor_setSpeed(TIM_TypeDef * timer, int channel, GPIO_TypeDef * gpio, int pin, float speed)
{
const int dir = (speed > 0.) ? 1 : 0;

6
Services/RFReceiver.c
View file

@ -7,9 +7,5 @@ void RFReceiver_conf(TIM_TypeDef * timer, int channel)
float RFReceiver_getData(TIM_TypeDef * timer)
{
const int dutyCycle = Timer_pwmi_getDutyCycle(timer);
const int period = Timer_pwmi_getPeriod(timer);
const float impulseLength = dutyCycle * period;
return (impulseLength -1) * 200 - 100;
return Timer_pwmi_getDutyCycle(timer);
}

6
Services/ServoMotor.c
View file

@ -13,9 +13,13 @@ void ServoMotor_start(TIM_TypeDef * timer)
Timer_start(timer);
}
float convertAngleToDutyCycle(int angle) {
return ((float) angle) / 90.0 / 20 + 0.05;
}
void ServoMotor_setAngle(TIM_TypeDef * timer, int channel, int angle)
{
Timer_pwmo_setDutyCycle(timer, channel, ((float) angle) / 359.0);
Timer_pwmo_setDutyCycle(timer, channel, convertAngleToDutyCycle(angle));
}
int ServoMotor_getAngle(TIM_TypeDef * timer, int channel)

12
Src/Orientation.c
View file

@ -1,7 +1,11 @@
#include "Orientation.h"
#include "math.h"
#define THRESHOLD 30
#define THRESHOLD 0
const float MIN_DUTY_CYCLE = 0.05;
const float ZERO_DUTY_CYCLE = 0.075;
const float MAX_DUTY_CYCLE = 0.1;
// Recepteur
TIM_TypeDef * RECEIVER_TIMER = TIM4;
@ -21,10 +25,12 @@ void Orientation_conf()
void Orientation_background()
{
const float speed = RFReceiver_getData(RECEIVER_TIMER);
const float duty_cycle = RFReceiver_getData(RECEIVER_TIMER);
const float speed = (duty_cycle - ZERO_DUTY_CYCLE) / (MAX_DUTY_CYCLE - ZERO_DUTY_CYCLE);
//Si la vitesse (en valeur absolue) ne dépasse pas un certain seuil, on ne démarre pas le moteur
if (THRESHOLD < fabs(speed)) {
if (THRESHOLD > fabs(speed)) {
DCMotor_setSpeed(DCMOTOR_TIMER, DCMOTOR_CHANNEL, DCMOTOR_GPIO, DCMOTOR_PIN, 0);
}
else {

2
Src/Roll.c
View file

@ -31,7 +31,7 @@ int Roll_getEmergencyState(void)
void Roll_background(void)
{
const int xAngle = Accelerometer_getAngle(ROLL_ADC, ROLL_X_CHANNEL);
const int xAngle = Accelerometer_getAngle(ROLL_ADC, ROLL_Y_CHANNEL);
//const int yAngle = Accelerometer_getAngle(ROLL_ADC, ROLL_Y_CHANNEL);
const int currentState = abs(xAngle) >= 40;

6
Src/Sail.c
View file

@ -30,10 +30,10 @@ void Sail_start()
int windToSailAngle(int windAngle)
{
if (windAngle > 180)
if (windAngle < 180)
return 90 * (windAngle - 45) / 135;
else
return 360 - 90 * ((360 - windAngle) - 45) / 135;
return 90 * ((360 - windAngle) - 45) / 135;
}
int Sail_getSailAngle(void)
@ -59,7 +59,7 @@ void Sail_background()
return;
const int windAngle = IncrementalEncoder_getAngle(ENCODER_TIMER);
if (windAngle < 45 || windAngle > 315)
ServoMotor_setAngle(MOTOR_TIMER, MOTOR_CHANNEL, 0);
else

4
Src/main.c
View file

@ -102,7 +102,7 @@ int main(void)
Scheduler_start();
while (1) {
Display_background(secCounter);
// Display_background(secCounter);
}
@ -151,7 +151,7 @@ void SystemClock_Config(void)
/* Enable HSE oscillator */
// ********* Commenter la ligne ci-dessous pour MCBSTM32 *****************
// ********* Conserver la ligne si Nucléo*********************************
LL_RCC_HSE_EnableBypass();
// LL_RCC_HSE_EnableBypass();
LL_RCC_HSE_Enable();
while(LL_RCC_HSE_IsReady() != 1)
{