processor-2000/registers_test.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY registers_test IS
END registers_test;
 
ARCHITECTURE behavior OF registers_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT registers
    PORT(
         addr_A : IN  std_logic_vector(0 to 3);
         addr_B : IN  std_logic_vector(0 to 3);
         addr_W : IN  std_logic_vector(0 to 3);
         W : IN  std_logic;
         DATA : IN  std_logic_vector(0 to 7);
         RST : IN  std_logic;
         CLK : IN  std_logic;
         QA : OUT  std_logic_vector(0 to 7);
         QB : OUT  std_logic_vector(0 to 7)
        );
    END COMPONENT;
    

   --Inputs
   signal addr_A : std_logic_vector(0 to 3) := (others => '0');
   signal addr_B : std_logic_vector(0 to 3) := (others => '0');
   signal addr_W : std_logic_vector(0 to 3) := (others => '0');
   signal W : std_logic := '0';
   signal DATA : std_logic_vector(0 to 7) := (others => '0');
   signal RST : std_logic := '0';
   signal CLK : std_logic := '0';

 	--Outputs
   signal QA : std_logic_vector(0 to 7);
   signal QB : std_logic_vector(0 to 7);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: registers PORT MAP (
          addr_A => addr_A,
          addr_B => addr_B,
          addr_W => addr_W,
          W => W,
          DATA => DATA,
          RST => RST,
          CLK => CLK,
          QA => QA,
          QB => QB
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

		addr_A <=
		"0000",
		"0010" after 1*CLK_period,
		"0110" after 2*CLK_period,
		"1000" after 3*CLK_period,
		"1100" after 4*CLK_period,
		"0000" after 5*CLK_period,
		"0001" after 6*CLK_period,
		"0010" after 8*CLK_period,
		"1000" after 9*CLK_period,
		"1111" after 11*CLK_period;

		addr_B <=
		"0000",
		"0001" after 1*CLK_period,
		"0111" after 2*CLK_period,
		"1000" after 3*CLK_period,
		"1111" after 4*CLK_period,
		"0001" after 5*CLK_period,
		"1111" after 9*CLK_period,
		"0001" after 11*CLK_period;
		

		addr_W <=
		"0000",
		"0001" after 6*CLK_period,
		"0010" after 7*CLK_period,
		"1000" after 8*CLK_period,
		"1111" after 9*CLK_period;

		DATA <= 
		"01010101",
		"10101010" after 6*CLK_period,
		"00000000" after 7*CLK_period,
		"11111111" after 8*CLK_period,
		"00001111" after 10*CLK_period;
		
		W <=
		'0',
		'1' after 5*CLK_period,
		'0' after 9*CLK_period,
		'1' after 10*CLK_period;
		
		RST <= '1', '0' after 12*CLK_period;
		
      wait;
   end process;

END;